From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D136621A07A80 for ; Mon, 10 Sep 2018 19:03:40 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Sep 2018 19:03:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,358,1531810800"; d="scan'208";a="89339641" Received: from shwdeopenpsi068.ccr.corp.intel.com ([10.239.158.46]) by orsmga001.jf.intel.com with ESMTP; 10 Sep 2018 19:03:39 -0700 From: Star Zeng To: edk2-devel@lists.01.org Cc: Star Zeng , Ruiyu Ni , Jian J Wang , Fei1 Wang Date: Tue, 11 Sep 2018 10:03:37 +0800 Message-Id: <1536631417-39920-1-git-send-email-star.zeng@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 MIME-Version: 1.0 Subject: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Sep 2018 02:03:41 -0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the HSEE in the USBCMD bit is a ‘1’ and the HSE bit in the USBSTS register is a ‘1’, the xHC shall assert out-of-band error signaling to the host and assert the SERR# pin. To prevent masking any potential issues with SERR, this patch is to set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is set. Cc: Ruiyu Ni Cc: Jian J Wang Cc: Fei1 Wang Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng --- MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 41 ++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c index 5f0736a516b6..89f073e1d83f 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -587,6 +587,39 @@ XhcIsSysError ( } /** + Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is set. + + The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Controller Reset(HCRST). + This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set. + + @param Xhc The XHCI Instance. + +**/ +VOID +XhcSetHsee ( + IN USB_XHCI_INSTANCE *Xhc + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT16 XhciCmd; + + PciIo = Xhc->PciIo; + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PCI_COMMAND_OFFSET, + sizeof (XhciCmd), + &XhciCmd + ); + if (!EFI_ERROR (Status)) { + if ((XhciCmd & EFI_PCI_COMMAND_SERR) != 0) { + XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE); + } + } +} + +/** Reset the XHCI host controller. @param Xhc The XHCI Instance. @@ -628,6 +661,14 @@ XhcResetHC ( // gBS->Stall (XHC_1_MILLISECOND); Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout); + + if (!EFI_ERROR (Status)) { + // + // The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST. + // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set. + // + XhcSetHsee (Xhc); + } } return Status; -- 2.7.0.windows.1