From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::142; helo=mail-lf1-x142.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 047F4211350FC for ; Sat, 15 Sep 2018 15:26:06 -0700 (PDT) Received: by mail-lf1-x142.google.com with SMTP id t140-v6so4806676lff.4 for ; Sat, 15 Sep 2018 15:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gDn/glqesa20QlzZmBBbA2VvnZgVijNa0YQWUtiajEs=; b=KtwyeVOugczO/2mls0ygm/n/RpcLDRYbIN6IG3RDLwI+su6Und7zJb4twQhFu8yJxq 090YqCwMAptdLuPG0viBWY5Om6lClO6AqSlj/ESuD0OruJEDTPTXliDPmXvVAf7eKftt bgFT9d2KdMLwTBVgP9O/OC4+tKtCtcNt5cMVSPayxtCoZe6ojBDCvADclkhllWYEnBY+ vvbvManDAZcmyh4JiIWNmTeDbVqBQTOzMFoJ4WXMfgi+IJNKm6LRSEN5aO44E6+2aTp9 cV/vNb9S0WDDaasePPDy31QF1eh7kLpgD6GY4On0/s/tLAEB7krWT+0ZQCWDka8vbogn TJjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gDn/glqesa20QlzZmBBbA2VvnZgVijNa0YQWUtiajEs=; b=Umn4J1+iiBE1u+edu4AP0/tmv+jL87BJ5xqjeWoPDdcTW3h9Z7fHZ3VijhUHplR310 FZZ0fsNr38oaOVaqB5aDK5gzvgt6YEeVIvdGBgITsVNCR99ejIZpP0q7gq7JT5FOkcQ9 61zSGDXe3vkMPFFaOzhXZu2m8dtTcGJJmq2Ccw2qerpYjPJ+ABAguSRJBrAsJDH7V6Ri lr6Rbox/XKsmMybr0l35WWAsbKkJ2CaHMY4QDTq1G8u4k2qVpD0O4UXcOfNUtwwLhwBL 2adDUxtTTBoYmnYKzipTsdosvMfOWJcQruJbjCIrl6QQ9aFJjDbKUql3L+FWERf1wQOu 8s9g== X-Gm-Message-State: APzg51B4Q2LD/N1/kYHoO09ItOZysDCbabVUzRHsVMSTtuHOuw+qPg2Z 6QX41jtL3M6D0ExYyiXxaUkUmcMRpgM= X-Google-Smtp-Source: ANB0VdYU6kxnHqy8887m0MO7TpcblWPfBpqyqdkq8cRwAk92rQNUsORWD7/OeYexZ45RpcFrKEFw+Q== X-Received: by 2002:a19:6b0b:: with SMTP id d11-v6mr10310014lfa.99.1537050364770; Sat, 15 Sep 2018 15:26:04 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id c2-v6sm2044974lfg.45.2018.09.15.15.26.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 15 Sep 2018 15:26:04 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: feng.tian@intel.com, michael.d.kinney@intel.com, liming.gao@intel.com, leif.lindholm@linaro.org, hao.a.wu@intel.com, ard.biesheuvel@linaro.org, nadavh@marvell.com, mw@semihalf.com, jsd@semihalf.com, tm@semihalf.com Date: Sun, 16 Sep 2018 00:25:44 +0200 Message-Id: <1537050346-16445-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537050346-16445-1-git-send-email-mw@semihalf.com> References: <1537050346-16445-1-git-send-email-mw@semihalf.com> Subject: [PATCH v3 1/3] MdeModulePkg/SdMmcPciHcDxe: Adjust eMMC clock and bus width sequence X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 15 Sep 2018 22:26:07 -0000 According to JESD84-B50-1 chapter A.6 (documentation about eMMC4.5 standard) step "Changing the data bus width" (A.6.3) should be executed after step "Switching to high-speed mode" (A.6.2). This patch fixes the bus-width/clock-setting sequence in EmmcSwitchToHighSpeed (). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c index c5fd214..12935ef 100755 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c @@ -745,10 +745,6 @@ EmmcSwitchToHighSpeed ( UINT8 HostCtrl1; UINT8 HostCtrl2; - Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth); - if (EFI_ERROR (Status)) { - return Status; - } // // Set to Hight Speed timing // @@ -783,6 +779,11 @@ EmmcSwitchToHighSpeed ( HsTiming = 1; Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth); return Status; } -- 2.7.4