* [PATCH 0/2] Xhci: Handle value 5 in Port Speed field of PORTSC @ 2018-10-21 4:24 Star Zeng 2018-10-21 4:24 ` [PATCH 1/2] MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision based on SBRN Star Zeng 2018-10-21 4:24 ` [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC Star Zeng 0 siblings, 2 replies; 5+ messages in thread From: Star Zeng @ 2018-10-21 4:24 UTC (permalink / raw) To: edk2-devel; +Cc: Star Zeng, Ruiyu Ni, Hao Wu, Jian J Wang REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1267 Please refer to the log message of each commit for more details. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Star Zeng (2): MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision based on SBRN MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 18 +++++++++++++++++- MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 6 ++++-- MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 6 ++++-- MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h | 6 +++--- 4 files changed, 28 insertions(+), 8 deletions(-) -- 2.7.0.windows.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision based on SBRN 2018-10-21 4:24 [PATCH 0/2] Xhci: Handle value 5 in Port Speed field of PORTSC Star Zeng @ 2018-10-21 4:24 ` Star Zeng 2018-10-22 8:52 ` Ni, Ruiyu 2018-10-21 4:24 ` [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC Star Zeng 1 sibling, 1 reply; 5+ messages in thread From: Star Zeng @ 2018-10-21 4:24 UTC (permalink / raw) To: edk2-devel; +Cc: Star Zeng, Ruiyu Ni, Hao Wu, Jian J Wang Current hard code Usb2Hc.XXXRevision may be not accurate. This patch updates code to assign Usb2Hc.XXXRevision based on SBRN (Serial Bus Release Number, PCI configuration space offset 0x60) although there is no code consuming them. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> --- MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 14 ++++++++++++++ MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c index 48eccf770a35..4796d4611b19 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c @@ -1770,6 +1770,7 @@ XhcCreateUsbHc ( EFI_STATUS Status; UINT32 PageSize; UINT16 ExtCapReg; + UINT8 ReleaseNumber; Xhc = AllocateZeroPool (sizeof (USB_XHCI_INSTANCE)); @@ -1786,6 +1787,19 @@ XhcCreateUsbHc ( Xhc->OriginalPciAttributes = OriginalPciAttributes; CopyMem (&Xhc->Usb2Hc, &gXhciUsb2HcTemplate, sizeof (EFI_USB2_HC_PROTOCOL)); + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint8, + XHC_PCI_SBRN_OFFSET, + 1, + &ReleaseNumber + ); + + if (!EFI_ERROR (Status)) { + Xhc->Usb2Hc.MajorRevision = (ReleaseNumber & 0xF0) >> 4; + Xhc->Usb2Hc.MinorRevision = (ReleaseNumber & 0x0F); + } + InitializeListHead (&Xhc->AsyncIntTransfers); // diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h index 20e7ac0e8f02..feef3a4bd5ef 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h @@ -26,6 +26,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask +#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset + #define USB_HUB_CLASS_CODE 0x09 #define USB_HUB_SUBCLASS_CODE 0x00 -- 2.7.0.windows.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision based on SBRN 2018-10-21 4:24 ` [PATCH 1/2] MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision based on SBRN Star Zeng @ 2018-10-22 8:52 ` Ni, Ruiyu 0 siblings, 0 replies; 5+ messages in thread From: Ni, Ruiyu @ 2018-10-22 8:52 UTC (permalink / raw) To: Zeng, Star, edk2-devel@lists.01.org; +Cc: Wu, Hao A, Wang, Jian J Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Thanks/Ray > -----Original Message----- > From: Zeng, Star > Sent: Sunday, October 21, 2018 12:24 PM > To: edk2-devel@lists.01.org > Cc: Zeng, Star <star.zeng@intel.com>; Ni, Ruiyu <ruiyu.ni@intel.com>; Wu, > Hao A <hao.a.wu@intel.com>; Wang, Jian J <jian.j.wang@intel.com> > Subject: [PATCH 1/2] MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision > based on SBRN > > Current hard code Usb2Hc.XXXRevision may be not accurate. > This patch updates code to assign Usb2Hc.XXXRevision based on SBRN (Serial > Bus Release Number, PCI configuration space offset > 0x60) although there is no code consuming them. > > Cc: Ruiyu Ni <ruiyu.ni@intel.com> > Cc: Hao Wu <hao.a.wu@intel.com> > Cc: Jian J Wang <jian.j.wang@intel.com> > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng <star.zeng@intel.com> > --- > MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 14 ++++++++++++++ > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 2 ++ > 2 files changed, 16 insertions(+) > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > index 48eccf770a35..4796d4611b19 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > @@ -1770,6 +1770,7 @@ XhcCreateUsbHc ( > EFI_STATUS Status; > UINT32 PageSize; > UINT16 ExtCapReg; > + UINT8 ReleaseNumber; > > Xhc = AllocateZeroPool (sizeof (USB_XHCI_INSTANCE)); > > @@ -1786,6 +1787,19 @@ XhcCreateUsbHc ( > Xhc->OriginalPciAttributes = OriginalPciAttributes; > CopyMem (&Xhc->Usb2Hc, &gXhciUsb2HcTemplate, sizeof > (EFI_USB2_HC_PROTOCOL)); > > + Status = PciIo->Pci.Read ( > + PciIo, > + EfiPciIoWidthUint8, > + XHC_PCI_SBRN_OFFSET, > + 1, > + &ReleaseNumber > + ); > + > + if (!EFI_ERROR (Status)) { > + Xhc->Usb2Hc.MajorRevision = (ReleaseNumber & 0xF0) >> 4; > + Xhc->Usb2Hc.MinorRevision = (ReleaseNumber & 0x0F); } > + > InitializeListHead (&Xhc->AsyncIntTransfers); > > // > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > index 20e7ac0e8f02..feef3a4bd5ef 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > @@ -26,6 +26,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY > KIND, EITHER EXPRESS OR IMPLIED. > #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset > #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask > > +#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number > Register Offset > + > #define USB_HUB_CLASS_CODE 0x09 > #define USB_HUB_SUBCLASS_CODE 0x00 > > -- > 2.7.0.windows.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC 2018-10-21 4:24 [PATCH 0/2] Xhci: Handle value 5 in Port Speed field of PORTSC Star Zeng 2018-10-21 4:24 ` [PATCH 1/2] MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision based on SBRN Star Zeng @ 2018-10-21 4:24 ` Star Zeng 2018-10-22 8:52 ` Ni, Ruiyu 1 sibling, 1 reply; 5+ messages in thread From: Star Zeng @ 2018-10-21 4:24 UTC (permalink / raw) To: edk2-devel; +Cc: Star Zeng, Ruiyu Ni, Hao Wu, Jian J Wang REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1267 The value 5 Port Speed field of PORTSC is new defined in XHCI 1.1 spec November 2017. This patch updates XhciDxe and XhciPei to handle it, otherwise the USB 3.1 device may not be recognized with the XHCI controller following XHCI 1.1 spec November 2017. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> --- MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 4 +++- MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 4 ++-- MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 6 ++++-- MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h | 6 +++--- 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c index 4796d4611b19..f1c60bef01c0 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c @@ -403,7 +403,8 @@ XhcGetRootHubPortStatus ( State = XhcReadOpReg (Xhc, Offset); // - // According to XHCI 1.0 spec, bit 10~13 of the root port status register identifies the speed of the attached device. + // According to XHCI 1.1 spec November 2017, + // bit 10~13 of the root port status register identifies the speed of the attached device. // switch ((State & XHC_PORTSC_PS) >> 10) { case 2: @@ -415,6 +416,7 @@ XhcGetRootHubPortStatus ( break; case 4: + case 5: PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED; break; diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h index feef3a4bd5ef..ac14b7426fe7 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h @@ -2,7 +2,7 @@ This file contains the register definition of XHCI host controller. -Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -171,7 +171,7 @@ typedef union { #define XHC_PORTSC_RESET BIT4 // Port Reset #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State #define XHC_PORTSC_PP BIT9 // Port Power -#define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // Port Speed +#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe #define XHC_PORTSC_CSC BIT17 // Connect Status Change #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c index ee4d1f97bd04..e45da34a456e 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c @@ -2,7 +2,7 @@ PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid which is used to enable recovery function from USB Drivers. -Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions @@ -1317,7 +1317,8 @@ XhcPeiGetRootHubPortStatus ( DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: Port: %x State: %x\n", PortNumber, State)); // - // According to XHCI 1.0 spec, bit 10~13 of the root port status register identifies the speed of the attached device. + // According to XHCI 1.1 spec November 2017, + // bit 10~13 of the root port status register identifies the speed of the attached device. // switch ((State & XHC_PORTSC_PS) >> 10) { case 2: @@ -1329,6 +1330,7 @@ XhcPeiGetRootHubPortStatus ( break; case 4: + case 5: PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED; break; diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h index 3787aeccf55f..07aeb81f2a95 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h @@ -1,7 +1,7 @@ /** @file Private Header file for Usb Host Controller PEIM -Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions @@ -82,9 +82,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled #define XHC_PORTSC_OCA BIT3 // Over-current Active #define XHC_PORTSC_RESET BIT4 // Port Reset -#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State +#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State #define XHC_PORTSC_PP BIT9 // Port Power -#define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // Port Speed +#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe #define XHC_PORTSC_CSC BIT17 // Connect Status Change #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change -- 2.7.0.windows.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC 2018-10-21 4:24 ` [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC Star Zeng @ 2018-10-22 8:52 ` Ni, Ruiyu 0 siblings, 0 replies; 5+ messages in thread From: Ni, Ruiyu @ 2018-10-22 8:52 UTC (permalink / raw) To: Zeng, Star, edk2-devel@lists.01.org; +Cc: Wu, Hao A, Wang, Jian J Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Thanks/Ray > -----Original Message----- > From: Zeng, Star > Sent: Sunday, October 21, 2018 12:24 PM > To: edk2-devel@lists.01.org > Cc: Zeng, Star <star.zeng@intel.com>; Ni, Ruiyu <ruiyu.ni@intel.com>; Wu, > Hao A <hao.a.wu@intel.com>; Wang, Jian J <jian.j.wang@intel.com> > Subject: [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field > of PORTSC > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1267 > > The value 5 Port Speed field of PORTSC is new defined in > XHCI 1.1 spec November 2017. > > This patch updates XhciDxe and XhciPei to handle it, otherwise > the USB 3.1 device may not be recognized with the XHCI controller > following XHCI 1.1 spec November 2017. > > Cc: Ruiyu Ni <ruiyu.ni@intel.com> > Cc: Hao Wu <hao.a.wu@intel.com> > Cc: Jian J Wang <jian.j.wang@intel.com> > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng <star.zeng@intel.com> > --- > MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 4 +++- > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 4 ++-- > MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 6 ++++-- > MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h | 6 +++--- > 4 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > index 4796d4611b19..f1c60bef01c0 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > @@ -403,7 +403,8 @@ XhcGetRootHubPortStatus ( > State = XhcReadOpReg (Xhc, Offset); > > // > - // According to XHCI 1.0 spec, bit 10~13 of the root port status register > identifies the speed of the attached device. > + // According to XHCI 1.1 spec November 2017, > + // bit 10~13 of the root port status register identifies the speed of the > attached device. > // > switch ((State & XHC_PORTSC_PS) >> 10) { > case 2: > @@ -415,6 +416,7 @@ XhcGetRootHubPortStatus ( > break; > > case 4: > + case 5: > PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED; > break; > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > index feef3a4bd5ef..ac14b7426fe7 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > @@ -2,7 +2,7 @@ > > This file contains the register definition of XHCI host controller. > > -Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR> > This program and the accompanying materials > are licensed and made available under the terms and conditions of the BSD > License > which accompanies this distribution. The full text of the license may be > found at > @@ -171,7 +171,7 @@ typedef union { > #define XHC_PORTSC_RESET BIT4 // Port Reset > #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link > State > #define XHC_PORTSC_PP BIT9 // Port Power > -#define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // Port Speed > +#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port > Speed > #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe > #define XHC_PORTSC_CSC BIT17 // Connect Status Change > #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c > b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c > index ee4d1f97bd04..e45da34a456e 100644 > --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c > +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c > @@ -2,7 +2,7 @@ > PEIM to produce gPeiUsb2HostControllerPpiGuid based on > gPeiUsbControllerPpiGuid > which is used to enable recovery function from USB Drivers. > > -Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR> > > This program and the accompanying materials > are licensed and made available under the terms and conditions > @@ -1317,7 +1317,8 @@ XhcPeiGetRootHubPortStatus ( > DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: Port: %x > State: %x\n", PortNumber, State)); > > // > - // According to XHCI 1.0 spec, bit 10~13 of the root port status register > identifies the speed of the attached device. > + // According to XHCI 1.1 spec November 2017, > + // bit 10~13 of the root port status register identifies the speed of the > attached device. > // > switch ((State & XHC_PORTSC_PS) >> 10) { > case 2: > @@ -1329,6 +1330,7 @@ XhcPeiGetRootHubPortStatus ( > break; > > case 4: > + case 5: > PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED; > break; > > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h > b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h > index 3787aeccf55f..07aeb81f2a95 100644 > --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h > +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h > @@ -1,7 +1,7 @@ > /** @file > Private Header file for Usb Host Controller PEIM > > -Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR> > > This program and the accompanying materials > are licensed and made available under the terms and conditions > @@ -82,9 +82,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY > KIND, EITHER EXPRESS OR IMPLIED. > #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled > #define XHC_PORTSC_OCA BIT3 // Over-current Active > #define XHC_PORTSC_RESET BIT4 // Port Reset > -#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State > +#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link > State > #define XHC_PORTSC_PP BIT9 // Port Power > -#define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // Port Speed > +#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed > #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe > #define XHC_PORTSC_CSC BIT17 // Connect Status Change > #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change > -- > 2.7.0.windows.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-10-22 8:53 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-10-21 4:24 [PATCH 0/2] Xhci: Handle value 5 in Port Speed field of PORTSC Star Zeng 2018-10-21 4:24 ` [PATCH 1/2] MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision based on SBRN Star Zeng 2018-10-22 8:52 ` Ni, Ruiyu 2018-10-21 4:24 ` [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC Star Zeng 2018-10-22 8:52 ` Ni, Ruiyu
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