From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=chandni.cherukuri@arm.com; receiver=edk2-devel@lists.01.org Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id 1851921188C53 for ; Fri, 2 Nov 2018 09:37:36 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B9EA2A78; Fri, 2 Nov 2018 09:37:35 -0700 (PDT) Received: from usa.arm.com (a73437-lin.blr.arm.com [10.162.0.155]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 322DF3F718; Fri, 2 Nov 2018 09:37:33 -0700 (PDT) From: Chandni Cherukuri To: edk2-devel@lists.01.org Date: Fri, 2 Nov 2018 22:06:52 +0530 Message-Id: <1541176613-2539-5-git-send-email-chandni.cherukuri@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541176613-2539-1-git-send-email-chandni.cherukuri@arm.com> References: <1541176613-2539-1-git-send-email-chandni.cherukuri@arm.com> Subject: [PATCH edk2-platforms 4/5] Platform/ARM/Sgi: Add ACPI tables for SGI-Clark.Helios platform X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Nov 2018 16:37:36 -0000 X-List-Received-Date: Fri, 02 Nov 2018 16:37:36 -0000 X-List-Received-Date: Fri, 02 Nov 2018 16:37:36 -0000 X-List-Received-Date: Fri, 02 Nov 2018 16:37:36 -0000 X-List-Received-Date: Fri, 02 Nov 2018 16:37:36 -0000 X-List-Received-Date: Fri, 02 Nov 2018 16:37:36 -0000 X-List-Received-Date: Fri, 02 Nov 2018 16:37:36 -0000 X-List-Received-Date: Fri, 02 Nov 2018 16:37:36 -0000 X-List-Received-Date: Fri, 02 Nov 2018 16:37:36 -0000 X-List-Received-Date: Fri, 02 Nov 2018 16:37:36 -0000 Added ACPI tables and GUID name 'gSgiClarkHeliosAcpiTablesFileGuid' for SGI-Clark.Helios platform. Change-Id: Ib212c0b27ad1f9f709385ac92e5e06b1bd33bfc0 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chandni Cherukuri --- Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/AcpiTables.inf | 58 +++++ Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Dbg2.aslc | 90 +++++++ Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Dsdt.asl | 262 +++++++++++++++++++ Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Fadt.aslc | 87 +++++++ Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Gtdt.aslc | 152 +++++++++++ Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Iort.aslc | 106 ++++++++ Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Madt.aslc | 266 ++++++++++++++++++++ Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Mcfg.aslc | 61 +++++ Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Spcr.aslc | 77 ++++++ Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Ssdt.asl | 95 +++++++ Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf | 1 + Platform/ARM/SgiPkg/SgiPlatform.dec | 1 + Platform/ARM/SgiPkg/SgiPlatform.dsc | 1 + Platform/ARM/SgiPkg/SgiPlatform.fdf | 1 + 14 files changed, 1258 insertions(+) diff --git a/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/AcpiTables.inf new file mode 100644 index 0000000..63ebf55 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/AcpiTables.inf @@ -0,0 +1,58 @@ +## @file +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2018, ARM Ltd. All rights reserved. +# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SgiClarkHeliosAcpiTables + FILE_GUID = 2af40815-a84e-4de9-8c38-9140b3544073 + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + Dbg2.aslc + Dsdt.asl + Fadt.aslc + Gtdt.aslc + Iort.aslc + Madt.aslc + Mcfg.aslc + Spcr.aslc + Ssdt.asl + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/SgiPkg/SgiPlatform.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdClusterCount + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase + gArmPlatformTokenSpaceGuid.PL011UartInterrupt + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress diff --git a/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Dbg2.aslc b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Dbg2.aslc new file mode 100644 index 0000000..3970461 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Dbg2.aslc @@ -0,0 +1,90 @@ +/** @file +* Debug Port Table 2 (DBG2) +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "SgiAcpiHeader.h" +#include +#include +#include + +#define SGI_DBG2_NUM_DEBUG_PORTS 1 +#define SGI_DBG2_NUM_GAS 1 +#define SGI_DBG2_NS_STR_LENGTH 8 +#define SGI_PL011_REGISTER_SPACE 0x1000 + +#define NAME_STR_UART1 {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'} + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[SGI_DBG2_NS_STR_LENGTH]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo[SGI_DBG2_NUM_DEBUG_PORTS]; +} DBG2_TABLE; + +#pragma pack() + +#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \ + { \ + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision */ \ + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length */ \ + NumReg, /* UINT8 NumberofGenericAddressRegisters */ \ + SGI_DBG2_NS_STR_LENGTH, /* UINT16 NameSpaceStringLength */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset */ \ + 0, /* UINT16 OemDataLength */ \ + 0, /* UINT16 OemDataOffset */ \ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type */ \ + SubType, /* UINT16 Port Subtype */ \ + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, /* UINT8 Reserved[2] */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset */ \ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset */ \ + }, \ + ARM_GAS32 (UartBase), /* EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \ + UartAddrLen, /* UINT32 AddressSize */ \ + UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \ +} + +STATIC DBG2_TABLE Dbg2 = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + SGI_DBG2_NUM_DEBUG_PORTS + }, + { + // Kernel Debug Port + DBG2_DEBUG_PORT_DDI ( + SGI_DBG2_NUM_GAS, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART, + FixedPcdGet64 (PcdSerialDbgRegisterBase), + SGI_PL011_REGISTER_SPACE, + NAME_STR_UART1 + ) + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Dsdt.asl new file mode 100644 index 0000000..706fd88 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Dsdt.asl @@ -0,0 +1,262 @@ +/** @file +* Differentiated System Description Table Fields (DSDT) +* +* Copyright (c) 2018, ARM Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "ARMLTD", "SGI-ClarkH", + EFI_ACPI_ARM_OEM_REVISION) { + Scope (_SB) { + // + // HeliosCores 8X2 Processor declaration + // + Device (CP00) { // HeliosCore: Cluster 0, Cpu 0, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 0) + Name (_STA, 0xF) + } + + Device (CP01) { // HeliosCore: Cluster 0, Cpu 0, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 1) + Name (_STA, 0xF) + } + + Device (CP02) { // HeliosCore: Cluster 0, Cpu 1, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 2) + Name (_STA, 0xF) + } + + Device (CP03) { // HeliosCore: Cluster 0, Cpu 1, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 3) + Name (_STA, 0xF) + } + + Device (CP04) { // HeliosCore: Cluster 0, Cpu 2, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 4) + Name (_STA, 0xF) + } + + Device (CP05) { // HeliosCore: Cluster 0, Cpu 2, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 5) + Name (_STA, 0xF) + } + + Device (CP06) { // HeliosCore: Cluster 0, Cpu 3, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 6) + Name (_STA, 0xF) + } + + Device (CP07) { // HeliosCore: Cluster 0, Cpu 3, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 7) + Name (_STA, 0xF) + } + + Device (CP08) { // HeliosCore: Cluster 0, Cpu 4, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 8) + Name (_STA, 0xF) + } + + Device (CP09) { // HeliosCore: Cluster 0, Cpu 4, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 9) + Name (_STA, 0xF) + } + + Device (CP10) { // HeliosCore: Cluster 0, Cpu 5, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 10) + Name (_STA, 0xF) + } + + Device (CP11) { // HeliosCore: Cluster 0, Cpu 5, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 11) + Name (_STA, 0xF) + } + + Device (CP12) { // HeliosCore: Cluster 0, Cpu 6, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 12) + Name (_STA, 0xF) + } + + Device (CP13) { // HeliosCore: Cluster 0, Cpu 6, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 13) + Name (_STA, 0xF) + } + + Device (CP14) { // HeliosCore: Cluster 0, Cpu 7, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 14) + Name (_STA, 0xF) + } + + Device (CP15) { // HeliosCore: Cluster 0, Cpu 7, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 15) + Name (_STA, 0xF) + } + + Device (CP16) { // HeliosCore: Cluster 0, Cpu 0, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 16) + Name (_STA, 0xF) + } + + Device (CP17) { // HeliosCore: Cluster 0, Cpu 0, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 17) + Name (_STA, 0xF) + } + + Device (CP18) { // HeliosCore: Cluster 0, Cpu 1, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 18) + Name (_STA, 0xF) + } + + Device (CP19) { // HeliosCore: Cluster 0, Cpu 1, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 19) + Name (_STA, 0xF) + } + + Device (CP20) { // HeliosCore: Cluster 0, Cpu 2, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 20) + Name (_STA, 0xF) + } + + Device (CP21) { // HeliosCore: Cluster 0, Cpu 2, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 21) + Name (_STA, 0xF) + } + + Device (CP22) { // HeliosCore: Cluster 0, Cpu 3, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 22) + Name (_STA, 0xF) + } + + Device (CP23) { // HeliosCore: Cluster 0, Cpu 3, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 23) + Name (_STA, 0xF) + } + + Device (CP24) { // HeliosCore: Cluster 0, Cpu 4, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 24) + Name (_STA, 0xF) + } + + Device (CP25) { // HeliosCore: Cluster 0, Cpu 4, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 25) + Name (_STA, 0xF) + } + + Device (CP26) { // HeliosCore: Cluster 0, Cpu 5, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 26) + Name (_STA, 0xF) + } + + Device (CP27) { // HeliosCore: Cluster 0, Cpu 5, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 27) + Name (_STA, 0xF) + } + + Device (CP28) { // HeliosCore: Cluster 0, Cpu 6, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 28) + Name (_STA, 0xF) + } + + Device (CP29) { // HeliosCore: Cluster 0, Cpu 6, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 29) + Name (_STA, 0xF) + } + + Device (CP30) { // HeliosCore: Cluster 0, Cpu 7, Thread 0 + Name (_HID, "ACPI0007") + Name (_UID, 30) + Name (_STA, 0xF) + } + + Device (CP31) { // HeliosCore: Cluster 0, Cpu 7, Thread 1 + Name (_HID, "ACPI0007") + Name (_UID, 31) + Name (_STA, 0xF) + } + + // UART PL011 + Device (COM0) { + Name (_HID, "ARMH0011") + Name (_CID, "ARMH0011") + Name (_UID, Zero) + Name (_STA, 0xF) + Name (_CRS, ResourceTemplate() { + Memory32Fixed ( + ReadWrite, + FixedPcdGet64 (PcdSerialDbgRegisterBase), + 0x1000 + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 147 } + }) + } + + // SMSC 91C111 + Device (ETH0) { + Name (_HID, "LNRO0003") + Name (_UID, Zero) + Name (_STA, 0xF) + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x18000000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 111 } + }) + Name (_DSD, Package() { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) {"reg-io-width", 4 }, + } + }) + } + + // VIRTIO DISK + Device (VR00) { + Name (_HID, "LNRO0005") + Name (_UID, 0) + Name (_CCA, 1) // mark the device coherent + + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x1c130000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 202 } + }) + } + } // Scope(_SB) +} diff --git a/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Fadt.aslc b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Fadt.aslc new file mode 100644 index 0000000..35b3ec8 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Fadt.aslc @@ -0,0 +1,87 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "SgiAcpiHeader.h" +#include +#include + +STATIC EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ARM_ACPI_HEADER ( + EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_6_2_HW_REDUCED_ACPI | EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // GAS ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_2_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // GAS XPm1aEvtBlk + NULL_GAS, // GAS XPm1bEvtBlk + NULL_GAS, // GAS XPm1aCntBlk + NULL_GAS, // GAS XPm1bCntBlk + NULL_GAS, // GAS XPm2CntBlk + NULL_GAS, // GAS XPmTmrBlk + NULL_GAS, // GAS XGpe0Blk + NULL_GAS, // GAS XGpe1Blk + NULL_GAS, // GAS SleepControlReg + NULL_GAS, // GAS SleepStatusReg + 0 // UINT64 HypervisorVendorIdentity; +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Gtdt.aslc b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Gtdt.aslc new file mode 100644 index 0000000..d7105f3 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Gtdt.aslc @@ -0,0 +1,152 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "SgiAcpiHeader.h" +#include +#include +#include + +#define SGI_PLATFORM_WATCHDOG_COUNT 2 +#define SGI_PLATFORM_TIMER_COUNT (SGI_PLATFORM_WATCHDOG_COUNT + 1) +#define SGI_TIMER_FRAMES_COUNT 2 + +#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#define GTDT_GLOBAL_FLAGS 0 +#define GTDT_GTIMER_FLAGS EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY + +#define SGI_GT_BLOCK_CTL_BASE 0x2A810000 +#define SGI_GT_BLOCK_FRAME1_CTL_BASE 0x2A820000 +#define SGI_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define SGI_GT_BLOCK_FRAME1_GSIV 0x5B + +#define SGI_GT_BLOCK_FRAME0_CTL_BASE 0x2A830000 +#define SGI_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF +#define SGI_GT_BLOCK_FRAME0_GSIV 0x5C + +#define SGI_GTX_TIMER_FLAGS 0 +#define GTX_TIMER_SECURE EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER +#define GTX_TIMER_NON_SECURE 0 +#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY +#define SGI_GTX_COMMON_FLAGS_S (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_SECURE) +#define SGI_GTX_COMMON_FLAGS_NS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_NON_SECURE) + +#define EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( \ + RefreshFramePhysicalAddress, ControlFramePhysicalAddress, \ + WatchdogTimerGSIV, WatchdogTimerFlags) \ + { \ + EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG, \ + sizeof (EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \ + EFI_ACPI_RESERVED_WORD, \ + RefreshFramePhysicalAddress, \ + ControlFramePhysicalAddress, \ + WatchdogTimerGSIV, \ + WatchdogTimerFlags \ + } + +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE GtBlock; + EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[SGI_TIMER_FRAMES_COUNT]; + EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[SGI_PLATFORM_WATCHDOG_COUNT]; +} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES; + +#pragma pack () + +STATIC EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress + SGI_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount + sizeof (EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + }, + { + EFI_ACPI_6_2_GTDT_GT_BLOCK, // UINT8 Type + sizeof (EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE) + // UINT16 Length + sizeof (EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE) * + SGI_TIMER_FRAMES_COUNT, + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved + SGI_GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase + SGI_TIMER_FRAMES_COUNT, // UINT32 GTBlockTimerCount + sizeof (EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset + }, + { + { + 0, // UINT8 GTFrameNumber + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, // UINT8 Reserved[3] + SGI_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 CntBaseX + SGI_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 CntEL0BaseX + SGI_GT_BLOCK_FRAME0_GSIV, // UINT32 GTxPhysicalTimerGSIV + SGI_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags + 0, // UINT32 GTxVirtualTimerGSIV + 0, // UINT32 GTxVirtualTimerFlags + SGI_GTX_COMMON_FLAGS_NS // UINT32 GTxCommonFlags + }, + { + 1, // UINT8 GTFrameNumber + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, // UINT8 Reserved[3] + SGI_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 CntBaseX + SGI_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 CntEL0BaseX + SGI_GT_BLOCK_FRAME1_GSIV, // UINT32 GTxPhysicalTimerGSIV + SGI_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags + 0, // UINT32 GTxVirtualTimerGSIV + 0, // UINT32 GTxVirtualTimerFlags + SGI_GTX_COMMON_FLAGS_S // UINT32 GTxCommonFlags + } + }, + { + EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT ( + FixedPcdGet32 (PcdGenericWatchdogRefreshBase), + FixedPcdGet32 (PcdGenericWatchdogControlBase), + 93, + 0 + ), + EFI_ACPI_6_2_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT ( + FixedPcdGet32 (PcdGenericWatchdogRefreshBase), + FixedPcdGet32 (PcdGenericWatchdogControlBase), + 94, + EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER + ) + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; diff --git a/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Iort.aslc b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Iort.aslc new file mode 100644 index 0000000..47c095f --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Iort.aslc @@ -0,0 +1,106 @@ +/** @file +* I/O Remapping Table (Iort) +* +* Copyright (c) 2018, ARM Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include "SgiAcpiHeader.h" + +#pragma pack(1) + +typedef struct +{ + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode; + UINT32 ItsIdentifiers; +} ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE; + +typedef struct +{ + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMap; +} ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE; + +typedef struct +{ + EFI_ACPI_6_0_IO_REMAPPING_TABLE Header; + ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode; + ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; +} ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE; + +#pragma pack () + +ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort = +{ + // EFI_ACPI_6_0_IO_REMAPPING_TABLE + { + ARM_ACPI_HEADER // EFI_ACPI_DESCRIPTION_HEADER + ( + EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE, + ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION + ), + 2, // NumNodes + sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, + // ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_NODE + { + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type + sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE), // Length + 0, // Revision + 0, // Reserved + 0, // NumIdMappings + 0 // IdReference + }, + 1 // GIC ITS Identifiers + }, + 0 + }, + // ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_RC_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_NODE + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE), // Length + 0, // Revision + 0, // Reserved + 1, // NumIdMappings + OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE, RcIdMap), + }, + 1, // CacheCoherent + 0, // AllocationHints + 0, // Reserved + 0, // MemoryAccessFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute + 0x0 // PciSegmentNumber + }, + // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE + { + 0x0000, // InputBase + 0xffff, // NumIds + 0x0000, // OutputBase + OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode), + 0 // Flags + } + } +}; + +VOID* CONST ReferenceAcpiTable = &Iort; diff --git a/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Madt.aslc new file mode 100644 index 0000000..0d66d8a --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Madt.aslc @@ -0,0 +1,266 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" +#include +#include +#include +#include + +// EFI_ACPI_6_2_GIC_STRUCTURE +#define EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, \ + PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency) \ + { \ + EFI_ACPI_6_2_GIC, /* Type */ \ + sizeof (EFI_ACPI_6_2_GIC_STRUCTURE), /* Length */ \ + EFI_ACPI_RESERVED_WORD, /* Reserved */ \ + GicId, /* CPUInterfaceNumber */ \ + AcpiCpuUid, /* AcpiProcessorUid */ \ + Flags, /* Flags */ \ + 0, /* ParkingProtocolVersion */ \ + PmuIrq, /* PerformanceInterruptGsiv */ \ + 0, /* ParkedAddress */ \ + GicBase, /* PhysicalBaseAddress */ \ + GicVBase, /* GICV */ \ + GicHBase, /* GICH */ \ + GsivId, /* VGICMaintenanceInterrupt */ \ + GicRBase, /* GICRBaseAddress */ \ + Mpidr, /* MPIDR */ \ + Efficiency, /* ProcessorPowerEfficiencyClass */ \ + { \ + EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \ + EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \ + EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \ + } \ + } + +// EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE +#define EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, \ + GicDistVector, GicVersion) \ + { \ + EFI_ACPI_6_2_GICD, /* Type */ \ + sizeof (EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE), \ + EFI_ACPI_RESERVED_WORD, /* Reserved1 */ \ + GicDistHwId, /* GicId */ \ + GicDistBase, /* PhysicalBaseAddress */ \ + GicDistVector, /* SystemVectorBase */ \ + GicVersion, /* GicVersion */ \ + { \ + EFI_ACPI_RESERVED_BYTE, /* Reserved2[0] */ \ + EFI_ACPI_RESERVED_BYTE, /* Reserved2[1] */ \ + EFI_ACPI_RESERVED_BYTE /* Reserved2[2] */ \ + } \ + } + +// EFI_ACPI_6_2_GICR_STRUCTURE +#define EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \ + { \ + EFI_ACPI_6_2_GICR, /* Type */ \ + sizeof (EFI_ACPI_6_2_GICR_STRUCTURE), /* Length */ \ + EFI_ACPI_RESERVED_WORD, /* Reserved */ \ + RedisRegionAddr, /* DiscoveryRangeBaseAddress */ \ + RedisDiscLength /* DiscoveryRangeLength */ \ + } + +// EFI_ACPI_6_2_GIC_ITS_STRUCTURE +#define EFI_ACPI_6_2_GIC_ITS_INIT(GicItsId, GicItsBase) \ + { \ + EFI_ACPI_6_2_GIC_ITS, /* Type */ \ + sizeof (EFI_ACPI_6_2_GIC_ITS_STRUCTURE), \ + EFI_ACPI_RESERVED_WORD, /* Reserved */ \ + GicItsId, /* GicItsId */ \ + GicItsBase, /* PhysicalBaseAddress */ \ + EFI_ACPI_RESERVED_DWORD /* DiscoveryRangeLength */ \ + } + +// Multiple APIC Description Table +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[32]; + EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts; +} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // MADT specific fields + 0, // LocalApicAddress + 0 // Flags + }, + { + // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, + // PmuIrq, GicBase, GicVBase, + // GicHBase, GsivId, GicRBase, + // Efficiency) + // Note: The GIC Structure of the primary CPU must be the first entry + // (see note in 5.2.12.14 GICC Structure of ACPI v6.2). + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0 + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0 + 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 3, GET_MPID(0x0, 0x101), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-0 + 0, 4, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-1 + 0, 5, GET_MPID(0x0, 0x201), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-0 + 0, 6, GET_MPID(0x0, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-1 + 0, 7, GET_MPID(0x0, 0x301), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-0 + 0, 8, GET_MPID(0x0, 0x400), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-1 + 0, 9, GET_MPID(0x0, 0x401), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-0 + 0, 10, GET_MPID(0x0, 0x500), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-1 + 0, 11, GET_MPID(0x0, 0x501), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-0 + 0, 12, GET_MPID(0x0, 0x600), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-1 + 0, 13, GET_MPID(0x0, 0x601), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-0 + 0, 14, GET_MPID(0x0, 0x700), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-1 + 0, 15, GET_MPID(0x0, 0x701), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + //Cluster 1 + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0 + 0, 16, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 17, GET_MPID(0x100, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0 + 0, 18, GET_MPID(0x100, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1 + 0, 19, GET_MPID(0x100, 0x101), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-0 + 0, 20, GET_MPID(0x100, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-2 Thread-1 + 0, 21, GET_MPID(0x100, 0x201), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-0 + 0, 22, GET_MPID(0x100, 0x300), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-3 Thread-1 + 0, 23, GET_MPID(0x100, 0x301), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-0 + 0, 24, GET_MPID(0x100, 0x400), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-4 Thread-1 + 0, 25, GET_MPID(0x100, 0x401), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-0 + 0, 26, GET_MPID(0x100, 0x500), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-5 Thread-1 + 0, 27, GET_MPID(0x100, 0x501), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-0 + 0, 28, GET_MPID(0x100, 0x600), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-6 Thread-1 + 0, 29, GET_MPID(0x100, 0x601), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-0 + 0, 30, GET_MPID(0x100, 0x700), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-7 Thread-1 + 0, 31, GET_MPID(0x100, 0x701), EFI_ACPI_6_2_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + }, + // GIC Distributor Entry + EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), + 0, 3), + // GIC Redistributor + EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase), + SIZE_8MB), + // GIC ITS + EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000) +}; + +// +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Mcfg.aslc b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Mcfg.aslc new file mode 100644 index 0000000..b711c72 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Mcfg.aslc @@ -0,0 +1,61 @@ +/** @file +* Memory mapped configuration space base address description table (MCFG) +* +* Copyright (c) 2018, ARM Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include "SgiAcpiHeader.h" +#include "SgiPlatform.h" + +#include +#include +#include + +#pragma pack(1) + +typedef struct +{ + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[1]; +} EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; + +#pragma pack() + +EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION + ), + EFI_ACPI_RESERVED_QWORD // Reserved + }, + { + // PCIe ECAM + { + FixedPcdGet64 (PcdPciExpressBaseAddress), // Base Address + 0x0, // Segment Group Number + FixedPcdGet32 (PcdPciBusMin), // Start Bus Number + FixedPcdGet32 (PcdPciBusMax), // End Bus Number + 0x00000000 // Reserved + } + } +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Spcr.aslc b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Spcr.aslc new file mode 100644 index 0000000..0aa1c3e --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Spcr.aslc @@ -0,0 +1,77 @@ +/** @file +* Serial Port Console Redirection Table (SPCR) +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "SgiAcpiHeader.h" +#include +#include +#include + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + ARM_ACPI_HEADER ( + EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION + ), + // UINT8 InterfaceType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, + // UINT8 Reserved1[3]; + { + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress; + ARM_GAS32 (FixedPcdGet64 (PcdSerialDbgRegisterBase)), + // UINT8 InterruptType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + // UINT8 Irq; + 0, + // UINT32 GlobalSystemInterrupt; + FixedPcdGet32 (PL011UartInterrupt), + // UINT8 BaudRate; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, + // UINT8 Parity; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // UINT8 StopBits; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // UINT8 FlowControl; + 0, + // UINT8 TerminalType; + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + // UINT8 Reserved2; + EFI_ACPI_RESERVED_BYTE, + // UINT16 PciDeviceId; + 0xFFFF, + // UINT16 PciVendorId; + 0xFFFF, + // UINT8 PciBusNumber; + 0x00, + // UINT8 PciDeviceNumber; + 0x00, + // UINT8 PciFunctionNumber; + 0x00, + // UINT32 PciFlags; + 0x00000000, + // UINT8 PciSegment; + 0x00, + // UINT32 Reserved3; + EFI_ACPI_RESERVED_DWORD +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Spcr; diff --git a/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Ssdt.asl b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Ssdt.asl new file mode 100644 index 0000000..b6c5b2c --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/Ssdt.asl @@ -0,0 +1,95 @@ +/** @file +* Secondary System Description Table (SSDT) +* +* Copyright (c) 2018, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "SgiAcpiHeader.h" + +DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "ARMLTD", "SGI-ClarkH", + EFI_ACPI_ARM_OEM_REVISION) +{ + Scope (_SB) { + // PCI Root Complex + Device (PCI0) { + Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_CCA, 1) // Cache Coherency Attribute + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x70000000, // Min Base Address + 0x777FFFFF, // Max Base Address + 0x00000000, // Translate + 0x07800000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x500000000, // Min Base Address + 0x7FFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x300000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x00000000, // Min Base Address + 0x007FFFFF, // Max Base Address + 0x77800000, // Translate + 0x00800000, // Length + , + , + , + TypeTranslation + ) + }) // Name (RBUF) + + Return (RBUF) + } // Method (_CRS) + } + } +} diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf index 0371c40..d903ed8 100644 --- a/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf @@ -38,6 +38,7 @@ gArmSgiPlatformIdDescriptorGuid gSgi575AcpiTablesFileGuid gSgiClarkAresAcpiTablesFileGuid + gSgiClarkHeliosAcpiTablesFileGuid [FeaturePcd] gArmSgiTokenSpaceGuid.PcdVirtioSupported diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec index f66fa1f..f6e0ba1 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dec +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec @@ -34,6 +34,7 @@ gArmSgiTokenSpaceGuid = { 0x577d6941, 0xaea1, 0x40b4, { 0x90, 0x93, 0x2a, 0x86, 0x61, 0x72, 0x5a, 0x57 } } gSgi575AcpiTablesFileGuid = { 0xc712719a, 0x0aaf, 0x438c, { 0x9c, 0xdd, 0x35, 0xab, 0x4d, 0x60, 0x20, 0x7d } } gSgiClarkAresAcpiTablesFileGuid = { 0x4b0b91d0, 0x4a05, 0x45c4, { 0x88, 0xa7, 0x88, 0xe1, 0x70, 0xe7, 0x66, 0x94 } } + gSgiClarkHeliosAcpiTablesFileGuid = { 0x2af40815, 0xa84e, 0x4de9, { 0x8c, 0x38, 0x91, 0x40, 0xb3, 0x54, 0x40, 0x73 } } [PcdsFeatureFlag.common] # Set this PCD to TRUE to enable virtio support. diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc b/Platform/ARM/SgiPkg/SgiPlatform.dsc index 0df0f88..99babd9 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc @@ -252,6 +252,7 @@ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf Platform/ARM/SgiPkg/AcpiTables/Sgi575/AcpiTables.inf Platform/ARM/SgiPkg/AcpiTables/SgiClarkA/AcpiTables.inf + Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/AcpiTables.inf MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf # diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/SgiPlatform.fdf index f400083..8ec3374 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.fdf +++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf @@ -107,6 +107,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/Sgi575/AcpiTables.inf INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/SgiClarkA/AcpiTables.inf + INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/SgiClarkH/AcpiTables.inf INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf # Required by PCI -- 2.7.4