From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=92.121.34.13; helo=inva020.nxp.com; envelope-from=meenakshi.aggarwal@nxp.com; receiver=edk2-devel@lists.01.org Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 956B021196220 for ; Wed, 28 Nov 2018 01:16:33 -0800 (PST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 4D7281A02F8; Wed, 28 Nov 2018 10:16:32 +0100 (CET) Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id EB1AB1A0302; Wed, 28 Nov 2018 10:16:31 +0100 (CET) Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 48EF4340; Wed, 28 Nov 2018 14:46:31 +0530 (IST) From: Meenakshi Aggarwal To: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, edk2-devel@lists.01.org Date: Wed, 28 Nov 2018 20:31:51 +0530 Message-Id: <1543417315-5763-38-git-send-email-meenakshi.aggarwal@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1543417315-5763-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1518771035-6733-1-git-send-email-meenakshi.aggarwal@nxp.com> <1543417315-5763-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [PATCH edk2-platforms 37/41] Compilation: Update the fdf, dsc and dec files. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Nov 2018 09:16:34 -0000 LS1043A PCIe compilation and update firmware device, description and declaration files.Defining Embedded Package PCD which should be at least 20 for 64K PCIe IO size required for CPU hob during PEI phase to Add IO space post PEI phase. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav Signed-off-by: Meenakshi Aggarwal --- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 ++++++++++++++++ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 7 +++++++ .../LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++ .../LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++ Platform/NXP/NxpQoriqLs.dsc.inc | 2 ++ Silicon/NXP/LS1043A/LS1043A.dsc.inc | 4 ++++ Silicon/NXP/NxpQoriqLs.dec | 10 ++++++++++ 7 files changed, 47 insertions(+) diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc index b69ffa2..b43c81a 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -42,6 +42,8 @@ BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf [PcdsFixedAtBuild.common] @@ -74,6 +76,13 @@ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000 gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000 + # + # PCI PCDs. + # + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000 + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC + ################################################################################ # # Components Section - list of all EDK II Modules needed by this Platform @@ -94,4 +103,11 @@ Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F + } + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + ## diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf index 6b27aed..d02b3cc 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf @@ -131,6 +131,13 @@ READ_LOCK_STATUS = TRUE INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf # + # PCI + # + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + # # Network modules # INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf index 7feac56..f2c8b66 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -65,3 +65,5 @@ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdRomSize diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c index 64c5612..1ef3292 100644 --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize); VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + // ROM Space + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr); + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr); + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + // IFC region 1 // // A-009241 : Unaligned write transactions to IFC may result in corruption of data diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc index 5529a04..063d0b8 100644 --- a/Platform/NXP/NxpQoriqLs.dsc.inc +++ b/Platform/NXP/NxpQoriqLs.dsc.inc @@ -245,6 +245,8 @@ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20 + # # Optional feature to help prevent EFI memory map fragments # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc index a4eb117..f3220fa 100644 --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc @@ -64,6 +64,9 @@ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000 + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3 + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000 + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000 # # Big Endian IPs @@ -71,5 +74,6 @@ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE ## diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec index da148b7..aae0a34 100644 --- a/Silicon/NXP/NxpQoriqLs.dec +++ b/Silicon/NXP/NxpQoriqLs.dec @@ -78,6 +78,16 @@ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129 gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x0|UINT64|0x0000012C + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D + + # + # PCI PCDs + # + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0 + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x000001D1 + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x000001D2 + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x000001D3 # # IFC PCDs -- 1.9.1