From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=40.107.5.86; helo=eur03-ve1-obe.outbound.protection.outlook.com; envelope-from=achin.gupta@arm.com; receiver=edk2-devel@lists.01.org Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50086.outbound.protection.outlook.com [40.107.5.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 42C4521962301 for ; Sun, 23 Dec 2018 04:36:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3yQtqTZh4tT17mEr8+3DJhOmbJ5v/9zet8nl3ig/zDE=; b=Ys3QKzE1U0DW/TCsq3AFaaleS1snX1xAHlPjcuZlNTZaduzSk0sKg2T7qZdX4DbMlNEiUZKpyjaZDXObnsipTGXT1D/8g10RTKU/auaaSipJGEjUmA3+7ld9nDdhFU1TS8VAhtXNIXGVPD3YYdr7vpVYSLnvL5HTgf89TgSDmpE= Received: from AM0PR08MB2980.eurprd08.prod.outlook.com (52.134.92.153) by AM0PR08MB3316.eurprd08.prod.outlook.com (52.134.94.141) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1446.23; Sun, 23 Dec 2018 12:36:27 +0000 Received: from AM0PR08MB2980.eurprd08.prod.outlook.com ([fe80::699d:8afc:800:46ce]) by AM0PR08MB2980.eurprd08.prod.outlook.com ([fe80::699d:8afc:800:46ce%2]) with mapi id 15.20.1446.026; Sun, 23 Dec 2018 12:36:27 +0000 From: Achin Gupta To: "edk2-devel@lists.01.org" CC: Supreeth Venkatesh , Achin Gupta , "ard.biesheuvel@linaro.org" , "leif.lindholm@linaro.org" , nd Thread-Topic: [edk2-platforms PATCH v3 1/2] VExpressPkg: Add dsc and fdf files for generating Standalone MM Image. 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 X-List-Received-Date: Sun, 23 Dec 2018 12:36:33 -0000 Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable From: Supreeth Venkatesh This patch adds description file and firmware device file to generate secure world Standalone Management Mode (MM) image on AArch64 FVP. The secure world Standalone Management Mode (MM) image generated on AArch64 FVP feeds into the fiptool as BL32 image. These files provide reference for Standalone Management Mode (MM) image generation on AArch64 FVP. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Supreeth Venkatesh --- Platform/ARM/VExpressPkg/ArmVExpress-StandaloneMm-FVP-AArch64.dsc | 102 ++= +++++++++ Platform/ARM/VExpressPkg/ArmVExpress-StandaloneMm-FVP-AArch64.fdf | 184 ++= ++++++++++++++++++ 2 files changed, 286 insertions(+) diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-StandaloneMm-FVP-AArch64.= dsc b/Platform/ARM/VExpressPkg/ArmVExpress-StandaloneMm-FVP-AArch64.dsc new file mode 100644 index 0000000..56d94d3 --- /dev/null +++ b/Platform/ARM/VExpressPkg/ArmVExpress-StandaloneMm-FVP-AArch64.dsc @@ -0,0 +1,102 @@ +# +# Copyright (c) 2011-2018, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D ArmVExpress-StandaloneMm-FVP-AArch64 + PLATFORM_GUID =3D 49269c13-165c-46f0-85a4-16f290610588 + PLATFORM_VERSION =3D 1.0 + DSC_SPECIFICATION =3D 0x00010011 +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY =3D $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY =3D Build/ArmVExpress-StandaloneMm-FVP-AA= rch64 +!endif + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/ARM/VExpressPkg/ArmVExpress-= StandaloneMm-FVP-AArch64.fdf + +[LibraryClasses.common] + # + # Basic + # + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + FvLib|StandaloneMmPkg/Library/FvLib/FvLib.inf + HobLib|StandaloneMmPkg/Library/StandaloneMmCoreHobLib/StandaloneMmCoreHo= bLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + MemLib|StandaloneMmPkg/Library/StandaloneMmMemLib/StandaloneMmMemLib.inf + MemoryAllocationLib|StandaloneMmPkg/Library/StandaloneMmCoreMemoryAlloca= tionLib/StandaloneMmCoreMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + + # + # Entry point + # + StandaloneMmDriverEntryPoint|StandaloneMmPkg/Library/StandaloneMmDriverE= ntryPoint/StandaloneMmDriverEntryPoint.inf + +[LibraryClasses.AARCH64] + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuStandaloneMmCoreLib.inf + ArmSvcLib|ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMainte= nanceLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCof= fExtraActionLib.inf + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf + # ARM PL011 UART Driver + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortL= ib.inf + + StandaloneMmCoreEntryPoint|StandaloneMmPkg/Library/StandaloneMmCoreEntry= Point/StandaloneMmCoreEntryPoint.inf + +[BuildOptions] +GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 -march=3Darmv8-a+no= fp + + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFeatureFlag] + gStandaloneMmPkgTokenSpaceGuid.PcdStandaloneMmEnable|TRUE + +[PcdsFixedAtBuild] + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800000CF + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xff + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x0f + + ## PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c0b0000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + # + # MM Core + # + StandaloneMmPkg/Core/StandaloneMmCore.inf + +[Components.AARCH64] + StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-StandaloneMm-FVP-AArch64.= fdf b/Platform/ARM/VExpressPkg/ArmVExpress-StandaloneMm-FVP-AArch64.fdf new file mode 100644 index 0000000..11de0e7 --- /dev/null +++ b/Platform/ARM/VExpressPkg/ArmVExpress-StandaloneMm-FVP-AArch64.fdf @@ -0,0 +1,184 @@ +# +# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.] +!ifdef ARM_FVP_RUN_NORFLASH +BaseAddress =3D 0x08000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The ba= se address of the Firmware in Flash0. +!else +BaseAddress =3D 0xff200000|gArmTokenSpaceGuid.PcdFdBaseAddress # UEFI i= n DRAM + 128MB. +!endif +Size =3D 0x00e00000|gArmTokenSpaceGuid.PcdFdSize # The si= ze in bytes of the device (64MiB). +ErasePolarity =3D 1 + +# This one is tricky, it must be: BlockSize * NumBlocks =3D Size +BlockSize =3D 0x00001000 +NumBlocks =3D 0x0e00 + +0x00000000|0x00280000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +INF StandaloneMmPkg/Core/StandaloneMmCore.inf +INF StandaloneMmPkg/Drivers/StandaloneMmCpu/AArch64/StandaloneMmCpu.inf + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + + +##########################################################################= ## +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section = # +##########################################################################= ## +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER =3D $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING=3D"$(MODULE_NAME)" Optional +# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) +# } +# } +# } +# +##########################################################################= ## + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.MM_CORE_STANDALONE] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + PE32 PE32 Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.MM_STANDALONE] + FILE MM_STANDALONE =3D $(NAMED_GUID) { + SMM_DEPEX SMM_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ASL |.aml + } --=20 1.9.1