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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id 4-v6sm2214904ljw.84.2019.01.21.02.52.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 02:52:33 -0800 (PST) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Date: Mon, 21 Jan 2019 11:52:09 +0100 Message-Id: <1548067931-18618-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548067931-18618-1-git-send-email-mw@semihalf.com> References: <1548067931-18618-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH 1/3] Marvell: Armada7k8k: Shift PEI stack base X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 X-List-Received-Date: Mon, 21 Jan 2019 10:52:36 -0000 Recent changes in the ARM-TF configure its runtime serices region as protected, hence the hitherto PEI stack base address (0x41F0000) violated it. In order to fix this, extend the region which is non-accessible by the OS to cover both the ARM-TF (0x4000000 - 0x4200000) and OPTEE (0x4400000 - 0x5400000) within a single area and set the PEI stack base address between both images. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc index eafcd6e..c8c597f 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -376,12 +376,12 @@ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|36 - gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x41F0000 + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x43F0000 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 # Secure region reservation gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 - gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0200000 + gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x1400000 # TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 -- 2.7.4