From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::242; helo=mail-lj1-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4FFF021962301 for ; Mon, 21 Jan 2019 17:32:52 -0800 (PST) Received: by mail-lj1-x242.google.com with SMTP id n18-v6so19121437lji.7 for ; Mon, 21 Jan 2019 17:32:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OdWQEfvTmZYy7/9ZRMzMExSjpSH/QQYh8DlsjqgKc2A=; b=llkjUQ6c7RL7jB28JTs+uyJRooGmWMXNL7SYJ+Upx3GNmResFGjgjSGezb5AeLXAWC D8SUJO3wg2PfVL32rYe6/DmDDpCkqevz1/3KDRITBKUNbXwjSRoVQzqL2A2UzvxTDNoO rESXTz9qLMj2XnXo/O3XVyDc6ZONdH9ZNy/dDWB0kEadfIFD/KH6bbh5WwQgvx/SdSvV fzAN95abBn77gWBSuHSp0E3WaSy26KCwLMO6xhLAlFAHdv+TuiN2ZG4oF5VKpJTECQyX pSC6gArFjRBpEQPd3lXayYpfTEB0BzL186MegreBxte6uIGhOpO518K2/jJ3FVhsLRfS IiQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OdWQEfvTmZYy7/9ZRMzMExSjpSH/QQYh8DlsjqgKc2A=; b=stQqoR/qL0yCOX/Tk4aNEo0kh8zwfQ5v/qrLxYHZFIR1kq3xlJhw7YB3SCYoGQAFNk +4iAZmwTPm1ALOqwQ5LZ5gV8biuTIh2o1vbvPcRgdu4YLNJepcd3z+7jNyj3gjeXeSwI 0v0Te2sTosVIRySMP3jjTJMUG90yDL9kDvdcoRH+3Vcpe2BH6NST326oaKzfOE/iM98j tl1QH9KcYOQXta3zfvnKZwSBNC/83ldKr8ng6+uB6dKbN4U/EzEM4kXdt1rTjXzV8bnM tLejV9sTtAxykZRghztFCfuqFGI/wvrl/xdtF+qtufQ2V5WNPHu1YybrYxJGVbWY3zwH zxxg== X-Gm-Message-State: AJcUukexAZvLcxu4HdGxy28Gs5r6m4wrzniEt8QqQc3ZieThuxhyvfeb Z51ScOjvngjZ7xPS5uuywqbjgL4EJu0= X-Google-Smtp-Source: ALg8bN72IsL0ml72yjKZqH9xDX27sCFTAh2sO3UgbVDHstTN+du/TrOoAd2Bj5ERcbl5xi33euGlyg== X-Received: by 2002:a2e:1f01:: with SMTP id f1-v6mr1538536ljf.129.1548120770418; Mon, 21 Jan 2019 17:32:50 -0800 (PST) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id b21sm2524463lfi.7.2019.01.21.17.32.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jan 2019 17:32:49 -0800 (PST) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Date: Tue, 22 Jan 2019 02:32:22 +0100 Message-Id: <1548120742-11928-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548120742-11928-1-git-send-email-mw@semihalf.com> References: <1548120742-11928-1-git-send-email-mw@semihalf.com> Subject: [platforms: PATCH v2 4/4] Marvell/Armada7k8k: Read DRAM settings from ARM-TF X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Jan 2019 01:32:52 -0000 From: Grzegorz Jaszczyk The memory controller registers are marked as secure in the latest ARM-TF for Armada SoCs. It is available however get the DRAM information via SiP services in the EL3, so use it instead of accessing the registers directly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 3 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h | 25 -------- Silicon/Marvell/Include/Library/MvSmc.h | 1 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 60 ++++++-------------- 4 files changed, 22 insertions(+), 67 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index e888566..0c7f320 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -41,12 +41,15 @@ [Packages] ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec Silicon/Marvell/Marvell.dec [LibraryClasses] + ArmadaSoCDescLib ArmLib + ArmSmcLib DebugLib MemoryAllocationLib MppLib diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h index cc30e4a..8101cf3 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.h @@ -46,28 +46,3 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. (MmioRead32 (CCU_MC_RCR_REG) & REMAP_SIZE_MASK) + SIZE_1MB #define DRAM_REMAP_TARGET \ (MmioRead32 (CCU_MC_RTBR_REG) << TARGET_BASE_OFFS) - -#define DRAM_CH0_MMAP_LOW_REG(cs) (0xf0020200 + (cs) * 0x8) -#define DRAM_CS_VALID_ENABLED_MASK 0x1 -#define DRAM_AREA_LENGTH_OFFS 16 -#define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS) -#define DRAM_START_ADDRESS_L_OFFS 23 -#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFFS) -#define DRAM_CH0_MMAP_HIGH_REG(cs) (0xf0020204 + (cs) * 0x8) -#define DRAM_START_ADDR_HTOL_OFFS 32 - -#define DRAM_MAX_CS_NUM 8 - -#define DRAM_CS_ENABLED(Cs) \ - (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_CS_VALID_ENABLED_MASK) -#define GET_DRAM_REGION_BASE(Cs) \ - ((UINT64)MmioRead32 (DRAM_CH0_MMAP_HIGH_REG ((Cs))) << \ - DRAM_START_ADDR_HTOL_OFFS) | \ - (MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)) & DRAM_START_ADDRESS_L_MASK); -#define GET_DRAM_REGION_SIZE_CODE(Cs) \ - (MmioRead32 (DRAM_CH0_MMAP_LOW_REG ((Cs))) & \ - DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS -#define DRAM_REGION_SIZE_EVEN(C) (((C) >= 7) && ((C) <= 26)) -#define GET_DRAM_REGION_SIZE_EVEN(C) ((UINT64)1 << ((C) + 16)) -#define DRAM_REGION_SIZE_ODD(C) ((C) <= 4) -#define GET_DRAM_REGION_SIZE_ODD(C) ((UINT64)0x18000000 << (C)) diff --git a/Silicon/Marvell/Include/Library/MvSmc.h b/Silicon/Marvell/Include/Library/MvSmc.h index 2d1542a..0c90f11 100644 --- a/Silicon/Marvell/Include/Library/MvSmc.h +++ b/Silicon/Marvell/Include/Library/MvSmc.h @@ -19,5 +19,6 @@ #define MV_SMC_ID_COMPHY_POWER_ON 0x82000001 #define MV_SMC_ID_COMPHY_POWER_OFF 0x82000002 #define MV_SMC_ID_COMPHY_PLL_LOCK 0x82000003 +#define MV_SMC_ID_DRAM_SIZE 0x82000010 #endif //__MV_SMC_H__ diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c index 2a4f5ad..8517deb 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c @@ -32,12 +32,18 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *******************************************************************************/ -#include +#include + +#include + +#include #include +#include #include #include #include #include +#include #include "Armada7k8kLibMem.h" @@ -57,49 +63,19 @@ GetDramSize ( IN OUT UINT64 *MemSize ) { - UINT64 BaseAddr; - UINT8 RegionCode; - UINT8 Cs; - - *MemSize = 0; - - for (Cs = 0; Cs < DRAM_MAX_CS_NUM; Cs++) { - - /* Exit loop on first disabled DRAM CS */ - if (!DRAM_CS_ENABLED (Cs)) { - break; - } - - /* - * Sanity check for base address of next DRAM block. - * Only continuous space will be used. - */ - BaseAddr = GET_DRAM_REGION_BASE (Cs); - if (BaseAddr != *MemSize) { - DEBUG ((DEBUG_ERROR, - "%a: DRAM blocks are not contiguous, limit size to 0x%llx\n", - __FUNCTION__, - *MemSize)); - return EFI_SUCCESS; - } - - /* Decode area length for current CS from register value */ - RegionCode = GET_DRAM_REGION_SIZE_CODE (Cs); - - if (DRAM_REGION_SIZE_EVEN (RegionCode)) { - *MemSize += GET_DRAM_REGION_SIZE_EVEN (RegionCode); - } else if (DRAM_REGION_SIZE_ODD (RegionCode)) { - *MemSize += GET_DRAM_REGION_SIZE_ODD (RegionCode); - } else { - DEBUG ((DEBUG_ERROR, - "%a: Invalid memory region code (0x%x) for CS#%d\n", - __FUNCTION__, - RegionCode, - Cs)); - return EFI_INVALID_PARAMETER; - } + ARM_SMC_ARGS SmcRegs = {0}; + EFI_STATUS Status; + + SmcRegs.Arg0 = MV_SMC_ID_DRAM_SIZE; + Status = ArmadaSoCAp8xxBaseGet (&SmcRegs.Arg1, 0); + if (EFI_ERROR (Status)) { + return Status; } + ArmCallSmc (&SmcRegs); + + *MemSize = SmcRegs.Arg0; + return EFI_SUCCESS; } -- 2.7.4