[platforms: PATCH v3 4/5] Marvell/Library: ArmadaSoCDescLib: Add North Bridge description

[Marcin Wojtas <mw@semihalf.com>]

From: Grzegorz Jaszczyk <jaz@semihalf.com>

For upcomming patch there is need to get AP806 base, provide required
getter function for it.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h |  6 ++++
 Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h                             | 28 ++++++++++++++++
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 34 ++++++++++++++++++++
 3 files changed, 68 insertions(+)

diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
index bfc8639..c2d7933 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
@@ -22,9 +22,15 @@
 // Common macros
 //
 #define MV_SOC_CP_BASE(Cp)               (0xF2000000 + ((Cp) * 0x2000000))
+#define MV_SOC_AP806_BASE                0xF0000000
 #define MV_SOC_AP806_COUNT               1
 
 //
+// Armada7k8k default North Bridge index
+//
+#define ARMADA7K8K_AP806_INDEX           0
+
+//
 // Platform description of AHCI controllers
 //
 #define MV_SOC_AHCI_BASE(Cp)             (MV_SOC_CP_BASE (Cp) + 0x540000)
diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
index 26b075a..fc17c3a 100644
--- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
+++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
@@ -20,6 +20,34 @@
 #include <Protocol/EmbeddedGpio.h>
 
 //
+// North Bridge description
+//
+
+/**
+
+Routine Description:
+
+  Get base address of the SoC North Bridge.
+
+Arguments:
+
+  ApBase  - Base address of the North Bridge.
+  ApIndex - Index of the North Bridge.
+
+Returns:
+
+  EFI_SUCCESS           - Proper base address is returned.
+  EFI_INVALID_PARAMETER - The index is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaSoCAp8xxBaseGet (
+  IN OUT EFI_PHYSICAL_ADDRESS  *ApBase,
+  IN UINTN                      ApIndex
+  );
+
+//
 // ComPhy SoC description
 //
 typedef struct {
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
index 5b72c20..584f445 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
@@ -28,6 +28,40 @@
 
 #include "Armada7k8kSoCDescLib.h"
 
+/**
+
+Routine Description:
+
+  Get base address of the SoC North Bridge.
+
+Arguments:
+
+  ApBase  - Base address of the North Bridge.
+  ApIndex - Index of the North Bridge.
+
+Returns:
+
+  EFI_SUCCESS           - Proper base address is returned.
+  EFI_INVALID_PARAMETER - The index is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaSoCAp8xxBaseGet (
+  IN OUT EFI_PHYSICAL_ADDRESS  *ApBase,
+  IN UINTN                      ApIndex
+  )
+{
+  if (ApIndex != ARMADA7K8K_AP806_INDEX) {
+    DEBUG ((DEBUG_ERROR, "%a: Only one AP806 in A7K/A8K SoC\n", __FUNCTION__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  *ApBase = MV_SOC_AP806_BASE;
+
+  return EFI_SUCCESS;
+}
+
 EFI_STATUS
 EFIAPI
 ArmadaSoCDescComPhyGet (
-- 
2.7.4