From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=EXtrCkO2; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.193, mailfrom: mw@semihalf.com) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by groups.io with SMTP; Fri, 12 Apr 2019 03:20:02 -0700 Received: by mail-lj1-f193.google.com with SMTP id l7so8351784ljg.6 for ; Fri, 12 Apr 2019 03:20:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D6aN0XmdYygF2Bjse/COrP+mw5oqYaJfzTCS391+rZQ=; b=EXtrCkO2NeFzx0RPZpRfJL3YkfFxFofm6ptmW4DU1Od4KRntaQwPD+fbbAq/SSEL/Y crp/Z9tMLV5hnx3U0VRGXAvo8KkWppILplLH0pcGTPXCPBmzqmRzrvEhBSsVhTvnEHL1 wfkrVnWYaZiINuI6+1HnPLWwgPGPdDfjkjFAEH9Hjunas2iVYKvKU5aXB+8PmkjUXCb4 nVZT+TDX1nRO3YxuYdOjwEMHRnTgMZUngR9GbZysANjYsnClTph//bjPgxXt0Jpdx+DG 2PySUxTqoLE3BdB1cYLGz2ZYBqXBsc3qNQEnZ3OHXErW6cFDKyzyx1dd6Y4dJTVCL8nT CSJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D6aN0XmdYygF2Bjse/COrP+mw5oqYaJfzTCS391+rZQ=; b=hf0q/nrTJONn5+770j6VHwbFd8j0FQNXIrLZf5Hi+Q5hmhspXWzvoRzwbfhnwtrZkh 0V32cFjLLdZMd4AyJemttQto1FeEIRySCyEaCUQPyMx9yCs/8cFQxDOQUqsRyF3PhknS 56gA2S9p6N4Yot7GgIB95EC7rzPbUb4u4P4xsfzv2HHmtJIOA5snwfzbagTezUPqFHfd RdshdIv+54Vjy0C0+hTA4YlSh1OGkZAClKx7niKIWgeEzJvkcF4Hrz/wVlV8/Du7PRCz W1M4o6jNUT0tyAqEDeehL/vWvv8DAJLAwLhFIb9JMOd22XzKI6HiCEtMzVmb79pXj3zw XJow== X-Gm-Message-State: APjAAAVK1TmlEigsEBZjlpSxtVwqTCVEE5ZPkDyE/l4Ulqx5BCvgzRZI YHehRKrLLSNOidZqtmyCBkF8TsjRECtL/n3O X-Google-Smtp-Source: APXvYqxdVrXKQtYwJPkFQcIntUDwHI9uYFntiGLDzlKeHqmNQ+8NorboMIA+0LTg841XRjT3s/3Stg== X-Received: by 2002:a2e:960b:: with SMTP id v11mr17137934ljh.135.1555064399574; Fri, 12 Apr 2019 03:19:59 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id o3sm8025240lfd.53.2019.04.12.03.19.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 12 Apr 2019 03:19:58 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, jeremy.linton@arm.com, Jici.Gao@arm.com, Mark Kettenis Subject: [edk2-platforms: PATCH 1/6] Marvell/Armada7k8k: RealTimeClockLib: Update bus parameters Date: Fri, 12 Apr 2019 12:19:31 +0200 Message-Id: <1555064376-22302-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555064376-22302-1-git-send-email-mw@semihalf.com> References: <1555064376-22302-1-git-send-email-mw@semihalf.com> From: Mark Kettenis Adjust bus timing parameters to make reading and updating the RTC reliable. This patch aligns the bus configuration to the one used by Linux. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.h | 7 ++++++- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c | 5 +++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.h b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.h index 922f959..ee0c303 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.h @@ -41,10 +41,15 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define RTC_IRQ_2_CONFIG_REG 0x8 #define RTC_IRQ_ALARM_EN 0x1 #define RTC_ALARM_2_REG 0x14 +#define RTC_BRIDGE_TIMING_CTRL0_REG_OFFS 0x80 #define RTC_BRIDGE_TIMING_CTRL1_REG_OFFS 0x84 #define RTC_IRQ_STATUS_REG 0x90 #define RTC_IRQ_ALARM_MASK 0x1 +#define RTC_WRITE_PERIOD_DELAY_MASK 0xFFFF +#define RTC_WRITE_PERIOD_DELAY_DEFAULT 0x3FF +#define RTC_WRITE_SETUP_DELAY_MASK (0xFFFF << 16) +#define RTC_WRITE_SETUP_DELAY_DEFAULT (0x29 << 16) #define RTC_READ_OUTPUT_DELAY_MASK 0xFFFF -#define RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F +#define RTC_READ_OUTPUT_DELAY_DEFAULT 0x3F #endif /* __RTCLIB_H__ */ diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c index 087bd9a..7de5ed7 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c @@ -250,6 +250,11 @@ LibRtcInitialize ( /* Update RTC-MBUS bridge timing parameters */ MmioAndThenOr32 ( + mArmadaRtcBase + RTC_BRIDGE_TIMING_CTRL0_REG_OFFS, + ~(RTC_WRITE_SETUP_DELAY_MASK | RTC_WRITE_PERIOD_DELAY_MASK), + (RTC_WRITE_SETUP_DELAY_DEFAULT | RTC_WRITE_PERIOD_DELAY_DEFAULT) + ); + MmioAndThenOr32 ( mArmadaRtcBase + RTC_BRIDGE_TIMING_CTRL1_REG_OFFS, ~RTC_READ_OUTPUT_DELAY_MASK, RTC_READ_OUTPUT_DELAY_DEFAULT -- 2.7.4