From: "Marcin Wojtas" <mw@semihalf.com>
To: devel@edk2.groups.io
Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org,
nadavh@marvell.com, mw@semihalf.com, jsd@semihalf.com,
jaz@semihalf.com, kostap@marvell.com, jeremy.linton@arm.com,
Jici.Gao@arm.com
Subject: [edk2-platforms: PATCH v2 2/6] Marvell/Armada7k8k: AcpiTables: Enable edge trigger of PMU interrupt
Date: Tue, 16 Apr 2019 11:22:22 +0200 [thread overview]
Message-ID: <1555406546-5261-3-git-send-email-mw@semihalf.com> (raw)
In-Reply-To: <1555406546-5261-1-git-send-email-mw@semihalf.com>
Extend MADT GICC table flags with PERFORMANCE_INTERRUPT_MODEL,
which is responsible for configuring interrupt type in the OS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc b/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
index 3dae5d3..7ab927d 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc
@@ -35,6 +35,8 @@
#define PMU_INTERRUPT_CPU2 132
#define PMU_INTERRUPT_CPU3 133
+#define PMU_INTERRUPT_FLAG EFI_ACPI_6_0_GIC_ENABLED | EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL
+
#pragma pack(push, 1)
typedef struct {
EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
@@ -57,7 +59,7 @@ ACPI_6_0_MADT_STRUCTURE Madt = {
EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, // GicId
0x000, // AcpiCpuUid
0x000, // Mpidr
- EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_FLAG, // Flags
PMU_INTERRUPT_CPU0, // PmuIrq
GICC_BASE, // GicBase
GICV_BASE, // GicVBase
@@ -69,7 +71,7 @@ ACPI_6_0_MADT_STRUCTURE Madt = {
EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, // GicId
0x001, // AcpiCpuUid
0x001, // Mpidr
- EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_FLAG, // Flags
PMU_INTERRUPT_CPU1, // PmuIrq
GICC_BASE, // GicBase
GICV_BASE, // GicVBase
@@ -81,7 +83,7 @@ ACPI_6_0_MADT_STRUCTURE Madt = {
EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, // GicId
0x100, // AcpiCpuUid
0x100, // Mpidr
- EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_FLAG, // Flags
PMU_INTERRUPT_CPU2, // PmuIrq
GICC_BASE, // GicBase
GICV_BASE, // GicVBase
@@ -93,7 +95,7 @@ ACPI_6_0_MADT_STRUCTURE Madt = {
EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, // GicId
0x101, // AcpiCpuUid
0x101, // Mpidr
- EFI_ACPI_6_0_GIC_ENABLED, // Flags
+ PMU_INTERRUPT_FLAG, // Flags
PMU_INTERRUPT_CPU3, // PmuIrq
GICC_BASE, // GicBase
GICV_BASE, // GicVBase
--
2.7.4
next prev parent reply other threads:[~2019-04-16 9:23 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-16 9:22 [edk2-platforms: PATCH v2 0/6] Armada7k8k misc improvements Marcin Wojtas
2019-04-16 9:22 ` [edk2-platforms: PATCH v2 1/6] Marvell/Armada7k8k: RealTimeClockLib: Update bus parameters Marcin Wojtas
2019-04-16 9:22 ` Marcin Wojtas [this message]
2019-04-16 9:22 ` [edk2-platforms: PATCH v2 3/6] Marvell/Armada7k8k: Implement PMU interrupt handling Marcin Wojtas
2019-04-16 18:51 ` Ard Biesheuvel
2019-04-16 9:22 ` [edk2-platforms: PATCH v2 4/6] Marvell/Armada7k8k: Switch to software-based watchdog Marcin Wojtas
2019-04-16 9:22 ` [edk2-platforms: PATCH v2 5/6] Marvell/Armada7k8k: ArmadaSoCDescLib: Add more I2C controllers Marcin Wojtas
2019-04-16 9:22 ` [edk2-platforms: PATCH v2 6/6] Marvell/Armada80x0Db: Configure the CP1, comphy-2 to work with SFI 10G Marcin Wojtas
2019-04-16 18:51 ` [edk2-platforms: PATCH v2 0/6] Armada7k8k misc improvements Ard Biesheuvel
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