From: "Marcin Wojtas" <mw@semihalf.com>
To: devel@edk2.groups.io
Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org,
mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com,
kostap@marvell.com, jeremy.linton@arm.com, Jici.Gao@arm.com
Subject: [edk2-platforms: PATCH v3 1/1] Marvell/Library: ComPhyLib: Update mode parameter for PCIE power on
Date: Wed, 17 Apr 2019 23:20:06 +0200 [thread overview]
Message-ID: <1555536006-2356-1-git-send-email-mw@semihalf.com> (raw)
Most recent ARM-TF ComPhy PCIE initialization routines check
additional mode parameter in order to determine, where the SMC
is called from (OS / firmware). Adjust to that.
This patch fixes the Linux boot with DT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
index 9fd6602..e918f01 100644
--- a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
+++ b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h
@@ -43,11 +43,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Helper macros for passing ComPhy parameters to the EL3 */
+#define COMPHY_CALLED_FROM_FW (1 << 21)
#define COMPHY_FW_MODE_FORMAT(mode) (mode << 12)
#define COMPHY_FW_FORMAT(mode, idx, speeds) \
((mode << 12) | (idx << 8) | (speeds << 2))
#define COMPHY_FW_PCIE_FORMAT(pcie_width, mode, speeds) \
- ((pcie_width << 18) | COMPHY_FW_FORMAT (mode, 0, speeds))
+ (COMPHY_CALLED_FROM_FW | ((pcie_width) << 18) | \
+ COMPHY_FW_FORMAT(mode, 0, speeds))
/* Comphy speed */
#define COMPHY_SPEED_1_25G 0
--
2.7.4
next reply other threads:[~2019-04-17 21:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-17 21:20 Marcin Wojtas [this message]
2019-04-20 17:39 ` [edk2-platforms: PATCH v3 1/1] Marvell/Library: ComPhyLib: Update mode parameter for PCIE power on Ard Biesheuvel
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