From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=jRQ06FA+; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.194, mailfrom: mw@semihalf.com) Received: from mail-lj1-f194.google.com (mail-lj1-f194.google.com [209.85.208.194]) by groups.io with SMTP; Tue, 23 Apr 2019 23:52:12 -0700 Received: by mail-lj1-f194.google.com with SMTP id q66so15776254ljq.7 for ; Tue, 23 Apr 2019 23:52:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=RpXv6u2pySlGgNwoeov0o+BN7Y/X8kcdK0c2Et9X5wQ=; b=jRQ06FA+ZHZSHptSr3dwfA1O4YICxvC6hxf34HPPF8iEEicZBsn8CGgS9sv0vcDxlW YM0d4r5TifZYuvqaawiCadK+Rp3DSdONLV73NJCT3wf55js3i15YHTWrgJrnzQV3LFb5 YRTXD+PcFCJMZC/17JGRNb4AAjp+7DTgcImH/l80u2HzuUcoQdY2b0VLYNdgXJluxmqh PaQsvH6MEqQ32JuAvsdlA3UkvR0X9Hm7b4RDO2KfN9FzmtjsqSWfdx3VYtSwJHyIeIGA Xngo+7/IroCYRamfPMGlPx9tearecpuiZ6pf+X8w7E/mRnX6lidHotxOntHQqdN8pyUp JwOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=RpXv6u2pySlGgNwoeov0o+BN7Y/X8kcdK0c2Et9X5wQ=; b=cun7jk/+RIQE1Rd8YfTJSR3zr328m02o8I3grAM05l/2xjFXMkH/aBeltEC/8CnjIx DxEt47xX2Tm6SnyM0AEbjjWvEngppf//Lxf+2y7cLn7sdp++/ODOy+krU9g+DcW2Fp2c WZMxlVtvoI2V4pBiWJ15Rl9NjiQzIf78DVw8/jaEwTB0JytzP6U4YQ6mz8WAIDmHqY0E ACp5g26TGgqGSvSjAhLCVYm9raEJOCz6asvgos0VpHg4+kZ+1MbyxmAof9gf91rtl1Vq 0/mc17D3R2+KmNrZdUMQa78pR4ptsHA2/u4HvUOQRsj7vWB4DLuhx1j4n2cm+wZ4TTVF ksaQ== X-Gm-Message-State: APjAAAXsN1l0uNca4Nj8n5eB5GeKWR2aZTkvlaVmsL17i4oRWQgTfmSY mS1BMwmVlRWx7BpAK8nwn9uPSttOWKh1Ig== X-Google-Smtp-Source: APXvYqy1XJsgagnJ6H4lqXMFmepP5EYPzfYNeNWL26g198PsniGQ4rD5JIU+dsvTgRf7P5A1xALKgQ== X-Received: by 2002:a2e:8787:: with SMTP id n7mr16320224lji.31.1556088729676; Tue, 23 Apr 2019 23:52:09 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 125sm505129lfl.60.2019.04.23.23.52.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Apr 2019 23:52:08 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com Subject: [edk2-platforms: PATCH v2 0/3] Armada7k8k FVB improvements Date: Wed, 24 Apr 2019 08:51:48 +0200 Message-Id: <1556088711-14442-1-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 Hi, The second version of the patchset, as a result of discussions, abandons gate-clock handling of the SPI flash, as when booting from UEFI the proper flow is to rely on description provided by firmware and the clock handling itself should be left for the OS entirely. Instead a new patch is introduced, which removes unused components from the PEI FV. The patches are available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/fvb-upstream-r20190424 I'm looking forward to your comments or remarks. Best regards, Marcin Changelog: v1->v2 * Replace clock-enabling patch with PEI phase FV cleanup Hanna Hawa (1): Marvell/Drivers: MvFvbDxe: Change Pcd parameters to be 64 bit Kornel Duleba (1): Marvell/Drivers: Add non-mmio mode to MvFvbDxe Marcin Wojtas (1): Marvell/Armada7k8k: Cleanup PEI phase FV Silicon/Marvell/Marvell.dec | 10 +- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 13 +- Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 3 - Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.inf | 17 ++- Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.h | 1 + Silicon/Marvell/Drivers/Spi/MvFvbDxe/MvFvbDxe.c | 149 +++++++++++++++----- 6 files changed, 143 insertions(+), 50 deletions(-) -- 2.7.4