From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: tien.hock.loh@intel.com) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by groups.io with SMTP; Thu, 09 May 2019 02:20:12 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 May 2019 02:20:07 -0700 X-ExtLoop1: 1 Received: from pg-nx11.altera.com ([10.104.4.26]) by orsmga002.jf.intel.com with ESMTP; 09 May 2019 02:20:04 -0700 From: "Loh, Tien Hock" To: devel@edk2.groups.io, thloh85@gmail.com Cc: "Tien Hock, Loh" , Jian J Wang , Hao Wu , "Zhu, YongHong" Subject: [PATCH v2 1/1] MdeModulePkg: BaseSerialPortLib16550: Add missing Pcd to UNI Date: Thu, 9 May 2019 17:19:54 +0800 Message-Id: <1557393594-129092-1-git-send-email-tien.hock.loh@intel.com> X-Mailer: git-send-email 2.2.2 From: "Tien Hock, Loh" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1771 Some busses doesn't allow 8 bit MMIO read/write, this adds support for 32 bits read/write. This patch adds the UNI information on the new Pcd introduced - PcdSerialRegisterAccessWidth Signed-off-by: "Tien Hock, Loh" Cc: Jian J Wang Cc: Hao Wu Cc: "Zhu, YongHong" -- v2 - Added Bugzilla to commit - Fixed typo --- MdeModulePkg/MdeModulePkg.uni | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni index cf2aefa7ad..654dfeadb0 100644 --- a/MdeModulePkg/MdeModulePkg.uni +++ b/MdeModulePkg/MdeModulePkg.uni @@ -160,6 +160,12 @@ "TRUE - 16550 serial port registers are in MMIO space.
\n" "FALSE - 16550 serial port registers are in I/O space.
" +#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialRegisterAccessWidth_PROMPT #language en-US "Serial port registers access width" + +#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialRegisterAccessWidth_HELP #language en-US "Sets the 16550 serial port registers access width in MMIO space. Default is 8 bits access.

\n" + "8 - 16550 serial port MMIO register access are in 8 bits mode.
\n" + "32 - 16550 serial port MMIO registers acess are in 32 bits mode..
" + #string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialUseHardwareFlowControl_PROMPT #language en-US "Enable serial port hardware flow control" #string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdSerialUseHardwareFlowControl_HELP #language en-US "Indicates if the 16550 serial port hardware flow control will be enabled. Default is FALSE.

\n" -- 2.19.0