From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=rxCFGtSf; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.68, mailfrom: mw@semihalf.com) Received: from mail-lf1-f68.google.com (mail-lf1-f68.google.com [209.85.167.68]) by groups.io with SMTP; Thu, 09 May 2019 02:54:01 -0700 Received: by mail-lf1-f68.google.com with SMTP id u27so1081284lfg.10 for ; Thu, 09 May 2019 02:54:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UF22PdOTxCKQ0FPv0UVw3vTIbNtffN8rdOY2WuYpgb8=; b=rxCFGtSfWSFiblVk/6T6tqdQM9kwrw3dcP+95nK8YYY96i9+67SQK63QL21jl69AfS SAVH025tjKd/Iapn0mPpQWg9f+YxhJEe2NF209FFBhpVyMV25h/8ywxAKkQGmcUILSOM hf2WfilQDbExaRfJ8cnMnR8wX6bSOplSBDaEz7EIlPSuWhTeVeViRywzN1Ulv+R5mHM0 jVAjdq13YC08gFpIArk5sHrmoTyYdh6WoeJp2+kM4tw6+VtPDiTYEx7ei1MT6k8+hm95 bo+CRSgps2ke1Td7xDOxod9FTqgFPPNqMJSKjbrY4Ie51OnAXF29WveVNkKDTcjwhCX3 LTFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UF22PdOTxCKQ0FPv0UVw3vTIbNtffN8rdOY2WuYpgb8=; b=oH2PKfNHWtV7NpXXahpKuGIINgOlZQ2em+mWAHYMSijGsnA+NVgdGgddaokmQJhPws LSbuNbSjbbBvSSHsBgZPt1t3Wt2E3eDR1rlTRxEzVlomQLqYlO5q3prsQift9KkextUl 9x0vhhksonMn1OLf2NAjm9k8bM0R95OlKhRmnTOn/5UYNupYJDDUrzeExfUUeWUgLudp qUUQjkX4K3h/c/Dz+JYlXZJ/leybgp+ZQlwEP7RXjc4LmiEDcx8FesNv63eanufJIn7Y H5QxMzlLaFcqXUs8PNrVLf5pOrdT8993eye5mO4hcLJ5NJA9S04ml8fI1tRvP9HlmRmv loQQ== X-Gm-Message-State: APjAAAUzTdm+So1EICCDOrVoeuQ7/6I1WaMHchfkrd++2G5pHWm3C79D /Kc9Zkkc1VgVC2l0ye/4v8sA3IjGkO0= X-Google-Smtp-Source: APXvYqz3D2sBxIss/tzCKbaaem4TEZbrWfNO75OtUITsGHzBZUC2//MF+4E02LduH8wtGlRS4ntyTg== X-Received: by 2002:a19:2d1a:: with SMTP id k26mr1976736lfj.104.1557395639312; Thu, 09 May 2019 02:53:59 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id l25sm276668lfk.57.2019.05.09.02.53.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 May 2019 02:53:58 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-platforms: PATCH 03/14] Marvell/Library: ArmadaBoardDescLib: Add PCIE information Date: Thu, 9 May 2019 11:53:31 +0200 Message-Id: <1557395622-32425-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557395622-32425-1-git-send-email-mw@semihalf.com> References: <1557395622-32425-1-git-send-email-mw@semihalf.com> Introduce new callback that can provide information about PCIE controller per-board description. A new structure is defined containing base addresses, windows/bus configuration and reset GPIO usage indication. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h index 6ec5ace..530a2ba 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -15,6 +15,7 @@ #define __ARMADA_BOARD_DESC_LIB_H__ #include +#include // // COMPHY controllers per-board description @@ -111,6 +112,51 @@ typedef struct { } MV_BOARD_XHCI_DESC; // +// PCIE controllers description +// +typedef struct { + EFI_PHYSICAL_ADDRESS PcieBaseAddress; + EFI_PHYSICAL_ADDRESS ConfigSpaceAddress; + BOOLEAN HaveResetGpio; + MV_GPIO_PIN PcieResetGpio; + UINT64 PcieBusMin; + UINT64 PcieBusMax; + UINT64 PcieIoTranslation; + UINT64 PcieIoWinBase; + UINT64 PcieIoWinSize; + UINT64 PcieMmio32Translation; + UINT64 PcieMmio32WinBase; + UINT64 PcieMmio32WinSize; + UINT64 PcieMmio64Translation; + UINT64 PcieMmio64WinBase; + UINT64 PcieMmio64WinSize; +} MV_PCIE_CONTROLLER; + +typedef struct { + MV_PCIE_CONTROLLER *PcieControllers; + UINTN PcieControllerCount; +} MV_BOARD_PCIE_DESCRIPTION; + +/** + Return the number and description of PCIE controllers used on the platform. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER **PcieControllers, + IN OUT UINTN *PcieControllerCount + ); + +// // PP2 NIC devices per-board description // typedef struct { -- 2.7.4