From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=l6AEsK8c; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.66, mailfrom: mw@semihalf.com) Received: from mail-lf1-f66.google.com (mail-lf1-f66.google.com [209.85.167.66]) by groups.io with SMTP; Mon, 20 May 2019 08:27:55 -0700 Received: by mail-lf1-f66.google.com with SMTP id n22so10610668lfe.12 for ; Mon, 20 May 2019 08:27:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zcuL8j07/fKBk9K8JD1tUf1xj7cjRgVQWldGbTyvEnA=; b=l6AEsK8cyhyRqMvmkPG04IU6w7G18L0BRaQK4pkIcPo/ymCk/QU248nSCOlNsPVUp/ 4rl6Yhw8gnN6shlDr2/rpHzseHUXCZPsL8eYnR59v9IVwNR/HhKxrbtZCLsomiKNS9ma j93fGiRFN6sN+/UYyfcXQ8Yum+xrF9pAWdLo8ec3665aBqX1NcDPmXuTJ7r+DAEH27Jt uLaBAoeKOD6GugsfrxQDavZKsoLcsHvTF/jzh4vLRqAP34WGd+xlECETpbEhcToqWVk0 ITIGK2Sa3C4W20xqglF/nD6Y0YR52F5FGUnoOHo9zwVHuGnVdEO6S9Oq0kN0StIwhjNv ULng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zcuL8j07/fKBk9K8JD1tUf1xj7cjRgVQWldGbTyvEnA=; b=lLNkSMCDsWexudD6MnFMjwkjKkLO36Zrea40n/LMlHanRemdn5RgnlLL+BRTJJELst klklev4pvYyWYGDVUX6qXs9K4INspu5l54WxDjyJYWGhnroV/ghcCVoMXkncF+/EIPDp +1nDgBpBynZ783b2Rjmf8DSDsVKD1VA7+errt+i8nrgz413SbruTjhzRbxW61iKfy2Qq Ewvp3UOEpy2Ox4MtkHU0chCA9wo9svCIEhRfj7eAyVSX61pLf0yUvwqO8rU2DKs7Suy3 FEWbRnCv7KdHUhSZy2H67M3VqUV+UxTo1BuWhFg2tvHPY38Q+RTEBtE8FHzTj+qeiEqD 14FQ== X-Gm-Message-State: APjAAAUgZuESDy0wBy8JL0rmzFWCZ176Vezkr8dArwyQqkyyzQtGIuYF CqO+/wICtA7wHr4mq8jNrx0n624Zopc= X-Google-Smtp-Source: APXvYqxr2Hc2BwLePhcRRV+kQsgBSH6q0wLq5yIhn4rxPZri2jXrXhcdPVdQezcQJHgnOddKtkjGtA== X-Received: by 2002:ac2:4428:: with SMTP id w8mr33255968lfl.99.1558366072822; Mon, 20 May 2019 08:27:52 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id d5sm3906205lji.85.2019.05.20.08.27.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 May 2019 08:27:52 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-platforms: PATCH v2 03/14] Marvell/Library: ArmadaBoardDescLib: Add PCIE information Date: Mon, 20 May 2019 17:27:16 +0200 Message-Id: <1558366047-15994-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558366047-15994-1-git-send-email-mw@semihalf.com> References: <1558366047-15994-1-git-send-email-mw@semihalf.com> Introduce new callback that can provide information about PCIE controller per-board description. A new structure is defined containing base addresses, windows/bus configuration and reset GPIO usage indication. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h index a6d39c4..2ad19aa 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -9,6 +9,7 @@ #define __ARMADA_BOARD_DESC_LIB_H__ #include +#include // // COMPHY controllers per-board description @@ -105,6 +106,51 @@ typedef struct { } MV_BOARD_XHCI_DESC; // +// PCIE controllers description +// +typedef struct { + EFI_PHYSICAL_ADDRESS PcieDbiAddress; + EFI_PHYSICAL_ADDRESS ConfigSpaceAddress; + BOOLEAN HaveResetGpio; + MV_GPIO_PIN PcieResetGpio; + UINT64 PcieBusMin; + UINT64 PcieBusMax; + UINT64 PcieIoTranslation; + UINT64 PcieIoWinBase; + UINT64 PcieIoWinSize; + UINT64 PcieMmio32Translation; + UINT64 PcieMmio32WinBase; + UINT64 PcieMmio32WinSize; + UINT64 PcieMmio64Translation; + UINT64 PcieMmio64WinBase; + UINT64 PcieMmio64WinSize; +} MV_PCIE_CONTROLLER; + +typedef struct { + MV_PCIE_CONTROLLER CONST *PcieControllers; + UINTN PcieControllerCount; +} MV_BOARD_PCIE_DESCRIPTION; + +/** + Return the number and description of PCIE controllers used on the platform. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, + IN OUT UINTN *PcieControllerCount + ); + +// // PP2 NIC devices per-board description // typedef struct { -- 2.7.4