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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id d5sm3906205lji.85.2019.05.20.08.27.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 May 2019 08:27:55 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-platforms: PATCH v2 05/14] Marvell/Armada7k8k: MvBoardDesc: Extend protocol with PCIE support Date: Mon, 20 May 2019 17:27:18 +0200 Message-Id: <1558366047-15994-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558366047-15994-1-git-send-email-mw@semihalf.com> References: <1558366047-15994-1-git-send-email-mw@semihalf.com> Introduce new callback that can provide information about PCIE controllers, which are used on the platform. According ArmadaSoCDescLib ArmadaBoardDescLib routines are used for obtaining required data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Protocol/BoardDesc.h | 22 +++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 86 ++++++++++++++++++++ 2 files changed, 108 insertions(+) diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell/Include/Protocol/BoardDesc.h index 02905ea..48f6d9d 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -90,6 +90,27 @@ EFI_STATUS IN OUT MV_BOARD_XHCI_DESC **XhciDesc ); +/** + Return the description of PCIE controllers used on the platform. + + @param[in out] *This Pointer to board description protocol. + @param[in out] **PcieDescription Array containing PCIE controllers' + description. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval EFI_INVALID_PARAMETER Description wrongly defined. + @retval EFI_OUT_OF_RESOURCES Lack of resources. + @retval Other Return error status. + +**/ +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_PCIE_DESCRIPTION_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PCIE_DESCRIPTION CONST **PcieDescription + ); + typedef EFI_STATUS (EFIAPI *MV_BOARD_DESC_PP2_GET) ( @@ -121,6 +142,7 @@ struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; MV_BOARD_DESC_FREE BoardDescFree; MV_BOARD_GPIO_DESCRIPTION_GET GpioDescriptionGet; + MV_BOARD_PCIE_DESCRIPTION_GET PcieDescriptionGet; }; #endif // __MARVELL_BOARD_DESC_PROTOCOL_H__ diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c index 973c362..042db28 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -36,6 +36,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. MV_BOARD_DESC *mBoardDescInstance; STATIC MV_BOARD_GPIO_DESCRIPTION *mGpioDescription; +STATIC MV_BOARD_PCIE_DESCRIPTION *mPcieDescription; STATIC EFI_STATUS @@ -444,6 +445,90 @@ MvBoardDescXhciGet ( return EFI_SUCCESS; } +/** + Return the description of PCIE controllers used on the platform. + + @param[in out] *This Pointer to board description protocol. + @param[in out] **PcieDescription Array containing PCIE controllers' + description. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval EFI_INVALID_PARAMETER Description wrongly defined. + @retval EFI_OUT_OF_RESOURCES Lack of resources. + @retval Other Return error status. + +**/ +STATIC +EFI_STATUS +MvBoardPcieDescriptionGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PCIE_DESCRIPTION CONST **PcieDescription + ) +{ + UINTN SoCPcieControllerCount, BoardPcieControllerCount, SoCIndex, BoardIndex; + EFI_PHYSICAL_ADDRESS *PcieDbiAddresses; + MV_PCIE_CONTROLLER CONST *PcieControllers; + EFI_STATUS Status; + + /* Use existing structure if already created. */ + if (mPcieDescription != NULL) { + *PcieDescription = mPcieDescription; + return EFI_SUCCESS; + } + + /* Get SoC data about all available PCIE controllers. */ + Status = ArmadaSoCPcieGet (&PcieDbiAddresses, &SoCPcieControllerCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Get per-board information about all used PCIE controllers. */ + Status = ArmadaBoardPcieControllerGet (&PcieControllers, + &BoardPcieControllerCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Sanity check of the board description. */ + if (BoardPcieControllerCount > SoCPcieControllerCount) { + DEBUG ((DEBUG_ERROR, "%a: Too many controllers described\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + for (BoardIndex = 0; BoardIndex < BoardPcieControllerCount; BoardIndex++) { + for (SoCIndex = 0; SoCIndex < SoCPcieControllerCount; SoCIndex++) { + if (PcieControllers[BoardIndex].PcieDbiAddress == + PcieDbiAddresses[SoCIndex]) { + /* Match found */ + break; + } + } + if (SoCIndex == SoCPcieControllerCount) { + DEBUG ((DEBUG_ERROR, + "%a: Controller #%d base address invalid: 0x%x\n", + __FUNCTION__, + BoardIndex, + PcieControllers[BoardIndex].PcieDbiAddress)); + return EFI_INVALID_PARAMETER; + } + } + + /* Allocate and fill board description. */ + mPcieDescription = AllocateZeroPool (sizeof (MV_BOARD_PCIE_DESCRIPTION)); + if (mPcieDescription == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + mPcieDescription->PcieControllers = PcieControllers; + mPcieDescription->PcieControllerCount = BoardPcieControllerCount; + + *PcieDescription = mPcieDescription; + + return EFI_SUCCESS; +} + STATIC EFI_STATUS MvBoardDescPp2Get ( @@ -621,6 +706,7 @@ MvBoardDescInitProtocol ( BoardDescProtocol->BoardDescXhciGet = MvBoardDescXhciGet; BoardDescProtocol->BoardDescFree = MvBoardDescFree; BoardDescProtocol->GpioDescriptionGet = MvBoardGpioDescriptionGet; + BoardDescProtocol->PcieDescriptionGet = MvBoardPcieDescriptionGet; return EFI_SUCCESS; } -- 2.7.4