From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=OCgFA1B2; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.65, mailfrom: mw@semihalf.com) Received: from mail-lf1-f65.google.com (mail-lf1-f65.google.com [209.85.167.65]) by groups.io with SMTP; Fri, 24 May 2019 08:59:33 -0700 Received: by mail-lf1-f65.google.com with SMTP id u27so7528342lfg.10 for ; Fri, 24 May 2019 08:59:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zcuL8j07/fKBk9K8JD1tUf1xj7cjRgVQWldGbTyvEnA=; b=OCgFA1B2Lk9aOaHYjeIh6W9cLGYBeAejNdABTjBbQ6OxXTQOEmw7keqy7CCNmpbM9f PbuRK3vtbvGTMGTjvKEMnmI9T9b4HwYmmiCWnuKugOLhVlnawabh8usHQsF4Fbnp2Pli Dv/Cv+l8KexwShF35CSN1cWHLAKSYLWgUORp5hv2gNq2VNjRlTrjAmB5UzwHz2HrJkjy vQlELLm4A+d8/IUJwDcdfwcNkZ4nzfLGXwQnBxawybIhOYPbKkwrOu7nTZylza59A480 mTAdSqyAFubzFBPQ44R49By8K0mfFD/SVn1pVZ4enwIQ2q+30dhsowvdyAYHVFbajRBW XNZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zcuL8j07/fKBk9K8JD1tUf1xj7cjRgVQWldGbTyvEnA=; b=O22S8/eHYEIRv8z7rQe008588ktk/mX2/srmck2MTf1bGjI/xTyYa8ttttj+PhSGhD D0TVUme+kM7Vxcfl2x0m7p4YZvMvvovi4LQRjZmB/5OMA/kba4yuV9Uj8VCJUG8DI6f/ ar35JY+ByUsUHglC2gT0kNzMlhRshh0gqxILbvti78FMsxkx9UHYB+0Sa6iZ7g/yoadv 6rnvozHEAOpD5npCizQ8NysnNzJ+jqqxE/LrLHYnMG9gOhibAuj5dkX34GhCNcJ1Ei1v 4+wvIHhsBkkvL08P8JPp95OvK029FlQkQAfJakpWLlzRgMj1aOliV7SbzlXW4vfq5rGd fQRg== X-Gm-Message-State: APjAAAVbLQv9mHXnVk7nAuy9Yr8ayye+Vfcuh9+/aUU7M9mzSGiUE8ue b3a7w4s3TIonVl0PidN7XM4pYRlIZikGgA== X-Google-Smtp-Source: APXvYqzUWvzb3zPLJU1BU8G4S81Kyd1R3W9lUoIQUu+jvg7mveubawffmuGATrGKc8Rt2lm7sF4H0g== X-Received: by 2002:a19:4f54:: with SMTP id a20mr50802010lfk.136.1558713571505; Fri, 24 May 2019 08:59:31 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id d18sm685280lfl.95.2019.05.24.08.59.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 May 2019 08:59:30 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com, Jici.Gao@arm.com, rebecca@bluestop.org, kettenis@jive.eu Subject: [edk2-platforms: PATCH v3 03/14] Marvell/Library: ArmadaBoardDescLib: Add PCIE information Date: Fri, 24 May 2019 17:59:00 +0200 Message-Id: <1558713551-25363-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558713551-25363-1-git-send-email-mw@semihalf.com> References: <1558713551-25363-1-git-send-email-mw@semihalf.com> Introduce new callback that can provide information about PCIE controller per-board description. A new structure is defined containing base addresses, windows/bus configuration and reset GPIO usage indication. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h index a6d39c4..2ad19aa 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -9,6 +9,7 @@ #define __ARMADA_BOARD_DESC_LIB_H__ #include +#include // // COMPHY controllers per-board description @@ -105,6 +106,51 @@ typedef struct { } MV_BOARD_XHCI_DESC; // +// PCIE controllers description +// +typedef struct { + EFI_PHYSICAL_ADDRESS PcieDbiAddress; + EFI_PHYSICAL_ADDRESS ConfigSpaceAddress; + BOOLEAN HaveResetGpio; + MV_GPIO_PIN PcieResetGpio; + UINT64 PcieBusMin; + UINT64 PcieBusMax; + UINT64 PcieIoTranslation; + UINT64 PcieIoWinBase; + UINT64 PcieIoWinSize; + UINT64 PcieMmio32Translation; + UINT64 PcieMmio32WinBase; + UINT64 PcieMmio32WinSize; + UINT64 PcieMmio64Translation; + UINT64 PcieMmio64WinBase; + UINT64 PcieMmio64WinSize; +} MV_PCIE_CONTROLLER; + +typedef struct { + MV_PCIE_CONTROLLER CONST *PcieControllers; + UINTN PcieControllerCount; +} MV_BOARD_PCIE_DESCRIPTION; + +/** + Return the number and description of PCIE controllers used on the platform. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval EFI_NOT_FOUND None of the controllers is used. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, + IN OUT UINTN *PcieControllerCount + ); + +// // PP2 NIC devices per-board description // typedef struct { -- 2.7.4