From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=fslBWijr; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.196, mailfrom: mw@semihalf.com) Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by groups.io with SMTP; Wed, 26 Jun 2019 00:04:34 -0700 Received: by mail-lj1-f196.google.com with SMTP id t28so1012800lje.9 for ; Wed, 26 Jun 2019 00:04:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=o6AXPp4OnjDnZ2CQhKeGl4D8SgQonsHgb0IYb+E9bKo=; b=fslBWijrFALHtegPiDoCC4Pu2ZSvNRwwFvf88kHYmwGbdb8tPKEi0YXW+J+snwPyPO LZ1tNz6QjDl9t68xYmDFS02Yn0c6d3m/4iSlHEEDmm6tBH0MV0rlxCO1y0Q+BPsOprnr 9y/+acP/2DoumU3FIMATrEhEZyt5QiEqxoH5inOOJ7rSvPepujzi8/VPYt3m/ctGOSvY 7sK0heBBLzRAv2uj6N2rNp15juxzPgP3DUkzEO17l32khX4vANYC1uJTFFJep0rTAS2H cjTPzhE3kgSUsvhF0rDfcNV3lkVoGo9ZP/Zj7mJhngzpMlDkoNmM8ho7RgFuGZb9dWca qd2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=o6AXPp4OnjDnZ2CQhKeGl4D8SgQonsHgb0IYb+E9bKo=; b=rugcAAHA4QTP60I13ANPpiyE3GpWV09HzqLFPWJwgsRAL30d1vjQbp71ewqnkTYlZy 2+5KWuYEZNoOtM0goa3WuhPTnH2LVrXXARQPeOTmWiWrbwFNHUZl17Wfg2TQBusbhDTM BdpLZL11R+rWmMN72t7gh5+exhyUHQm1/uyz/KAPd4lx1E5cPC8osk3yfjhpSyvioMCs A/7xiMnejQ3+ls1+R4S57gguQWn+ym4A3L4D5KvhYt10k6iNGlxzx2l9x6UWaijJ8Dmm ca56HUjhohl/oX7G3qkhnf8WlnI6eD1kRrHwcQbUTYFeCPk4Y8+7+8FijzqU/29ynjqM AvYA== X-Gm-Message-State: APjAAAW2A9V3fZiYukxxW57ZxD4c+ypxDaBvtVVVHwCG1wa4tnUnXRrA sEvU1QMhOjWXVYBObf+wyvkBPPNyFgBE5Q== X-Google-Smtp-Source: APXvYqy7pKKBBQT3XfatFpYkaXwF7MPu4IvO++leFrPraa187M2W2N5uD933HCioOhGqBg53BsjWbw== X-Received: by 2002:a2e:94cb:: with SMTP id r11mr1711500ljh.212.1561532671802; Wed, 26 Jun 2019 00:04:31 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p29sm2657101ljp.87.2019.06.26.00.04.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Jun 2019 00:04:31 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-platforms: PATCH] Marvell/Drivers: XenonDxe: Explicitly disable HS400 Date: Wed, 26 Jun 2019 09:04:14 +0200 Message-Id: <1561532654-6277-1-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 Ensure that in case of SlowMode or 3.3V operation, also the HS400 capability will be disabled in the SdMmc driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h | 1 + Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h index 8bf1835..2d7c7f0 100644 --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h @@ -82,6 +82,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define SDHC_CAP_SDR50 BIT32 #define SDHC_CAP_SDR104 BIT33 #define SDHC_CAP_DDR50 BIT34 +#define SDHC_CAP_HS400 BIT63 #define SDHC_MAX_CURRENT_CAP 0x0048 #define SDHC_FORCE_EVT_AUTO_CMD 0x0050 #define SDHC_FORCE_EVT_ERR_INT 0x0052 diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c index 7a9266e..55ebcf8 100644 --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c @@ -357,7 +357,8 @@ XenonSdMmcCapability ( Capability &= ~(UINT64)(SDHC_CAP_VOLTAGE_33 | SDHC_CAP_VOLTAGE_30); } else { Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | - SDHC_CAP_SDR50 | SDHC_CAP_VOLTAGE_18); + SDHC_CAP_SDR50 | SDHC_CAP_HS400 | + SDHC_CAP_VOLTAGE_18); } if (!SdMmcDesc.Xenon8BitBusEnabled) { @@ -365,7 +366,7 @@ XenonSdMmcCapability ( } if (SdMmcDesc.XenonSlowModeEnabled) { - Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50); + Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | SDHC_CAP_HS400); } Capability &= ~(UINT64)(SDHC_CAP_SLOT_TYPE_MASK); -- 2.7.4