From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=W76Ryu6s; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.193, mailfrom: mw@semihalf.com) Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by groups.io with SMTP; Wed, 07 Aug 2019 12:46:38 -0700 Received: by mail-lj1-f193.google.com with SMTP id r9so86599577ljg.5 for ; Wed, 07 Aug 2019 12:46:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=dn2sQVLYp1A8fzGD2vuk7WhnWbIZYYViZJyb/IOzNZ0=; b=W76Ryu6sr1C5/p0UbMBYkHTaoFpdP+gSK/XidhAOYnzfouyl5NZDnYg7mjUTgh6rCa Vwg7WCoPhb2Rm/wo+8iNFGUxQSMmmXjWm7PoJ8ruAvdTTqR4tfgaTvEboQXeupV9C85r kB7oa0zBKSvyg4OZ5ceirpG7zL8Q7jRuto2Q9rXI5aDB0qa7i+fPsXeKEA2JyFMRqxXU tFOu5Ki4YoAFYyBO3cH/SbPbY6hivubWzwS879chEmXZA+imRwbP7hEIuZacysp/8by5 0KADEMNle+F5sTfoEsIoApe+aDPTC3cic+zGpcZ5UqTMy898nDKK/0Tnpyx7hH5mVSgg 9Raw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=dn2sQVLYp1A8fzGD2vuk7WhnWbIZYYViZJyb/IOzNZ0=; b=DasDO3gYNtDyRoRc0bWnzdsh5pGXEoQQUyfEb+NF9YAFpkMAdls72LAWcRNAjqmXll DIZhtQO7+MO11F34MjABNIrtR2W1uYsj9tGMZjNdHCWlq+LSJK/EzBppTrf+oIOMCOJu 1b9MLVak00/qJzsnkTJ8rClAhLVjHiIDJEDldMhUNq9M1UpIRjm+2F6vRHb8Rv42fOJZ JnTdCDcSSpnI4uXiSHRG7DF7jKD3lBTb2hxkZIU7gbKTNw002VWpRs3sn/r3NKOXOw0L i9rKFKk3OTugMnsbDGTeNGVJzzlTvb5AYTPyOr2xr3tREL5LIoVe7cEQBM7/HsOf8K+F f5ew== X-Gm-Message-State: APjAAAVXNtw8Ib3OrDdsQQbxx+mDe277VHYgZ93ZkA9IJtccAcAnNwMb HP2XqoMW0yLNnnA4FFiBH61x9VmF8man7w== X-Google-Smtp-Source: APXvYqzJGu+nc+wZTCIYdRALf2w4bQLXjnuwLYdwA+seTcpKMuZY1KkVMm9Ya17THbZwIxVDP2vMtQ== X-Received: by 2002:a2e:9657:: with SMTP id z23mr5622176ljh.116.1565207196004; Wed, 07 Aug 2019 12:46:36 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h11sm16691071lfm.14.2019.08.07.12.46.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Aug 2019 12:46:35 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-platforms: PATCH v2] Marvell/Drivers: XenonDxe: Explicitly disable HS400 Date: Wed, 7 Aug 2019 21:46:12 +0200 Message-Id: <1565207172-8921-1-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 On another SoC revision, the capability register marks HS400 support as enabled. However in case the interface itself is powered with 3.3V this flag must be unset by the SdMmcOverride protocol callback - otherwise the generic EmmcSwitchToHS400 () would be executed with a failure. Ensure that in case of SlowMode or 3.3V operation, the HS400 capability will be disabled in the SdMmc driver, along with other highest-speed modes. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h | 1 + Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h index afc2b2f..2ad23e2 100644 --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h @@ -55,6 +55,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define SDHC_CAP_SDR50 BIT32 #define SDHC_CAP_SDR104 BIT33 #define SDHC_CAP_DDR50 BIT34 +#define SDHC_CAP_HS400 BIT63 #define SDHC_MAX_CURRENT_CAP 0x0048 #define SDHC_FORCE_EVT_AUTO_CMD 0x0050 #define SDHC_FORCE_EVT_ERR_INT 0x0052 diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c index 3b54459..afd650b 100644 --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c @@ -330,7 +330,8 @@ XenonSdMmcCapability ( Capability &= ~(UINT64)(SDHC_CAP_VOLTAGE_33 | SDHC_CAP_VOLTAGE_30); } else { Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | - SDHC_CAP_SDR50 | SDHC_CAP_VOLTAGE_18); + SDHC_CAP_SDR50 | SDHC_CAP_HS400 | + SDHC_CAP_VOLTAGE_18); } if (!SdMmcDesc.Xenon8BitBusEnabled) { @@ -338,7 +339,7 @@ XenonSdMmcCapability ( } if (SdMmcDesc.XenonSlowModeEnabled) { - Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50); + Capability &= ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | SDHC_CAP_HS400); } Capability &= ~(UINT64)(SDHC_CAP_SLOT_TYPE_MASK); -- 2.7.4