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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id i62sm18359206lji.14.2019.08.07.16.30.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Aug 2019 16:30:54 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-platforms: PATCH 4/9] Marvell/Library: ArmadaSoCDescLib: Extend Xenon information Date: Thu, 8 Aug 2019 01:30:25 +0200 Message-Id: <1565220630-1653-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565220630-1653-1-git-send-email-mw@semihalf.com> References: <1565220630-1653-1-git-send-email-mw@semihalf.com> Hitherto SoC description library code assumed that there could be only two Xenon SdMmc controller instances in the SoC. Remove this limitation, so that to support CN913x SoCs, which may have up to 4 of such interfaces. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 5 +-- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 34 +++++++++++++------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h index 0296d43..265b4f4 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h @@ -90,8 +90,9 @@ // // Platform description of SDMMC controllers // -#define MV_SOC_MAX_SDMMC_COUNT 2 -#define MV_SOC_SDMMC_BASE(Index) ((Index) == 0 ? 0xF06E0000 : 0xF2780000) +#define MV_SOC_SDMMC_PER_CP_COUNT 1 +#define MV_SOC_AP80X_SDMMC_BASE 0xF06E0000 +#define MV_SOC_CP_SDMMC_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x780000) // // Platform description of UTMI PHY's diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c index 5947601..3ffd57e 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c @@ -349,26 +349,36 @@ EFI_STATUS EFIAPI ArmadaSoCDescSdMmcGet ( IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, - IN OUT UINTN *DescCount + IN OUT UINTN *Count ) { - MV_SOC_SDMMC_DESC *Desc; - UINTN Index; + MV_SOC_SDMMC_DESC *SdMmc; + UINTN CpCount, CpIndex; - Desc = AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC_DESC)); - if (Desc == NULL) { + CpCount = FixedPcdGet8 (PcdMaxCpCount); + + *Count = CpCount * MV_SOC_SDMMC_PER_CP_COUNT + MV_SOC_AP806_COUNT; + SdMmc = AllocateZeroPool (*Count * sizeof (MV_SOC_SDMMC_DESC)); + if (SdMmc == NULL) { DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); return EFI_OUT_OF_RESOURCES; } - for (Index = 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) { - Desc[Index].SdMmcBaseAddress = MV_SOC_SDMMC_BASE (Index); - Desc[Index].SdMmcMemSize = SIZE_1KB; - Desc[Index].SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent; - } + *SdMmcDesc = SdMmc; + + /* AP80x controller */ + SdMmc->SdMmcBaseAddress = MV_SOC_AP80X_SDMMC_BASE; + SdMmc->SdMmcMemSize = SIZE_1KB; + SdMmc->SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent; + SdMmc++; - *SdMmcDesc = Desc; - *DescCount = MV_SOC_MAX_SDMMC_COUNT; + /* CP11x controllers */ + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) { + SdMmc->SdMmcBaseAddress = MV_SOC_CP_SDMMC_BASE (CpIndex); + SdMmc->SdMmcMemSize = SIZE_1KB; + SdMmc->SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent; + SdMmc++; + } return EFI_SUCCESS; } -- 2.7.4