* [edk2-platforms: PATCH 1/9] Marvell/Cn9130Db: Add ACPI tables
2019-08-07 23:30 [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
@ 2019-08-07 23:30 ` Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 2/9] Marvell/Cn9130Db: Add DeviceTree Marcin Wojtas
` (8 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-07 23:30 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
This patch adds ACPI tables and necessary headers,
which are common for Cn913x SoCs and the CN9130 development board
(variant A). Wiring up of support will be done in the follow-up
commits.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 56 ++++
| 37 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h | 20 ++
Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 36 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 324 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc | 41 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc | 80 +++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc | 58 ++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc | 135 ++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc | 210 +++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 49 +++
11 files changed, 1046 insertions(+)
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
new file mode 100644
index 0000000..191a747
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
@@ -0,0 +1,56 @@
+## @file
+# Component description file for PlatformAcpiTables module.
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Cn913xDbA/Dsdt.asl
+ Cn913xDbA/Mcfg.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Pptt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+[BuildOptions]
+ *_*_*_ASLCC_FLAGS = -DCN9130
--git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
new file mode 100644
index 0000000..b5fd397
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
@@ -0,0 +1,37 @@
+/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '}
+#define ACPI_OEM_REVISION 0
+#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O')
+#define ACPI_CREATOR_REVISION 0
+
+#if defined(CN9130)
+#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ',' ')
+#endif
+
+/**
+ * A macro to initialize the common header part of EFI ACPI tables
+ * as defined by EFI_ACPI_DESCRIPTION_HEADER structure.
+ **/
+#define __ACPI_HEADER(sign, type, rev) { \
+ sign, /* UINT32 Signature */ \
+ sizeof (type), /* UINT32 Length */ \
+ rev, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ ACPI_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \
+ ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ ACPI_OEM_REVISION, /* UINT32 OemRevision */ \
+ ACPI_CREATOR_ID, /* UINT32 CreatorId */ \
+ ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h
new file mode 100644
index 0000000..634bd8d
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h
@@ -0,0 +1,20 @@
+/**
+
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#define PCI_BUS_MIN 0x0
+#define PCI_BUS_MAX 0x0
+#define PCI_BUS_COUNT 0x1
+#define PCI_MMIO32_BASE 0xC0000000
+#define PCI_MMIO32_SIZE 0x10000000
+#define PCI_MMIO64_BASE 0x800000000
+#define PCI_MMIO64_SIZE 0x100000000
+#define PCI_IO_BASE 0x0
+#define PCI_IO_SIZE 0x10000
+#define PCI_IO_TRANSLATION 0xDFF00000
+#define PCI_ECAM_BASE 0xD0008000
+#define PCI_ECAM_SIZE 0x10000000
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
new file mode 100644
index 0000000..6befe2a
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
@@ -0,0 +1,36 @@
+/**
+
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ Glossary - abbreviations used in Marvell SampleAtReset library implementation:
+ ICU - Interrupt Consolidation Unit
+ AP - Application Processor hardware block (CN913x incorporates AP807)
+ CP - South Bridge hardware blocks (CN913x incorporates CP115)
+
+**/
+
+#define CP_GIC_SPI_CP0_PCI0 64
+#define CP_GIC_SPI_CP0_PCI1 65
+#define CP_GIC_SPI_CP0_PCI2 66
+#define CP_GIC_SPI_CP0_SDMMC 67
+#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127
+#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126
+#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125
+#define CP_GIC_SPI_CP0_EIP_RNG0 105
+#define CP_GIC_SPI_CP0_USB_H1 112
+#define CP_GIC_SPI_CP0_USB_H0 113
+#define CP_GIC_SPI_CP0_SATA_H0 114
+
+#define CP_GIC_SPI_CP1_PCI0 288
+#define CP_GIC_SPI_CP1_PCI1 289
+#define CP_GIC_SPI_CP1_PCI2 290
+#define CP_GIC_SPI_CP1_SDMMC 291
+#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351
+#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350
+#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349
+#define CP_GIC_SPI_CP1_EIP_RNG0 329
+#define CP_GIC_SPI_CP1_USB_H1 336
+#define CP_GIC_SPI_CP1_USB_H0 337
+#define CP_GIC_SPI_CP1_SATA_H0 338
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
new file mode 100644
index 0000000..5f9ba8a
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
@@ -0,0 +1,324 @@
+/** @file
+
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Cn913xDbA/Pcie.h"
+#include "IcuInterrupts.h"
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130DBA", 3)
+{
+ Scope (_SB)
+ {
+ Device (CPU0)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x000) // _UID: Unique ID
+ }
+ Device (CPU1)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x001) // _UID: Unique ID
+ }
+ Device (CPU2)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x100) // _UID: Unique ID
+ }
+ Device (CPU3)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x101) // _UID: Unique ID
+ }
+
+ Device (AHC0)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2540000, // Address Base (MMIO)
+ 0x00030000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_SATA_H0
+ }
+ })
+ }
+
+ Device (XHC0)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2500000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H0
+ }
+ })
+ }
+
+ Device (XHC1)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2510000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H1
+ }
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, "MRVL0001") // _HID: Hardware ID
+ Name (_CID, "HISI0031") // _CID: Compatible ID
+ Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ FixedPcdGet64(PcdSerialRegisterBase), // Address Base
+ 0x00000100, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 51
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) },
+ Package () { "reg-io-width", 1 },
+ Package () { "reg-shift", 2 },
+ }
+ })
+ }
+
+ Device (PP20)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "10gbase-kr"},
+ }
+ })
+ }
+ Device (ETH1)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT1
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 1 },
+ Package () { "gop-port-id", 2 },
+ Package () { "phy-mode", "rgmii-id"},
+ }
+ })
+ }
+ Device (ETH2)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT2
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 2 },
+ Package () { "gop-port-id", 3 },
+ Package () { "phy-mode", "rgmii-id"},
+ }
+ })
+ }
+ }
+
+ Device (RNG0)
+ {
+ Name (_HID, "PRP0001") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ CP_GIC_SPI_CP0_EIP_RNG0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "inside-secure,safexcel-eip76" },
+ }
+ })
+ }
+
+ //
+ // PCIe Root Bus
+ //
+ Device (PCI0)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x00) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }
+ })
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ PCI_BUS_MIN, // Range Minimum
+ PCI_BUS_MAX, // Range Maximum
+ 0x0000, // Translation Offset
+ PCI_BUS_COUNT // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ PCI_MMIO32_BASE, // Range Minimum
+ 0xCFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ PCI_MMIO32_SIZE // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ PCI_IO_BASE, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ PCI_IO_TRANSLATION, // Translation Address
+ PCI_IO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ PCI_ECAM_BASE,
+ PCI_ECAM_SIZE
+ )
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+ }
+ }
+}
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc
new file mode 100644
index 0000000..88f59ab
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc
@@ -0,0 +1,41 @@
+/** @file
+
+ Memory mapped config space base address table (MCFG)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+#include "Cn913xDbA/Pcie.h"
+
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure;
+} ACPI_6_0_MCFG_STRUCTURE;
+#pragma pack()
+
+STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg = {
+ {
+ __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ ACPI_6_0_MCFG_STRUCTURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+ EFI_ACPI_RESERVED_QWORD
+ }, {
+ PCI_ECAM_BASE, // BaseAddress
+ 0, // PciSegmentGroupNumber
+ PCI_BUS_MIN, // StartBusNumber
+ PCI_BUS_MAX, // EndBusNumber
+ EFI_ACPI_RESERVED_DWORD // Reserved
+ }
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc
new file mode 100644
index 0000000..ea396bd
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc
@@ -0,0 +1,80 @@
+/** @file
+
+ Fixed ACPI Description Table (FADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+#define FADT_FLAGS EFI_ACPI_6_0_HW_REDUCED_ACPI | \
+ EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE | \
+ EFI_ACPI_6_0_HEADLESS
+
+EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ __ACPI_HEADER (EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ FADT_FLAGS, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorVersion
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc
new file mode 100644
index 0000000..46bfe37
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc
@@ -0,0 +1,58 @@
+/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+// active low, level triggered
+#define GTDT_GTIMER_FLAGS EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+
+// active high, level triggered
+#define GTDT_WDG_FLAGS 0x0
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Header;
+ EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE SbsaWatchdog;
+} ACPI_6_0_GTDT_STRUCTURE;
+#pragma pack()
+
+ACPI_6_0_GTDT_STRUCTURE Gtdt = {
+ {
+ __ACPI_HEADER (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ ACPI_6_0_GTDT_STRUCTURE,
+ EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION),
+ 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecureEL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecureEL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBaseAddress
+ 0x1, // UINT32 PlatformTimerCount
+ sizeof (Gtdt.Header) // UINT32 PlatformTimerOffset
+ }, {
+ EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type
+ sizeof (Gtdt.SbsaWatchdog), // UINT16 Length
+ 0x0, // UINT8 Reserved
+ FixedPcdGet64 (PcdGenericWatchdogRefreshBase), // UINT64 RefreshFramePhysicalAddress
+ FixedPcdGet64 (PcdGenericWatchdogControlBase), // UINT64 WatchdogControlFramePhysicalAddress
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), // UINT32 WatchdogTimerGSIV
+ GTDT_WDG_FLAGS // UINT32 WatchdogTimerFlags
+ },
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc
new file mode 100644
index 0000000..abd3cfc
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc
@@ -0,0 +1,135 @@
+/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+#define GICC_BASE FixedPcdGet64 (PcdGicInterruptInterfaceBase)
+#define GICD_BASE FixedPcdGet64 (PcdGicDistributorBase)
+#define GICH_BASE 0xF0240000
+#define GICV_BASE 0xF0260000
+#define VGIC_MAINT_INT 25
+
+#define GIC_MSI_FRAME0 0xF0280000
+#define GIC_MSI_FRAME1 0xF0290000
+#define GIC_MSI_FRAME2 0xF02A0000
+#define GIC_MSI_FRAME3 0xF02B0000
+
+#define PMU_INTERRUPT_CPU0 130
+#define PMU_INTERRUPT_CPU1 131
+#define PMU_INTERRUPT_CPU2 132
+#define PMU_INTERRUPT_CPU3 133
+
+#define PMU_INTERRUPT_FLAG EFI_ACPI_6_0_GIC_ENABLED | EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL
+
+#pragma pack(push, 1)
+typedef struct {
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_0_GIC_STRUCTURE GicC[4];
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicD;
+ EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE GicM[4];
+} ACPI_6_0_MADT_STRUCTURE;
+#pragma pack(pop)
+
+
+ACPI_6_0_MADT_STRUCTURE Madt = {
+ {
+ __ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ ACPI_6_0_MADT_STRUCTURE,
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
+ 0, // UINT32 LocalApicAddress
+ 0 // UINT32 Flags
+ },
+ {
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, // GicId
+ 0x000, // AcpiCpuUid
+ 0x000, // Mpidr
+ PMU_INTERRUPT_FLAG, // Flags
+ PMU_INTERRUPT_CPU0, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, // GicId
+ 0x001, // AcpiCpuUid
+ 0x001, // Mpidr
+ PMU_INTERRUPT_FLAG, // Flags
+ PMU_INTERRUPT_CPU1, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, // GicId
+ 0x100, // AcpiCpuUid
+ 0x100, // Mpidr
+ PMU_INTERRUPT_FLAG, // Flags
+ PMU_INTERRUPT_CPU2, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, // GicId
+ 0x101, // AcpiCpuUid
+ 0x101, // Mpidr
+ PMU_INTERRUPT_FLAG, // Flags
+ PMU_INTERRUPT_CPU3, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ },
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0x0, // GicDistHwId
+ GICD_BASE, // GicDistBase
+ 0x0, // GicDistVector
+ EFI_ACPI_6_0_GIC_V2 // GicVersion
+ ),
+ {
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x0, // GicMsiFrameId
+ GIC_MSI_FRAME0, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x1, // GicMsiFrameId
+ GIC_MSI_FRAME1, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x2, // GicMsiFrameId
+ GIC_MSI_FRAME2, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x3, // GicMsiFrameId
+ GIC_MSI_FRAME3, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ }
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Madt;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc
new file mode 100644
index 0000000..f37c751
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc
@@ -0,0 +1,210 @@
+/** @file
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiHeader.h"
+
+#define NUM_CORES FixedPcdGet64 (PcdCoreCount)
+
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 Offset[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache;
+} ACPI_6_2_PPTT_CORE;
+
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset[1];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache;
+ ACPI_6_2_PPTT_CORE Cores[2];
+} ACPI_6_2_PPTT_CLUSTER;
+
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset[1];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache;
+ ACPI_6_2_PPTT_CLUSTER Clusters[NUM_CORES / 2];
+} ACPI_6_2_PPTT_PACKAGE;
+
+typedef struct {
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt;
+ ACPI_6_2_PPTT_PACKAGE Packages[1];
+} ACPI_6_2_PPTT_STRUCTURE;
+#pragma pack()
+
+#define PPTT_CORE(pid, cid, id) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_CORE, DCache), \
+ {}, \
+ { \
+ 0, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \
+ }, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, \
+ Packages[pid].Clusters[cid]), /* Parent */ \
+ 256 * (cid) + (id), /* AcpiProcessorId */ \
+ 2, /* NumberOfPrivateResources */ \
+ }, { \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, \
+ Packages[pid].Clusters[cid].Cores[id].DCache), \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, \
+ Packages[pid].Clusters[cid].Cores[id].ICache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_32KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 2, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 0, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ 3 * SIZE_16KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 3, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType */ \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ 0, /* WritePolicy */ \
+ }, \
+ 64 /* LineSize */ \
+ } \
+}
+
+#define PPTT_CLUSTER(pid, cid) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_CLUSTER, L2Cache), \
+ {}, \
+ { \
+ 0, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
+ }, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid]), /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 1, /* NumberOfPrivateResources */ \
+ }, { \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid].Clusters[cid].L2Cache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_512KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 16, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ PPTT_CORE(pid, cid, 0), \
+ PPTT_CORE(pid, cid, 1), \
+ } \
+}
+
+ACPI_6_2_PPTT_STRUCTURE Pptt = {
+ {
+ __ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ ACPI_6_2_PPTT_STRUCTURE,
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION),
+ },
+ {
+ {
+ {
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR,
+ FIELD_OFFSET (ACPI_6_2_PPTT_PACKAGE, L3Cache),
+ {},
+ {
+ 1, /* PhysicalPackage */
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */
+ },
+ 0, /* Parent */
+ 0, /* AcpiProcessorId */
+ 1, /* NumberOfPrivateResources */
+ }, {
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[0].L3Cache),
+ }, {
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE,
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE),
+ {},
+ {
+ 1, /* SizePropertyValid */
+ 1, /* NumberOfSetsValid */
+ 1, /* AssociativityValid */
+ 1, /* AllocationTypeValid */
+ 1, /* CacheTypeValid */
+ 1, /* WritePolicyValid */
+ 1, /* LineSizeValid */
+ },
+ 0, /* NextLevelOfCache */
+ SIZE_1MB, /* Size */
+ 2048, /* NumberOfSets */
+ 8, /* Associativity */
+ {
+ 0, /* AllocationType */
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK,
+ },
+ 64 /* LineSize */
+ }, {
+ PPTT_CLUSTER (0, 0),
+#if NUM_CORES > 3
+ PPTT_CLUSTER (0, 1),
+#endif
+ }
+ }
+ }
+};
+
+VOID * CONST ReferenceAcpiTable = &Pptt;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
new file mode 100644
index 0000000..f663d8a
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
@@ -0,0 +1,49 @@
+/** @file
+ Serial Port Console Redirection Table (SPCR)
+
+ Copyright (c) 2017, Linaro Limited. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_0_BYTE, Address }
+
+EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION
+ ),
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, // InterfaceType
+ { EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE }, // Reserved1[3]
+ MV_UART_AS32 (FixedPcdGet64(PcdSerialRegisterBase)), // BaseAddress
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, // InterruptType
+ 0, // Irq
+ 51, // GlobalSystemInterrupt
+ 0, // BaudRate
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, // Parity
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, // StopBits
+ 0, // FlowControl
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, // TerminalType
+ EFI_ACPI_RESERVED_BYTE, // Language
+ 0xFFFF, // PciDeviceId
+ 0xFFFF, // PciVendorId
+ 0, // PciBusNumber
+ 0, // PciDeviceNumber
+ 0, // PciFunctionNumber
+ 0, // PciFlags
+ 0, // PciSegment
+ EFI_ACPI_RESERVED_DWORD // Reserved2
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Spcr;
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms: PATCH 2/9] Marvell/Cn9130Db: Add DeviceTree
2019-08-07 23:30 [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 1/9] Marvell/Cn9130Db: Add ACPI tables Marcin Wojtas
@ 2019-08-07 23:30 ` Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 3/9] Marvell/Cn9130Db: Introduce board support Marcin Wojtas
` (7 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-07 23:30 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
This patch adds device tree sources which are common for Cn913x SoCs
and the CN9130 development board (variant A). Wiring up of support
will be done in the follow-up commits.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf | 22 +
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi | 43 ++
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi | 264 ++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi | 10 +
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi | 552 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts | 185 +++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi | 168 ++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi | 126 +++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts | 29 +
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi | 173 ++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 76 +++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 151 ++++++
12 files changed, 1799 insertions(+)
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
new file mode 100644
index 0000000..091a5b4
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
@@ -0,0 +1,22 @@
+## @file
+#
+# Device tree description of the Marvell CN9130-DB-A platform
+#
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9130DbADeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ cn9130-db-A.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
new file mode 100644
index 0000000..bae0ed9
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#include "armada-ap806.dtsi"
+
+/ {
+ model = "Marvell Armada AP806 Quad";
+ compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x000>;
+ enable-method = "psci";
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+ };
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
new file mode 100644
index 0000000..66124bf
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#define IRQ_TYPE_LEVEL_HIGH (1 << 2)
+#define IRQ_TYPE_LEVEL_LOW (1 << 3)
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
+
+/dts-v1/;
+
+/ {
+ model = "Marvell Armada AP806";
+ compatible = "marvell,armada-ap806";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ gpio0 = &ap_gpio;
+ spi0 = &spi0;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ ap806 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space@f0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0xf0000000 0x1000000>;
+
+ gic: interrupt-controller@210000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x210000 0x10000>,
+ <0x220000 0x20000>,
+ <0x240000 0x20000>,
+ <0x260000 0x20000>;
+
+ gic_v2m0: v2m@280000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x280000 0x1000>;
+ arm,msi-base-spi = <160>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m1: v2m@290000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x290000 0x1000>;
+ arm,msi-base-spi = <192>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m2: v2m@2a0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2a0000 0x1000>;
+ arm,msi-base-spi = <224>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m3: v2m@2b0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2b0000 0x1000>;
+ arm,msi-base-spi = <256>;
+ arm,msi-num-spis = <32>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupt-parent = <&pic>;
+ interrupts = <17>;
+ };
+
+ odmi: odmi@300000 {
+ compatible = "marvell,odmi-controller";
+ interrupt-controller;
+ msi-controller;
+ marvell,odmi-frames = <4>;
+ reg = <0x300000 0x4000>,
+ <0x304000 0x4000>,
+ <0x308000 0x4000>,
+ <0x30C000 0x4000>;
+ marvell,spi-base = <128>, <136>, <144>, <152>;
+ };
+
+ gicp: gicp@3f0040 {
+ compatible = "marvell,ap806-gicp";
+ reg = <0x3f0040 0x10>;
+ marvell,spi-ranges = <64 64>, <288 64>;
+ msi-controller;
+ };
+
+ pic: interrupt-controller@3f0100 {
+ compatible = "marvell,armada-8k-pic";
+ reg = <0x3f0100 0x10>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ xor@400000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x400000 0x1000>,
+ <0x410000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@420000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x420000 0x1000>,
+ <0x430000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@440000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x440000 0x1000>,
+ <0x450000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@460000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x460000 0x1000>,
+ <0x470000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ spi0: spi@510600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x510600 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@511000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x511000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-ms = <1000>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ uart0: serial@512000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512000 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ uart1: serial@512100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512100 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+
+ };
+
+ watchdog: watchdog@610000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x610000 0x1000>, <0x600000 0x1000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ ap_sdhci0: sdhci@6e0000 {
+ compatible = "marvell,armada-ap806-sdhci";
+ reg = <0x6e0000 0x300>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core";
+ clocks = <&ap_clk 4>;
+ dma-coherent;
+ marvell,xenon-phy-slow-mode;
+ status = "disabled";
+ };
+
+ ap_syscon: system-controller@6f4000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f4000 0x2000>;
+
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
+
+ ap_pinctrl: pinctrl {
+ compatible = "marvell,ap806-pinctrl";
+
+ uart0_pins: uart0-pins {
+ marvell,pins = "mpp11", "mpp19";
+ marvell,function = "uart0";
+ };
+ };
+
+ ap_gpio: gpio@1040 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x1040>;
+ ngpios = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ap_pinctrl 0 0 20>;
+ };
+ };
+
+ ap_thermal: thermal@6f808c {
+ compatible = "marvell,armada-ap806-thermal";
+ reg = <0x6f808c 0x4>,
+ <0x6f8084 0x8>;
+ };
+ };
+ };
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
new file mode 100644
index 0000000..8b610fd
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ */
+
+/* Common definitions used by Armada 7K/8K DTs */
+#define PASTER(x, y) x ## y
+#define EVALUATOR(x, y) PASTER(x, y)
+#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
+#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
new file mode 100644
index 0000000..b6e5ded
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
@@ -0,0 +1,552 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada CP110.
+ */
+
+#include "armada-common.dtsi"
+
+#define ICU_GRP_NSR 0x0
+#define ICU_GRP_SR 0x1
+#define ICU_GRP_SEI 0x4
+#define ICU_GRP_REI 0x5
+
+#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
+
+/ {
+ /*
+ * The contents of the node are defined below, in order to
+ * save one indentation level
+ */
+ CP110_NAME: CP110_NAME { };
+};
+
+&CP110_NAME {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&CP110_LABEL(icu)>;
+ ranges;
+
+ config-space@CP110_BASE {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
+
+ CP110_LABEL(ethernet): ethernet@0 {
+ compatible = "marvell,armada-7k-pp22";
+ reg = <0x0 0x100000>, <0x129000 0xb000>;
+ clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>,
+ <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(core_clk)>;
+ clock-names = "pp_clk", "gop_clk",
+ "mg_clk", "mg_core_clk", "axi_clk";
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ status = "disabled";
+ dma-coherent;
+
+ CP110_LABEL(eth0): eth0 {
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <0>;
+ gop-port-id = <0>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth1): eth1 {
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <1>;
+ gop-port-id = <2>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth2): eth2 {
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <2>;
+ gop-port-id = <3>;
+ status = "disabled";
+ };
+ };
+
+ CP110_LABEL(comphy): phy@120000 {
+ compatible = "marvell,comphy-cp110";
+ reg = <0x120000 0x6000>;
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CP110_LABEL(comphy0): phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy1): phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy2): phy@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy3): phy@3 {
+ reg = <3>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy4): phy@4 {
+ reg = <4>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy5): phy@5 {
+ reg = <5>;
+ #phy-cells = <1>;
+ };
+ };
+
+ CP110_LABEL(mdio): mdio@12a200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x12a200 0x10>;
+ clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>,
+ <&CP110_LABEL(core_clk)>, <&CP110_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(xmdio): mdio@12a600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,xmdio";
+ reg = <0x12a600 0x10>;
+ clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>,
+ <&CP110_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(icu): interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x440>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+ };
+
+ CP110_LABEL(rtc): rtc@284000 {
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(thermal): thermal@400078 {
+ compatible = "marvell,armada-cp110-thermal";
+ reg = <0x400078 0x4>,
+ <0x400070 0x8>;
+ };
+
+ CP110_LABEL(syscon0): system-controller@440000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x440000 0x2000>;
+
+ CP110_LABEL(clk): clock {
+ compatible = "marvell,cp110-clock";
+ status = "disabled";
+ #clock-cells = <2>;
+ };
+
+ CP110_LABEL(gpio1): gpio@100 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x100>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(gpio2): gpio@140 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x140>;
+ ngpios = <31>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ CP110_LABEL(usb3_0): usb3@500000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x500000 0x4000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(usb3_1): usb3@510000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x510000 0x4000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(sata0): sata@540000 {
+ compatible = "marvell,armada-8k-ahci",
+ "generic-ahci";
+ reg = <0x540000 0x30000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(xor0): xor@6a0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ };
+
+ CP110_LABEL(xor1): xor@6c0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ };
+
+ CP110_LABEL(spi0): spi@700600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700600 0x50>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(spi1): spi@700680 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c0): i2c@701000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c1): i2c@701100 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart0): serial@702000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702000 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart1): serial@702100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702100 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart2): serial@702200 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702200 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart3): serial@702300 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702300 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(nand_controller): nand@720000 {
+ /*
+ * Due to the limitation of the pins available
+ * this controller is only usable on the CPM
+ * for A7K and on the CPS for A8K.
+ */
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
+ reg = <0x720000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(nand_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(trng): trng@760000 {
+ compatible = "marvell,armada-8k-rng",
+ "inside-secure,safexcel-eip76";
+ reg = <0x760000 0x7d>;
+ interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(x2core_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "okay";
+ };
+
+ CP110_LABEL(sdhci0): sdhci@780000 {
+ compatible = "marvell,armada-cp110-sdhci";
+ reg = <0x780000 0x300>;
+ interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL(core_clk)>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ CP110_LABEL(crypto): crypto@800000 {
+ compatible = "inside-secure,safexcel-eip197";
+ reg = <0x800000 0x200000>;
+ interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mem", "ring0", "ring1",
+ "ring2", "ring3", "eip";
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(x2core_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ dma-coherent;
+ };
+ };
+
+ CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ /* 1 GHz fixed main PLL */
+ CP110_LABEL(mainpll): CP110_LABEL(mainpll) {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ CP110_LABEL(core_clk): CP110_LABEL(core_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <2>;
+ clock-div = <5>;
+ };
+
+ CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <2>;
+ clock-div = <5>;
+ };
+
+ CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
new file mode 100644
index 0000000..9e4aa51
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Model: Marvell CN9130 development board (CP NOR) setup(A)";
+ compatible = "marvell,cn9130-db-A", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* on-board eMMC - U9 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ bus-width = <8>;
+ status = "okay";
+ vqmmc-supply = <&ap0_reg_sd_vccq>;
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cp0_i2c1 {
+ status = "okay";
+};
+
+/* CON 28 */
+&cp0_sdhci0 {
+ status = "okay";
+};
+
+/* U54 */
+&cp0_nand_controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins>;
+
+ nand@0 {
+ reg = <0>;
+ label = "main-storage";
+ nand-rb = <0>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@200000 {
+ label = "Linux";
+ reg = <0x200000 0xd00000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+ };
+ };
+};
+
+/* U55 */
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>; /* CS0 */
+ status = "disabled";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+/* SLM-1521-V2, CON6 */
+&cp0_pcie0 {
+ status = "okay";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 0
+ &cp0_comphy1 0
+ &cp0_comphy2 0
+ &cp0_comphy3 0>;
+};
+
+&cp0_sata0 {
+ status = "okay";
+ /* SLM-1521-V2, CON2 */
+};
+
+&cp0_mdio {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp0_sfp_eth0>;
+};
+
+/* CON56 */
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+/* CON57 */
+&cp0_eth2 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi
new file mode 100644
index 0000000..eeb96f6
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+#include "cn9130.dtsi" /* include SoC device tree */
+
+/ {
+ model = "DB-CN-9130";
+ compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy0: cp0_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus0>;
+ };
+
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy1: cp0_usb3_phy1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus1>;
+ };
+
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+
+ ap0_reg_sd_vccq: ap0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "ap0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ cp0_sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_sfpp0_i2c>;
+ los-gpio = <&cp0_moudle_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp0_moudle_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp0_moudle_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_moudle_expander1 8 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+};
+
+/*
+ * CP0
+ */
+&cp0_i2c0 {
+ clock-frequency = <100000>;
+
+ /* U36 */
+ expander0: pca953x@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ status = "okay";
+ };
+
+ /* U42 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U38 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
+};
+
+&cp0_i2c1 {
+ clock-frequency = <100000>;
+
+ /* SLM-1521-V2 - U3 */
+ i2c-mux@72 { /* verify address - depends on dpr */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ cp0_sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* U12 */
+ cp0_moudle_expander1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+
+ };
+ };
+};
+
+
+&cp0_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins>;
+ bus-width = <4>;
+ no-1-8-v;
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
new file mode 100644
index 0000000..97ea923
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/*
+ * Device Tree file for the CN 9130 SoC, made of an AP807 Quad and
+ * three CP110.
+ */
+
+#include "armada-ap806-quad.dtsi"
+
+/ {
+ aliases {
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ };
+};
+
+/* This defines used to calculate the base address of each CP */
+#define CP110_PCIE_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP110_PCIE_BUS_MEM_CFG (0x82000000)
+
+/* CP110-0 Settings */
+#define CP110_NAME cp0
+#define CP110_NUM 0
+#define CP110_BASE f2000000
+#define CP110_PCIE0_BASE f2600000
+#define CP110_PCIE1_BASE f2620000
+#define CP110_PCIE2_BASE f2640000
+#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
+ (0xe0000000 + (iface - 1) * 0x1000000))
+#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NUM
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
+/ {
+ model = "Marvell CN 9130";
+ compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_crypto {
+ status = "okay";
+};
+
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,armada-7k-pinctrl";
+
+ cp0_devbus_pins: cp0-devbus-pins {
+ marvell,pins = "mpp15", "mpp16", "mpp17",
+ "mpp18", "mpp19", "mpp20",
+ "mpp21", "mpp22", "mpp23",
+ "mpp24", "mpp25", "mpp26",
+ "mpp27";
+ marvell,function = "dev";
+ };
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = "mpp0", "mpp1", "mpp2",
+ "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8",
+ "mpp9", "mpp10", "mpp11";
+ marvell,function = "ge0";
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = "mpp44", "mpp45", "mpp46",
+ "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52",
+ "mpp53", "mpp54", "mpp55";
+ marvell,function = "ge1";
+ };
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ nand_pins: nand-pins {
+ marvell,pins =
+ "mpp15", "mpp16", "mpp17", "mpp18", "mpp19",
+ "mpp20", "mpp21", "mpp22", "mpp23", "mpp24",
+ "mpp25", "mpp26", "mpp27";
+ marvell,function = "dev";
+ };
+ nand_rb: nand-rb {
+ marvell,pins = "mpp13";
+ marvell,function = "nf";
+ };
+ };
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
new file mode 100644
index 0000000..f08a748
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include "cn9130-db-A.dts"
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell CN9131 development board (CP NOR) setup(A)";
+ compatible = "marvell,cn9131-db-A", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* CON50 */
+&cp1_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp1_sfp_eth1>;
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
new file mode 100644
index 0000000..c8e425a
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NUM 1
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+ model = "Marvell CN9131 development board";
+ compatible = "marvell,cn9131-db", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+
+ aliases {
+ gpio3 = &cp1_gpio1;
+ gpio4 = &cp1_gpio2;
+ ethernet3 = &cp1_eth0;
+ ethernet4 = &cp1_eth1;
+ };
+
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp1_usb3_0_phy0: cp1_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp1_reg_usb3_vbus0>;
+ };
+
+ cp1_sfp_eth1: sfp-eth1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp1_i2c0>;
+ los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_sfp_pins>;
+ status = "disabled";
+ };
+};
+
+&cp1_crypto {
+ status = "okay";
+};
+
+&cp1_gpio1 {
+ status = "okay";
+};
+
+&cp1_gpio2 {
+ status = "okay";
+};
+
+&cp1_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+/* CON40 */
+&cp1_pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_pcie_reset_pins>;
+ num-lanes = <2>;
+ num-viewport = <8>;
+ marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy0 0
+ &cp1_comphy1 0>;
+};
+
+&cp1_sata0 {
+ status = "okay";
+ /* CON32 */
+ sata-port@1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy5 1>;
+ };
+};
+
+/* U24 */
+&cp1_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_spi0_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>; /* CS0 */
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+
+};
+
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp1_i2c0_pins: cp1-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp1_spi0_pins: cp1-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
+ marvell,pins = "mpp3";
+ marvell,function = "gpio";
+ };
+ cp1_sfp_pins: sfp-pins {
+ marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
+ marvell,function = "gpio";
+ };
+ cp1_pcie_reset_pins: cp1-pcie-reset-pins {
+ marvell,pins = "mpp0";
+ marvell,function = "gpio";
+ };
+ };
+};
+
+/* CON58 */
+&cp1_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp1_usb3_0_phy0>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy3 1>;
+ phy-names = "usb";
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
new file mode 100644
index 0000000..e9464f8
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
@@ -0,0 +1,76 @@
+/*
+ * copyright (c) 2019 marvell international ltd.
+ *
+ * spdx-license-identifier: gpl-2.0
+ * https://spdx.org/licenses
+ */
+
+#include "cn9131-db-A.dts"
+#include "cn9132-db.dtsi"
+
+/ {
+ model = "Model: Marvell CN9132 development board (CP NOR) setup(A)";
+ compatible = "marvell,cn9132-db-A", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+
+ aliases {
+ gpio5 = &cp2_gpio1;
+ gpio6 = &cp2_gpio2;
+ ethernet5 = &cp2_eth0;
+ };
+};
+
+&cp2_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp2_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp2_sfp_eth0>;
+};
+
+/* SLM-1521-V2, CON6 */
+&cp2_pcie0 {
+ status = "okay";
+ num-lanes = <2>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy0 0
+ &cp2_comphy1 0>;
+};
+
+/* SLM-1521-V2, CON8 */
+&cp2_pcie2 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy5 2>;
+};
+
+&cp2_sata0 {
+ status = "okay";
+ /* SLM-1521-V2, CON4 */
+ sata-port@0 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy2 0>;
+ };
+};
+
+/* CON 2 on SLM-1683 - microSD */
+&cp2_sdhci0 {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON11 */
+&cp2_usb3_1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy3 1>;
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
new file mode 100644
index 0000000..8613607
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
@@ -0,0 +1,151 @@
+/*
+ * copyright (c) 2019 marvell international ltd.
+ *
+ * spdx-license-identifier: gpl-2.0
+ * https://spdx.org/licenses
+ */
+
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NUM 2
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+ model = "DB-CN-9132";
+ compatible = "marvell,cn9132", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+
+ cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_usb3_0_phy0: cp2_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus0>;
+ };
+
+ cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_usb3_0_phy1: cp2_usb3_phy1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus1>;
+ };
+
+ cp2_reg_sd_vccq: cp2_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp2_sd_vcc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1 3300000 0x0>;
+ };
+
+ cp2_sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp2_sfpp0_i2c>;
+ los-gpio = <&cp2_moudle_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp2_moudle_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp2_moudle_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp2_moudle_expander1 8 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+};
+
+&cp2_crypto {
+ status = "okay";
+};
+
+&cp2_gpio1 {
+ status = "okay";
+};
+
+&cp2_gpio2 {
+ status = "okay";
+};
+
+&cp2_i2c0 {
+ clock-frequency = <100000>;
+
+ /* SLM-1521-V2 - U3 */
+ i2c-mux@72 {
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ cp2_sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* U12 */
+ cp2_moudle_expander1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+ };
+ };
+};
+
+&cp2_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_sdhci_pins>;
+ bus-width = <4>;
+ cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
+ vqmmc-supply = <&cp2_reg_sd_vccq>;
+};
+
+&cp2_syscon0 {
+ cp2_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp2_i2c0_pins: cp2-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp2_sdhci_pins: cp2-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ };
+};
+
+&cp2_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp2_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+&cp2_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp2_usb3_0_phy1>;
+ phy-names = "usb";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms: PATCH 3/9] Marvell/Cn9130Db: Introduce board support
2019-08-07 23:30 [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 1/9] Marvell/Cn9130Db: Add ACPI tables Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 2/9] Marvell/Cn9130Db: Add DeviceTree Marcin Wojtas
@ 2019-08-07 23:30 ` Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 4/9] Marvell/Library: ArmadaSoCDescLib: Extend Xenon information Marcin Wojtas
` (6 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-07 23:30 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
This patch introduces all necessary components required
for building EDK2 firmware for CN9130-DB setup A.
Because the board is modular and can be extended to support
also CN9131 and CN9132 SoC variants, extract common part into
.dsc.inc file, which will be included by them.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 107 +++++++++++++++
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc | 46 +++++++
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf | 29 ++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 37 +++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 19 +++
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c | 126 +++++++++++++++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 144 ++++++++++++++++++++
Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc | 17 +++
8 files changed, 525 insertions(+)
create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc
create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc
diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
new file mode 100644
index 0000000..33fb7cc
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -0,0 +1,107 @@
+## @file
+# Component description file for the CN9130 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # CP115 count
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|1
+
+ # MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|2
+
+ # APN807 MPP
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+
+ # CP115 #0 MPP
+ gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0x9 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # I2C
+ gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 }
+ gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
+ gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
+ gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+
+ # SPI
+ gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
+ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+
+ # ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+ # ComPhy0
+ # 0: PCIE0 5 Gbps
+ # 1: PCIE0 5 Gbps
+ # 2: PCIE0 5 Gbps
+ # 3: PCIE0 5 Gbps
+ # 4: SFI 10.31 Gbps
+ # 5: SATA1 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+
+ # UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ # MDIO
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+
+ # PHY
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+ # NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+
+ # PCIE
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000
+
+ # RTC
+ gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
+
+ # SoC Configuration Space
+ gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000
+
+ # Variable store
+ gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE
diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc
new file mode 100644
index 0000000..2380ec3
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc
@@ -0,0 +1,46 @@
+## @file
+# Component description file for the CN9130 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = Cn9130DbA
+ PLATFORM_GUID = 087305a1-8ddd-4027-89ca-68a3ef78fcc7
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001000B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc
+
+ #
+ # Network definition
+ #
+ DEFINE NETWORK_IP6_ENABLE = FALSE
+ DEFINE NETWORK_TLS_ENABLE = FALSE
+ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
+ DEFINE NETWORK_ISCSI_ENABLE = FALSE
+
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+
+[Components.common]
+ Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
+
+[Components.AARCH64]
+ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
+
+[LibraryClasses.common]
+ ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
+ NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
new file mode 100644
index 0000000..dfbdc84
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
@@ -0,0 +1,29 @@
+## @file
+#
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9130DbABoardDescLib
+ FILE_GUID = d0f95cbe-c150-47e2-ab8c-b3a3807bcc4b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmadaBoardDescLib
+
+[Sources]
+ Cn9130DbABoardDescLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
new file mode 100644
index 0000000..f7cfb36
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
@@ -0,0 +1,37 @@
+## @file
+#
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9130DbANonDiscoverableInitLib
+ FILE_GUID = 93886b61-b4f5-4ff3-ba96-6f2f9e7661b9
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NonDiscoverableInitLib
+
+[Sources]
+ NonDiscoverableInitLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ MvGpioLib
+
+[Protocols]
+ gEmbeddedGpioProtocolGuid
+
+[Depex]
+ gMarvellPlatformInitCompleteProtocolGuid
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
new file mode 100644
index 0000000..2533c35
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
@@ -0,0 +1,19 @@
+/**
+*
+* Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#ifndef __NON_DISCOVERABLE_INIT_LIB_H__
+#define __NON_DISCOVERABLE_INIT_LIB_H__
+
+#define CN9130_DB_IO_EXPANDER0 0
+#define CN9130_DB_VBUS0_PIN 0
+#define CN9130_DB_VBUS0_LIMIT_PIN 4
+#define CN9130_DB_VBUS1_PIN 1
+#define CN9130_DB_VBUS1_LIMIT_PIN 5
+#define CN9130_DB_SDMMC_VCC_PIN 14
+#define CN9130_DB_SDMMC_VCCQ_PIN 15
+
+#endif
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
new file mode 100644
index 0000000..2b46d14
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
@@ -0,0 +1,126 @@
+/**
+*
+* Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/ArmadaBoardDescLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/MvGpioLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+//
+// GPIO Expander
+//
+STATIC MV_GPIO_EXPANDER mGpioExpander = {
+ PCA9555_ID,
+ 0x21,
+ 0x0,
+};
+
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardGpioExpanderGet (
+ IN OUT MV_GPIO_EXPANDER **GpioExpanders,
+ IN OUT UINTN *GpioExpanderCount
+ )
+{
+ *GpioExpanderCount = 1;
+ *GpioExpanders = &mGpioExpander;
+
+ return EFI_SUCCESS;
+}
+
+//
+// PCIE
+//
+STATIC
+MV_PCIE_CONTROLLER mPcieController[] = {
+ { /* PCIE0 @0xF2640000 */
+ .PcieDbiAddress = 0xF2600000,
+ .ConfigSpaceAddress = 0xD0000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xFE,
+ .PcieIoTranslation = 0xDFF00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xC0000000,
+ .PcieMmio32WinSize = 0x10000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = MAX_UINT64,
+ .PcieMmio64WinSize = 0,
+ }
+};
+
+/**
+ Return the number and description of PCIE controllers used on the platform.
+
+ @param[in out] **PcieControllers Array containing PCIE controllers'
+ description.
+ @param[in out] *PcieControllerCount Amount of used PCIE controllers.
+
+ @retval EFI_SUCCESS The data were obtained successfully.
+ @retval other Return error status.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaBoardPcieControllerGet (
+ IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,
+ IN OUT UINTN *PcieControllerCount
+ )
+{
+ *PcieControllers = mPcieController;
+ *PcieControllerCount = ARRAY_SIZE (mPcieController);
+
+ return EFI_SUCCESS;
+}
+
+//
+// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib
+//
+STATIC
+MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = {
+ { /* eMMC 0xF06E0000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ TRUE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x40, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ },
+ { /* SD/MMC 0xF2780000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ FALSE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x19, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ }
+};
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardDescSdMmcGet (
+ OUT UINTN *SdMmcDevCount,
+ OUT MV_BOARD_SDMMC_DESC **SdMmcDesc
+ )
+{
+ *SdMmcDesc = mSdMmcDescTemplate;
+ *SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
new file mode 100644
index 0000000..598c649
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
@@ -0,0 +1,144 @@
+/**
+*
+* Copyright (c) 2017, Linaro Ltd. All rights reserved.
+* Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/MvGpioLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/NonDiscoverableDevice.h>
+
+#include "NonDiscoverableInitLib.h"
+
+STATIC
+EFI_STATUS
+EFIAPI
+ConfigurePins (
+ IN CONST MV_GPIO_PIN *VbusPin,
+ IN UINTN PinCount,
+ IN MV_GPIO_DRIVER_TYPE DriverType
+ )
+{
+ EMBEDDED_GPIO_MODE Mode;
+ EMBEDDED_GPIO_PIN Gpio;
+ EMBEDDED_GPIO *GpioProtocol;
+ EFI_STATUS Status;
+ UINTN Index;
+
+ Status = MvGpioGetProtocol (DriverType, &GpioProtocol);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION__));
+ return Status;
+ }
+
+ for (Index = 0; Index < PinCount; Index++) {
+ Mode = VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0;
+ Gpio = GPIO (VbusPin->ControllerId, VbusPin->PinNumber);
+ GpioProtocol->Set (GpioProtocol, Gpio, Mode);
+ VbusPin++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC CONST MV_GPIO_PIN mCp0XhciVbusPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_VBUS0_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_VBUS0_LIMIT_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_VBUS1_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_VBUS1_LIMIT_PIN,
+ TRUE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+Cp0XhciInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mCp0XhciVbusPins,
+ ARRAY_SIZE (mCp0XhciVbusPins),
+ MV_GPIO_DRIVER_TYPE_PCA95XX);
+}
+
+STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_SDMMC_VCC_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_SDMMC_VCCQ_PIN,
+ FALSE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+Cp0SdMmcInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mCp0SdMmcPins,
+ ARRAY_SIZE (mCp0SdMmcPins),
+ MV_GPIO_DRIVER_TYPE_PCA95XX);
+}
+
+NON_DISCOVERABLE_DEVICE_INIT
+EFIAPI
+NonDiscoverableDeviceInitializerGet (
+ IN NON_DISCOVERABLE_DEVICE_TYPE Type,
+ IN UINTN Index
+ )
+{
+ if (Type == NonDiscoverableDeviceTypeXhci) {
+ switch (Index) {
+ case 0:
+ case 1:
+ return Cp0XhciInit;
+ }
+ }
+
+ if (Type == NonDiscoverableDeviceTypeSdhci) {
+ switch (Index) {
+ case 1:
+ return Cp0SdMmcInit;
+ }
+ }
+
+ return NULL;
+}
diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc
new file mode 100644
index 0000000..4beeb3f
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc
@@ -0,0 +1,17 @@
+#
+# Copyright (C) 2019 Marvell International Ltd. and its affiliates
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+# Per-board additional content of the DXE phase firmware volume
+
+ INF Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf
+
+ # DTB
+ INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
+
+!if $(ARCH) == AARCH64
+ # ACPI support
+ INF RuleOverride = ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
+!endif
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms: PATCH 4/9] Marvell/Library: ArmadaSoCDescLib: Extend Xenon information
2019-08-07 23:30 [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (2 preceding siblings ...)
2019-08-07 23:30 ` [edk2-platforms: PATCH 3/9] Marvell/Cn9130Db: Introduce board support Marcin Wojtas
@ 2019-08-07 23:30 ` Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 5/9] Marvell/Library: MppLib: Allow to configure more Xenon PHYs Marcin Wojtas
` (5 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-07 23:30 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
Hitherto SoC description library code assumed that there could
be only two Xenon SdMmc controller instances in the SoC. Remove this
limitation, so that to support CN913x SoCs, which may have up to 4 of
such interfaces.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 5 +--
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 34 +++++++++++++-------
2 files changed, 25 insertions(+), 14 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
index 0296d43..265b4f4 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
@@ -90,8 +90,9 @@
//
// Platform description of SDMMC controllers
//
-#define MV_SOC_MAX_SDMMC_COUNT 2
-#define MV_SOC_SDMMC_BASE(Index) ((Index) == 0 ? 0xF06E0000 : 0xF2780000)
+#define MV_SOC_SDMMC_PER_CP_COUNT 1
+#define MV_SOC_AP80X_SDMMC_BASE 0xF06E0000
+#define MV_SOC_CP_SDMMC_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x780000)
//
// Platform description of UTMI PHY's
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
index 5947601..3ffd57e 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
@@ -349,26 +349,36 @@ EFI_STATUS
EFIAPI
ArmadaSoCDescSdMmcGet (
IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc,
- IN OUT UINTN *DescCount
+ IN OUT UINTN *Count
)
{
- MV_SOC_SDMMC_DESC *Desc;
- UINTN Index;
+ MV_SOC_SDMMC_DESC *SdMmc;
+ UINTN CpCount, CpIndex;
- Desc = AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC_DESC));
- if (Desc == NULL) {
+ CpCount = FixedPcdGet8 (PcdMaxCpCount);
+
+ *Count = CpCount * MV_SOC_SDMMC_PER_CP_COUNT + MV_SOC_AP806_COUNT;
+ SdMmc = AllocateZeroPool (*Count * sizeof (MV_SOC_SDMMC_DESC));
+ if (SdMmc == NULL) {
DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
return EFI_OUT_OF_RESOURCES;
}
- for (Index = 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) {
- Desc[Index].SdMmcBaseAddress = MV_SOC_SDMMC_BASE (Index);
- Desc[Index].SdMmcMemSize = SIZE_1KB;
- Desc[Index].SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent;
- }
+ *SdMmcDesc = SdMmc;
+
+ /* AP80x controller */
+ SdMmc->SdMmcBaseAddress = MV_SOC_AP80X_SDMMC_BASE;
+ SdMmc->SdMmcMemSize = SIZE_1KB;
+ SdMmc->SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent;
+ SdMmc++;
- *SdMmcDesc = Desc;
- *DescCount = MV_SOC_MAX_SDMMC_COUNT;
+ /* CP11x controllers */
+ for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
+ SdMmc->SdMmcBaseAddress = MV_SOC_CP_SDMMC_BASE (CpIndex);
+ SdMmc->SdMmcMemSize = SIZE_1KB;
+ SdMmc->SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent;
+ SdMmc++;
+ }
return EFI_SUCCESS;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms: PATCH 5/9] Marvell/Library: MppLib: Allow to configure more Xenon PHYs
2019-08-07 23:30 [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (3 preceding siblings ...)
2019-08-07 23:30 ` [edk2-platforms: PATCH 4/9] Marvell/Library: ArmadaSoCDescLib: Extend Xenon information Marcin Wojtas
@ 2019-08-07 23:30 ` Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 6/9] Marvell/Library: IcuLib: Fix debug information Marcin Wojtas
` (4 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-07 23:30 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
Hitherto MppLib code assumed that there could be only two
Xenon SdMmc controllers' PHYs. Remove this limitation, so that to
support CN913x SoCs, which may have up to 4 of such interfaces.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Library/MppLib/MppLib.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/Silicon/Marvell/Library/MppLib/MppLib.c b/Silicon/Marvell/Library/MppLib/MppLib.c
index 40d9077..f20668d 100644
--- a/Silicon/Marvell/Library/MppLib/MppLib.c
+++ b/Silicon/Marvell/Library/MppLib/MppLib.c
@@ -139,11 +139,9 @@ SetSdMmcPhyMpp (
case 0:
Offset = SD_MMC_PHY_AP_MPP_OFFSET;
break;
- case 1:
+ default:
Offset = SD_MMC_PHY_CP0_MPP_OFFSET;
break;
- default:
- return;
}
/*
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms: PATCH 6/9] Marvell/Library: IcuLib: Fix debug information
2019-08-07 23:30 [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (4 preceding siblings ...)
2019-08-07 23:30 ` [edk2-platforms: PATCH 5/9] Marvell/Library: MppLib: Allow to configure more Xenon PHYs Marcin Wojtas
@ 2019-08-07 23:30 ` Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 7/9] Marvell/Cn9131Db: Introduce board support Marcin Wojtas
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-07 23:30 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
In case the number of CP11x components exceeded the maximum
of currently supported, the user is informed with the information.
It turned out that the print arguments were incorrect - fix it.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Library/IcuLib/IcuLib.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Library/IcuLib/IcuLib.c
index 343c21b..4d9f174 100644
--- a/Silicon/Marvell/Library/IcuLib/IcuLib.c
+++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c
@@ -280,8 +280,8 @@ ArmadaIcuInitialize (
if (CpCount > ICU_MAX_SUPPORTED_UNITS) {
DEBUG ((DEBUG_ERROR,
"%a: Default ICU to GIC mapping is available for maximum %d CP110 units",
- ICU_MAX_SUPPORTED_UNITS,
- __FUNCTION__));
+ __FUNCTION__,
+ ICU_MAX_SUPPORTED_UNITS));
CpCount = ICU_MAX_SUPPORTED_UNITS;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms: PATCH 7/9] Marvell/Cn9131Db: Introduce board support
2019-08-07 23:30 [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (5 preceding siblings ...)
2019-08-07 23:30 ` [edk2-platforms: PATCH 6/9] Marvell/Library: IcuLib: Fix debug information Marcin Wojtas
@ 2019-08-07 23:30 ` Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 8/9] Marvell/Cn9132Db: " Marcin Wojtas
` (2 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-07 23:30 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
This patch introduces all necessary components required
for building EDK2 firmware for CN9131-DB setup A.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc | 72 ++++++++++++++
Platform/Marvell/Cn913xDb/Cn9131DbA.dsc | 47 ++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 57 ++++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf | 22 +++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 2 +
| 2 +
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 29 ++++++
Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc | 18 ++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 98 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi | 26 +++---
10 files changed, 361 insertions(+), 12 deletions(-)
create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
new file mode 100644
index 0000000..7235b9f
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
@@ -0,0 +1,72 @@
+## @file
+# Component description file for the CN9131 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # CP115 count
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|2
+
+ # MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|3
+
+ # CP115 #1 MPP
+ gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7, 0x2, 0x2, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ # ComPhy1
+ # 0: PCIE0 5 Gbps
+ # 1: PCIE0 5 Gbps
+ # 2: UNCONNECTED
+ # 3: USB3_HOST1 5 Gbps
+ # 4: SFI 10.31 Gbps
+ # 5: SATA1 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)}
+ gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_DEFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+
+ # UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ # MDIO
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+
+ # PHY
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+ # NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc
new file mode 100644
index 0000000..8f926cf
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc
@@ -0,0 +1,47 @@
+## @file
+# Component description file for the CN9131 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = Cn9131DbA
+ PLATFORM_GUID = 9fcb32d0-ea4e-4e9c-863d-06d90b160855
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001000B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc
+
+ #
+ # Network definition
+ #
+ DEFINE NETWORK_IP6_ENABLE = FALSE
+ DEFINE NETWORK_TLS_ENABLE = FALSE
+ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
+ DEFINE NETWORK_ISCSI_ENABLE = FALSE
+
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+!include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
+
+[Components.common]
+ Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
+
+[Components.AARCH64]
+ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
+
+[LibraryClasses.common]
+ ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
+ NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
new file mode 100644
index 0000000..bbf1b51
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
@@ -0,0 +1,57 @@
+## @file
+# Component description file for PlatformAcpiTables module.
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+# Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Cn9131DbA/Ssdt.asl
+ Cn913xDbA/Dsdt.asl
+ Cn913xDbA/Mcfg.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Pptt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+[BuildOptions]
+ *_*_*_ASLCC_FLAGS = -DCN9131
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
new file mode 100644
index 0000000..8108197
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
@@ -0,0 +1,22 @@
+## @file
+#
+# Device tree description of the Marvell CN9130-DB-A platform
+#
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9131DbADeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ cn9131-db-A.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
index 2533c35..6618737 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
@@ -15,5 +15,7 @@
#define CN9130_DB_VBUS1_LIMIT_PIN 5
#define CN9130_DB_SDMMC_VCC_PIN 14
#define CN9130_DB_SDMMC_VCCQ_PIN 15
+#define CN9131_DB_VBUS0_PIN 3
+#define CN9131_DB_VBUS0_LIMIT_PIN 2
#endif
--git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
index b5fd397..2838676 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
@@ -18,6 +18,8 @@
#if defined(CN9130)
#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ',' ')
+#elif defined (CN9131)
+#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','1',' ',' ')
#endif
/**
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
index 598c649..dded150 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
@@ -91,6 +91,33 @@ Cp0XhciInit (
MV_GPIO_DRIVER_TYPE_PCA95XX);
}
+STATIC CONST MV_GPIO_PIN mCp1XhciVbusPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP1_CONTROLLER0,
+ CN9131_DB_VBUS0_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP1_CONTROLLER0,
+ CN9131_DB_VBUS0_LIMIT_PIN,
+ TRUE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+Cp1XhciInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mCp1XhciVbusPins,
+ ARRAY_SIZE (mCp1XhciVbusPins),
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
+}
+
STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = {
{
MV_GPIO_DRIVER_TYPE_PCA95XX,
@@ -130,6 +157,8 @@ NonDiscoverableDeviceInitializerGet (
case 0:
case 1:
return Cp0XhciInit;
+ case 2:
+ return Cp1XhciInit;
}
}
diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc b/Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc
new file mode 100644
index 0000000..8ae449d
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc
@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2019 Marvell International Ltd. and its affiliates
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+# Per-board additional content of the DXE phase firmware volume
+
+ INF Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf
+ INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf
+
+ # DTB
+ INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
+
+!if $(ARCH) == AARCH64
+ # ACPI support
+ INF RuleOverride = ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
+!endif
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
new file mode 100644
index 0000000..59145b5
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
@@ -0,0 +1,98 @@
+/** @file
+
+ Secondary System Description Table Fields (SSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "IcuInterrupts.h"
+
+DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131DBA", 3)
+{
+ Scope (_SB)
+ {
+ Device (AHC1)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF4540000, // Address Base (MMIO)
+ 0x00030000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP1_SATA_H0
+ }
+ })
+ }
+
+ Device (XHC2)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF4510000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP1_USB_H1
+ }
+ })
+ }
+ Device (PP21)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP1_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "10gbase-kr"},
+ }
+ })
+ }
+ }
+ }
+}
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
index c8e425a..9c9dfb6 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
@@ -6,15 +6,23 @@
*/
#undef CP110_NUM
-#undef CP110_PCIE_MEM_SIZE
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
#undef CP110_PCIEx_CPU_MEM_BASE
-#undef CP110_PCIEx_BUS_MEM_BASE
+#undef CP110_PCIEx_MEM_BASE
/* CP110-1 Settings */
+#define CP110_NAME cp1
#define CP110_NUM 1
-#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
-#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
-#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+#define CP110_BASE f4000000
+#define CP110_PCIE0_BASE f4600000
+#define CP110_PCIE1_BASE f4620000
+#define CP110_PCIE2_BASE f4640000
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
#include "armada-cp110.dtsi"
@@ -93,12 +101,6 @@
&cp1_sata0 {
status = "okay";
- /* CON32 */
- sata-port@1 {
- status = "okay";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy5 1>;
- };
};
/* U24 */
@@ -138,7 +140,7 @@
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
+ compatible = "marvell,armada-7k-pinctrl";
cp1_i2c0_pins: cp1-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms: PATCH 8/9] Marvell/Cn9132Db: Introduce board support
2019-08-07 23:30 [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (6 preceding siblings ...)
2019-08-07 23:30 ` [edk2-platforms: PATCH 7/9] Marvell/Cn9131Db: Introduce board support Marcin Wojtas
@ 2019-08-07 23:30 ` Marcin Wojtas
2019-08-07 23:30 ` [edk2-platforms: PATCH 9/9] Marvell/Drivers: SmbiosPlatformDxe: Use more generic board name Marcin Wojtas
2019-08-08 11:51 ` [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Leif Lindholm
9 siblings, 0 replies; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-07 23:30 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
This patch introduces all necessary components required
for building EDK2 firmware for CN9132-DB setup A.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 72 +++++++++++
Platform/Marvell/Cn913xDb/Cn9132DbA.dsc | 45 +++++++
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf | 29 +++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf | 22 ++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 4 +
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | 135 ++++++++++++++++++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 42 ++++++
Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc | 13 ++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 6 -
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 20 ++-
10 files changed, 376 insertions(+), 12 deletions(-)
create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc
create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc
diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
new file mode 100644
index 0000000..a0b90fa
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
@@ -0,0 +1,72 @@
+## @file
+# Component description file for the CN9132 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # CP115 count
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|3
+
+ # MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|4
+
+ # CP115 #2 MPP
+ gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
+ gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x9, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0x0, 0x2, 0x2, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0xE, 0xE, 0xE, 0xE }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
+ # ComPhy1
+ # 0: PCIE0 5 Gbps
+ # 1: PCIE0 5 Gbps
+ # 2: SATA0 5 Gbps
+ # 3: USB3_HOST1 5 Gbps
+ # 4: SFI 10.31 Gbps
+ # 5: PCIE2 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)}
+ gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+
+ # UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ # MDIO
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+
+ # PHY
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+ # NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 }
diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc
new file mode 100644
index 0000000..12052ba
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc
@@ -0,0 +1,45 @@
+## @file
+# Component description file for the CN9132 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = Cn9132DbA
+ PLATFORM_GUID = b9d2c816-296f-460f-a190-fe9afdd208c7
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001000B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc
+
+ #
+ # Network definition
+ #
+ DEFINE NETWORK_IP6_ENABLE = FALSE
+ DEFINE NETWORK_TLS_ENABLE = FALSE
+ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
+ DEFINE NETWORK_ISCSI_ENABLE = FALSE
+
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+!include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
+!include Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
+
+[Components.common]
+ Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
+
+[LibraryClasses.common]
+ ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
+ NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
new file mode 100644
index 0000000..27a0214
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
@@ -0,0 +1,29 @@
+## @file
+#
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9132DbABoardDescLib
+ FILE_GUID = cf7a0f12-45fe-417b-9c34-053605973b68
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmadaBoardDescLib
+
+[Sources]
+ Cn9132DbABoardDescLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
new file mode 100644
index 0000000..c9e3b04
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
@@ -0,0 +1,22 @@
+## @file
+#
+# Device tree description of the Marvell CN9130-DB-A platform
+#
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9132DbADeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ cn9132-db-A.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
index 6618737..084bea0 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
@@ -17,5 +17,9 @@
#define CN9130_DB_SDMMC_VCCQ_PIN 15
#define CN9131_DB_VBUS0_PIN 3
#define CN9131_DB_VBUS0_LIMIT_PIN 2
+#define CN9132_DB_VBUS0_PIN 2
+#define CN9132_DB_VBUS0_LIMIT_PIN 0
+#define CN9132_DB_VBUS1_PIN 3
+#define CN9132_DB_VBUS1_LIMIT_PIN 1
#endif
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
new file mode 100644
index 0000000..d2846dd
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
@@ -0,0 +1,135 @@
+/**
+*
+* Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/ArmadaBoardDescLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/MvGpioLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+//
+// GPIO Expander
+//
+STATIC MV_GPIO_EXPANDER mGpioExpander = {
+ PCA9555_ID,
+ 0x21,
+ 0x0,
+};
+
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardGpioExpanderGet (
+ IN OUT MV_GPIO_EXPANDER **GpioExpanders,
+ IN OUT UINTN *GpioExpanderCount
+ )
+{
+ *GpioExpanderCount = 1;
+ *GpioExpanders = &mGpioExpander;
+
+ return EFI_SUCCESS;
+}
+
+//
+// PCIE
+//
+STATIC
+MV_PCIE_CONTROLLER mPcieController[] = {
+ { /* PCIE0 @0xF2640000 */
+ .PcieDbiAddress = 0xF2600000,
+ .ConfigSpaceAddress = 0xD0000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xFE,
+ .PcieIoTranslation = 0xDFF00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xC0000000,
+ .PcieMmio32WinSize = 0x10000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = MAX_UINT64,
+ .PcieMmio64WinSize = 0,
+ }
+};
+
+/**
+ Return the number and description of PCIE controllers used on the platform.
+
+ @param[in out] **PcieControllers Array containing PCIE controllers'
+ description.
+ @param[in out] *PcieControllerCount Amount of used PCIE controllers.
+
+ @retval EFI_SUCCESS The data were obtained successfully.
+ @retval other Return error status.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaBoardPcieControllerGet (
+ IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,
+ IN OUT UINTN *PcieControllerCount
+ )
+{
+ *PcieControllers = mPcieController;
+ *PcieControllerCount = ARRAY_SIZE (mPcieController);
+
+ return EFI_SUCCESS;
+}
+
+//
+// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib
+//
+STATIC
+MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = {
+ { /* eMMC 0xF06E0000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ TRUE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x40, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ },
+ { /* SD/MMC 0xF2780000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ FALSE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x19, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ },
+ { /* SD/MMC 0xF6780000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ FALSE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x19, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ }
+};
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardDescSdMmcGet (
+ OUT UINTN *SdMmcDevCount,
+ OUT MV_BOARD_SDMMC_DESC **SdMmcDesc
+ )
+{
+ *SdMmcDesc = mSdMmcDescTemplate;
+ *SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
index dded150..42dc54a 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
@@ -118,6 +118,45 @@ Cp1XhciInit (
MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
}
+STATIC CONST MV_GPIO_PIN mCp2XhciVbusPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS0_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS0_LIMIT_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS1_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS1_LIMIT_PIN,
+ TRUE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+Cp2XhciInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mCp2XhciVbusPins,
+ ARRAY_SIZE (mCp2XhciVbusPins),
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
+}
+
STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = {
{
MV_GPIO_DRIVER_TYPE_PCA95XX,
@@ -159,6 +198,9 @@ NonDiscoverableDeviceInitializerGet (
return Cp0XhciInit;
case 2:
return Cp1XhciInit;
+ case 3:
+ case 4:
+ return Cp2XhciInit;
}
}
diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc b/Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc
new file mode 100644
index 0000000..2a5bc38
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2019 Marvell International Ltd. and its affiliates
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+# Per-board additional content of the DXE phase firmware volume
+
+ INF Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf
+ INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf
+
+ # DTB
+ INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
index e9464f8..724d7dc 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
@@ -55,12 +55,6 @@
&cp2_sata0 {
status = "okay";
- /* SLM-1521-V2, CON4 */
- sata-port@0 {
- status = "okay";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp2_comphy2 0>;
- };
};
/* CON 2 on SLM-1683 - microSD */
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
index 8613607..7dc6c6e 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
@@ -6,15 +6,23 @@
*/
#undef CP110_NUM
-#undef CP110_PCIE_MEM_SIZE
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
#undef CP110_PCIEx_CPU_MEM_BASE
-#undef CP110_PCIEx_BUS_MEM_BASE
+#undef CP110_PCIEx_MEM_BASE
/* CP110-1 Settings */
+#define CP110_NAME cp2
#define CP110_NUM 2
-#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
-#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
-#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+#define CP110_BASE f6000000
+#define CP110_PCIE0_BASE f6600000
+#define CP110_PCIE1_BASE f6620000
+#define CP110_PCIE2_BASE f6640000
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
#include "armada-cp110.dtsi"
@@ -124,7 +132,7 @@
&cp2_syscon0 {
cp2_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
+ compatible = "marvell,armada-7k-pinctrl";
cp2_i2c0_pins: cp2-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms: PATCH 9/9] Marvell/Drivers: SmbiosPlatformDxe: Use more generic board name
2019-08-07 23:30 [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (7 preceding siblings ...)
2019-08-07 23:30 ` [edk2-platforms: PATCH 8/9] Marvell/Cn9132Db: " Marcin Wojtas
@ 2019-08-07 23:30 ` Marcin Wojtas
2019-08-08 11:51 ` [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Leif Lindholm
9 siblings, 0 replies; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-07 23:30 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
SmbiosPlatformDxe is used both by Armada 7k8k and CN913x platforms.
Replace board name placeholder in order to avoid confusion.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
index 08f4fa7..cdacd90 100644
--- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
+++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
@@ -102,7 +102,7 @@ STATIC SMBIOS_TABLE_TYPE1 mArmadaDefaultType1 = {
STATIC CHAR8 CONST *mArmadaDefaultType1Strings[] = {
"Marvell \0",/* Manufacturer */
- "Armada 7k/8k Family Board \0",/* Product Name placeholder*/
+ "Marvell Development Board \0",/* Product Name placeholder*/
"Revision unknown \0",/* Version placeholder */
" \0",/* 32 character buffer */
NULL
@@ -130,7 +130,7 @@ STATIC SMBIOS_TABLE_TYPE2 mArmadaDefaultType2 = {
STATIC CHAR8 CONST *mArmadaDefaultType2Strings[] = {
"Marvell \0",/* Manufacturer */
- "Armada 7k/8k Family Board \0",/* Product Name placeholder*/
+ "Marvell Development Board \0",/* Product Name placeholder*/
"Revision unknown \0",/* Version placeholder */
"Serial Not Set \0",/* Serial */
"Base of Chassis \0",/* Board location */
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support
2019-08-07 23:30 [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (8 preceding siblings ...)
2019-08-07 23:30 ` [edk2-platforms: PATCH 9/9] Marvell/Drivers: SmbiosPlatformDxe: Use more generic board name Marcin Wojtas
@ 2019-08-08 11:51 ` Leif Lindholm
2019-08-08 13:51 ` Marcin Wojtas
9 siblings, 1 reply; 16+ messages in thread
From: Leif Lindholm @ 2019-08-08 11:51 UTC (permalink / raw)
To: Marcin Wojtas; +Cc: devel, ard.biesheuvel, jsd, jaz, kostap
Hi Marcin,
On Thu, Aug 08, 2019 at 01:30:21AM +0200, Marcin Wojtas wrote:
> Hi,
>
> Marvell Octeon CN913X SoC is a new device, which is built of
> upgraded hardware blocks known from previously supported line
> of SoCs. It is avaialble in 3 variants - CN9130/CN9131/CN9132.
>
> CN9130 is made of a single Application Processor unit
> (AP807) and one internal south bridge (CP115). It can
> be extended to CN9131 (internal + external south bridges).
> The CN9132 has 3 south bridge units.
>
> This patchset adds all necessary components (.dsc/.fdf,
> libraries, ACPI, DT) to support all 3 variants, which
> are available on a modular CN913x Development Board.
Thanks for this contribution.
Do you have any further information on this SoC/Devboard?
Searching only gets me the CN8xxx SoCs.
> The patches are available in the github:
> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/cn913x-upstream-r20190808
>
> I'm looking forward to your comments or remarks.
First issue I run into is that 9130/9131 bail out on DSDT.aml:
"iasl"
-p/work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.aml
/work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.iiii
/work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.iiii
17: DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130DBA", 3)
Intel ACPI Component Architecture
ASL+ Optimizing Compiler/Disassembler version 20181213
Copyright (c) 2000 - 2018 Intel Corporation
ASL Input:
/work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.iiii
- 328 lines, 9303 bytes, 97 keywords
Compilation complete. 1 Errors, 0 Warnings, 0 Remarks, 34
Optimizations
Error 6155 -
Invalid OEM Table ID ^ (Length cannot exceed 8 characters)
This does not affect Cn9132DbA, since that one does not include the
ACPI module. Is this intenional?
Which version of iasl has this been tested with?
(Plese don't respin a v2, I will go through things a bit more and
provide feedback.)
Best Regards,
Leif
> Best regards,
> Marcin
>
>
> Marcin Wojtas (9):
> Marvell/Cn9130Db: Add ACPI tables
> Marvell/Cn9130Db: Add DeviceTree
> Marvell/Cn9130Db: Introduce board support
> Marvell/Library: ArmadaSoCDescLib: Extend Xenon information
> Marvell/Library: MppLib: Allow to configure more Xenon PHYs
> Marvell/Library: IcuLib: Fix debug information
> Marvell/Cn9131Db: Introduce board support
> Marvell/Cn9132Db: Introduce board support
> Marvell/Drivers: SmbiosPlatformDxe: Use more generic board name
>
> Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 107 ++++
> Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc | 72 +++
> Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 72 +++
> Platform/Marvell/Cn913xDb/Cn9130DbA.dsc | 46 ++
> Platform/Marvell/Cn913xDb/Cn9131DbA.dsc | 47 ++
> Platform/Marvell/Cn913xDb/Cn9132DbA.dsc | 45 ++
> Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf | 29 +
> Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf | 29 +
> Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 37 ++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 56 ++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 57 ++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf | 22 +
> Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf | 22 +
> Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf | 22 +
> Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 25 +
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 5 +-
> Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 39 ++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h | 20 +
> Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 36 ++
> Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c | 126 +++++
> Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | 135 +++++
> Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 215 ++++++++
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 34 +-
> Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 4 +-
> Silicon/Marvell/Library/IcuLib/IcuLib.c | 4 +-
> Silicon/Marvell/Library/MppLib/MppLib.c | 4 +-
> Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc | 17 +
> Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc | 18 +
> Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc | 13 +
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 98 ++++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 324 ++++++++++++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc | 41 ++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc | 80 +++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc | 58 ++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc | 135 +++++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc | 210 ++++++++
> Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 49 ++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi | 43 ++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi | 264 ++++++++++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi | 10 +
> Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi | 552 ++++++++++++++++++++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts | 185 +++++++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi | 168 ++++++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi | 126 +++++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts | 29 +
> Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi | 175 +++++++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 70 +++
> Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 159 ++++++
> 48 files changed, 4113 insertions(+), 21 deletions(-)
> create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
> create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
> create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
> create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc
> create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc
> create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc
> create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
> create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
> create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
> create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
> create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
> create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
> create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
> create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc
> create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc
> create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc
> create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
> create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support
2019-08-08 11:51 ` [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support Leif Lindholm
@ 2019-08-08 13:51 ` Marcin Wojtas
2019-08-08 16:48 ` Leif Lindholm
0 siblings, 1 reply; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-08 13:51 UTC (permalink / raw)
To: Leif Lindholm
Cc: edk2-devel-groups-io, Ard Biesheuvel, jsd@semihalf.com,
Grzegorz Jaszczyk, Kostya Porotchkin
Hi Leif,
czw., 8 sie 2019 o 13:51 Leif Lindholm <leif.lindholm@linaro.org> napisał(a):
>
> Hi Marcin,
>
> On Thu, Aug 08, 2019 at 01:30:21AM +0200, Marcin Wojtas wrote:
> > Hi,
> >
> > Marvell Octeon CN913X SoC is a new device, which is built of
> > upgraded hardware blocks known from previously supported line
> > of SoCs. It is avaialble in 3 variants - CN9130/CN9131/CN9132.
> >
> > CN9130 is made of a single Application Processor unit
> > (AP807) and one internal south bridge (CP115). It can
> > be extended to CN9131 (internal + external south bridges).
> > The CN9132 has 3 south bridge units.
> >
> > This patchset adds all necessary components (.dsc/.fdf,
> > libraries, ACPI, DT) to support all 3 variants, which
> > are available on a modular CN913x Development Board.
>
> Thanks for this contribution.
> Do you have any further information on this SoC/Devboard?
> Searching only gets me the CN8xxx SoCs.
>
Indeed :/ I guess there should be some public information soon,
unfortunately I'm not in charge of it.
FYI, 2 days ago the support for it was submitted to the Linux lists:
https://www.spinics.net/lists/arm-kernel/msg746208.html
In high level this SoC is successor of Armada - enhanced modularity,
more interfaces, higher freq, new DDR controller and so on.
> > The patches are available in the github:
> > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/cn913x-upstream-r20190808
> >
> > I'm looking forward to your comments or remarks.
>
> First issue I run into is that 9130/9131 bail out on DSDT.aml:
> "iasl"
> -p/work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.aml
> /work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.iiii
> /work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.iiii
> 17: DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130DBA", 3)
>
> Intel ACPI Component Architecture
> ASL+ Optimizing Compiler/Disassembler version 20181213
> Copyright (c) 2000 - 2018 Intel Corporation
>
> ASL Input:
> /work/git/tianocore/Build/Cn9130DbA-AARCH64/DEBUG_GCC5/AARCH64/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA/OUTPUT/Cn913xDbA/Dsdt.iiii
> - 328 lines, 9303 bytes, 97 keywords
>
> Compilation complete. 1 Errors, 0 Warnings, 0 Remarks, 34
> Optimizations
> Error 6155 -
> Invalid OEM Table ID ^ (Length cannot exceed 8 characters)
>
> This does not affect Cn9132DbA, since that one does not include the
> ACPI module. Is this intenional?
>
Maybe I should've mention this explicitly - yes, as for now we do not
support ACPI on triple-CP115 variant. The reason is following -
currently we have a static configuration of the ICU (CP115 interrupt
controller) to GIC. Thanks to that, we can assign GIC interrupts in
static ACPI tables. Unfortunately dual CP115/CP110 setup uses all
available GIC IRQs for this. We need to create mapping only for the
used devices and pass it to the ACPI tables.
What is needed to fix it properly:
- create ICU-GIC dynamic mapping
- dynamically fill this information in DSDT/SSDT.
> Which version of iasl has this been tested with?
>
I built it successfully with iasl versions: 20180105 and 20160108-2.
Anyway, in v2 I'll shorten OEM table ID to 8 characters ( "CN9130DBA"
is 9 character).
> (Plese don't respin a v2, I will go through things a bit more and
> provide feedback.)
>
Thanks,
Marcin
> Best Regards,
>
> Leif
>
> > Best regards,
> > Marcin
> >
> >
> > Marcin Wojtas (9):
> > Marvell/Cn9130Db: Add ACPI tables
> > Marvell/Cn9130Db: Add DeviceTree
> > Marvell/Cn9130Db: Introduce board support
> > Marvell/Library: ArmadaSoCDescLib: Extend Xenon information
> > Marvell/Library: MppLib: Allow to configure more Xenon PHYs
> > Marvell/Library: IcuLib: Fix debug information
> > Marvell/Cn9131Db: Introduce board support
> > Marvell/Cn9132Db: Introduce board support
> > Marvell/Drivers: SmbiosPlatformDxe: Use more generic board name
> >
> > Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 107 ++++
> > Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc | 72 +++
> > Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 72 +++
> > Platform/Marvell/Cn913xDb/Cn9130DbA.dsc | 46 ++
> > Platform/Marvell/Cn913xDb/Cn9131DbA.dsc | 47 ++
> > Platform/Marvell/Cn913xDb/Cn9132DbA.dsc | 45 ++
> > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf | 29 +
> > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf | 29 +
> > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 37 ++
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 56 ++
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 57 ++
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf | 22 +
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf | 22 +
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf | 22 +
> > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 25 +
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 5 +-
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 39 ++
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h | 20 +
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 36 ++
> > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c | 126 +++++
> > Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | 135 +++++
> > Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 215 ++++++++
> > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 34 +-
> > Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 4 +-
> > Silicon/Marvell/Library/IcuLib/IcuLib.c | 4 +-
> > Silicon/Marvell/Library/MppLib/MppLib.c | 4 +-
> > Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc | 17 +
> > Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc | 18 +
> > Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc | 13 +
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 98 ++++
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 324 ++++++++++++
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc | 41 ++
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc | 80 +++
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc | 58 ++
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc | 135 +++++
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc | 210 ++++++++
> > Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 49 ++
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi | 43 ++
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi | 264 ++++++++++
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi | 10 +
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi | 552 ++++++++++++++++++++
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts | 185 +++++++
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi | 168 ++++++
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi | 126 +++++
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts | 29 +
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi | 175 +++++++
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 70 +++
> > Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 159 ++++++
> > 48 files changed, 4113 insertions(+), 21 deletions(-)
> > create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
> > create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
> > create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
> > create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc
> > create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc
> > create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc
> > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
> > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
> > create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf
> > create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
> > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
> > create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
> > create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
> > create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.fdf.inc
> > create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.fdf.inc
> > create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.fdf.inc
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc
> > create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
> > create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
> >
> > --
> > 2.7.4
> >
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support
2019-08-08 13:51 ` Marcin Wojtas
@ 2019-08-08 16:48 ` Leif Lindholm
2019-08-08 17:05 ` Marcin Wojtas
0 siblings, 1 reply; 16+ messages in thread
From: Leif Lindholm @ 2019-08-08 16:48 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel-groups-io, Ard Biesheuvel, jsd@semihalf.com,
Grzegorz Jaszczyk, Kostya Porotchkin
Hi Marcin.
On Thu, Aug 08, 2019 at 03:51:15PM +0200, Marcin Wojtas wrote:
> > > This patchset adds all necessary components (.dsc/.fdf,
> > > libraries, ACPI, DT) to support all 3 variants, which
> > > are available on a modular CN913x Development Board.
> >
> > Thanks for this contribution.
> > Do you have any further information on this SoC/Devboard?
> > Searching only gets me the CN8xxx SoCs.
>
> Indeed :/ I guess there should be some public information soon,
> unfortunately I'm not in charge of it.
>
> FYI, 2 days ago the support for it was submitted to the Linux lists:
> https://www.spinics.net/lists/arm-kernel/msg746208.html
Ah, good to know, thanks.
> In high level this SoC is successor of Armada - enhanced modularity,
> more interfaces, higher freq, new DDR controller and so on.
OK. Yes, I see now these platforms are implemented as overlays on top
of existing Armada DB.
> > This does not affect Cn9132DbA, since that one does not include the
> > ACPI module. Is this intenional?
> >
>
> Maybe I should've mention this explicitly - yes, as for now we do not
> support ACPI on triple-CP115 variant. The reason is following -
> currently we have a static configuration of the ICU (CP115 interrupt
> controller) to GIC. Thanks to that, we can assign GIC interrupts in
> static ACPI tables. Unfortunately dual CP115/CP110 setup uses all
> available GIC IRQs for this. We need to create mapping only for the
> used devices and pass it to the ACPI tables.
>
> What is needed to fix it properly:
> - create ICU-GIC dynamic mapping
> - dynamically fill this information in DSDT/SSDT.
>
> > Which version of iasl has this been tested with?
> >
>
> I built it successfully with iasl versions: 20180105 and 20160108-2.
>
> Anyway, in v2 I'll shorten OEM table ID to 8 characters ( "CN9130DBA"
> is 9 character).
OK. Working around this manually (shortening the name), the 9130
builds fine. The 9131 needs an identical change to Ssdt.aml.
However, all platforms still fail when I try building for ARM (which
is supported according to the .dsc files).
It seems the build fails from the missing PcdDramRemapTarget
definition, in the build of
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S
Moreover, this also affects existing Armada70x0/80x0 platforms.
Could you look into this issue separately?
On a higher level, I confess to not being entirely convinced about the
triplicate .dsc/.dsc.inc/.fdf.inc setup. (Of the three, the .dsc.inc
is the one I object the least to.)
For the .dscs, I understand the desire to separate the build
directories, but could this be achieved with -D build flags instead?
Certainly the differences in .fdf.inc could be handled via
conditional statements determined in a single .dsc.
If (and this is a possibility) the 3 different .dscs is the right way
forward, I still think everything other than the [defines] section
should be kept in a common .dsc.inc.
(This quite possibly concludes my commentary on v1. Don't hold back a
v2 waiting for more.)
Best Regards,
Leif
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support
2019-08-08 16:48 ` Leif Lindholm
@ 2019-08-08 17:05 ` Marcin Wojtas
2019-08-08 17:53 ` Leif Lindholm
0 siblings, 1 reply; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-08 17:05 UTC (permalink / raw)
To: Leif Lindholm
Cc: edk2-devel-groups-io, Ard Biesheuvel, jsd@semihalf.com,
Grzegorz Jaszczyk, Kostya Porotchkin
czw., 8 sie 2019 o 18:48 Leif Lindholm <leif.lindholm@linaro.org> napisał(a):
>
> Hi Marcin.
>
> On Thu, Aug 08, 2019 at 03:51:15PM +0200, Marcin Wojtas wrote:
> > > > This patchset adds all necessary components (.dsc/.fdf,
> > > > libraries, ACPI, DT) to support all 3 variants, which
> > > > are available on a modular CN913x Development Board.
> > >
> > > Thanks for this contribution.
> > > Do you have any further information on this SoC/Devboard?
> > > Searching only gets me the CN8xxx SoCs.
> >
> > Indeed :/ I guess there should be some public information soon,
> > unfortunately I'm not in charge of it.
> >
> > FYI, 2 days ago the support for it was submitted to the Linux lists:
> > https://www.spinics.net/lists/arm-kernel/msg746208.html
>
> Ah, good to know, thanks.
>
> > In high level this SoC is successor of Armada - enhanced modularity,
> > more interfaces, higher freq, new DDR controller and so on.
>
> OK. Yes, I see now these platforms are implemented as overlays on top
> of existing Armada DB.
>
> > > This does not affect Cn9132DbA, since that one does not include the
> > > ACPI module. Is this intenional?
> > >
> >
> > Maybe I should've mention this explicitly - yes, as for now we do not
> > support ACPI on triple-CP115 variant. The reason is following -
> > currently we have a static configuration of the ICU (CP115 interrupt
> > controller) to GIC. Thanks to that, we can assign GIC interrupts in
> > static ACPI tables. Unfortunately dual CP115/CP110 setup uses all
> > available GIC IRQs for this. We need to create mapping only for the
> > used devices and pass it to the ACPI tables.
> >
> > What is needed to fix it properly:
> > - create ICU-GIC dynamic mapping
> > - dynamically fill this information in DSDT/SSDT.
> >
> > > Which version of iasl has this been tested with?
> > >
> >
> > I built it successfully with iasl versions: 20180105 and 20160108-2.
> >
> > Anyway, in v2 I'll shorten OEM table ID to 8 characters ( "CN9130DBA"
> > is 9 character).
>
> OK. Working around this manually (shortening the name), the 9130
> builds fine. The 9131 needs an identical change to Ssdt.aml.
>
> However, all platforms still fail when I try building for ARM (which
> is supported according to the .dsc files).
> It seems the build fails from the missing PcdDramRemapTarget
> definition, in the build of
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S
>
> Moreover, this also affects existing Armada70x0/80x0 platforms.
> Could you look into this issue separately?
Thanks for the notice, I will take a look.
>
> On a higher level, I confess to not being entirely convinced about the
> triplicate .dsc/.dsc.inc/.fdf.inc setup. (Of the three, the .dsc.inc
> is the one I object the least to.)
> For the .dscs, I understand the desire to separate the build
> directories, but could this be achieved with -D build flags instead?
> Certainly the differences in .fdf.inc could be handled via
> conditional statements determined in a single .dsc.
>
> If (and this is a possibility) the 3 different .dscs is the right way
> forward, I still think everything other than the [defines] section
> should be kept in a common .dsc.inc.
>
I will try the -D option. How about:
- single .dsc / .fdf.inc
- triple .dsc.inc (they overlap in really minimal way and show pretty
good the differences between 3 variants)
?
> (This quite possibly concludes my commentary on v1. Don't hold back a
> v2 waiting for more.)
>
Ok, thanks!
Marcin
> Best Regards,
>
> Leif
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support
2019-08-08 17:05 ` Marcin Wojtas
@ 2019-08-08 17:53 ` Leif Lindholm
2019-08-09 6:36 ` Marcin Wojtas
0 siblings, 1 reply; 16+ messages in thread
From: Leif Lindholm @ 2019-08-08 17:53 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel-groups-io, Ard Biesheuvel, jsd@semihalf.com,
Grzegorz Jaszczyk, Kostya Porotchkin
On Thu, Aug 08, 2019 at 07:05:29PM +0200, Marcin Wojtas wrote:
> > On a higher level, I confess to not being entirely convinced about the
> > triplicate .dsc/.dsc.inc/.fdf.inc setup. (Of the three, the .dsc.inc
> > is the one I object the least to.)
> > For the .dscs, I understand the desire to separate the build
> > directories, but could this be achieved with -D build flags instead?
> > Certainly the differences in .fdf.inc could be handled via
> > conditional statements determined in a single .dsc.
> >
> > If (and this is a possibility) the 3 different .dscs is the right way
> > forward, I still think everything other than the [defines] section
> > should be kept in a common .dsc.inc.
> >
>
> I will try the -D option. How about:
> - single .dsc / .fdf.inc
> - triple .dsc.inc (they overlap in really minimal way and show pretty
> good the differences between 3 variants)
> ?
Yeah, that sounds good to me. Agreed on the .dsc.inc - you could
possibly slightly decrease duplication if keeping them as one file,
but it would be more difficult to read and review changes.
Best Regards,
Leif
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-platforms: PATCH 0/9] Marvell Octeon CN913X SoC family support
2019-08-08 17:53 ` Leif Lindholm
@ 2019-08-09 6:36 ` Marcin Wojtas
0 siblings, 0 replies; 16+ messages in thread
From: Marcin Wojtas @ 2019-08-09 6:36 UTC (permalink / raw)
To: Leif Lindholm
Cc: edk2-devel-groups-io, Ard Biesheuvel, jsd@semihalf.com,
Grzegorz Jaszczyk, Kostya Porotchkin
Hi Leif,
czw., 8 sie 2019 o 19:53 Leif Lindholm <leif.lindholm@linaro.org> napisał(a):
>
> On Thu, Aug 08, 2019 at 07:05:29PM +0200, Marcin Wojtas wrote:
> > > On a higher level, I confess to not being entirely convinced about the
> > > triplicate .dsc/.dsc.inc/.fdf.inc setup. (Of the three, the .dsc.inc
> > > is the one I object the least to.)
> > > For the .dscs, I understand the desire to separate the build
> > > directories, but could this be achieved with -D build flags instead?
> > > Certainly the differences in .fdf.inc could be handled via
> > > conditional statements determined in a single .dsc.
> > >
> > > If (and this is a possibility) the 3 different .dscs is the right way
> > > forward, I still think everything other than the [defines] section
> > > should be kept in a common .dsc.inc.
> > >
> >
> > I will try the -D option. How about:
> > - single .dsc / .fdf.inc
> > - triple .dsc.inc (they overlap in really minimal way and show pretty
> > good the differences between 3 variants)
> > ?
>
> Yeah, that sounds good to me. Agreed on the .dsc.inc - you could
> possibly slightly decrease duplication if keeping them as one file,
> but it would be more difficult to read and review changes.
>
Well, when you look into .dsc.inc details, you should notice that
there is no repeated PCD (having the same value) in neither of 3
files. In case we decided to merge them into, we would end up with
ifdefs, so I'm not convinced the readability would increase...
Best regards,
Marcin
^ permalink raw reply [flat|nested] 16+ messages in thread