From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=Kcv7M7Wc; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.194, mailfrom: mw@semihalf.com) Received: from mail-lj1-f194.google.com (mail-lj1-f194.google.com [209.85.208.194]) by groups.io with SMTP; Wed, 14 Aug 2019 19:54:44 -0700 Received: by mail-lj1-f194.google.com with SMTP id u15so1004369ljl.3 for ; Wed, 14 Aug 2019 19:54:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sWlPTCKE5rD/VnB651g0bkSulp16/j6+uITx5Cu2XW0=; b=Kcv7M7Wc1jlMCojJM7l0H6Kcw91wiS/6nKH8wmig/mHC5kb2ljoM3WOJrPRZFrqmB9 FgGJhnmTi9aJDsa+7U2HfnhG3J1bGVZE5zqo+sdG/nEoVnv7FMUkIPcOpaNXIOaXCwyd KQOMp26lvljslOkcGf+ZQaZ1dUJOLdIHdOeZr4du71fV0AH117R2d2PuwkJmmfytpfPd wnQ8epvcUUKTBNMKpO1/NtpYRlHgz5KSp8uUbgvwd9MrPdL1GaeJNHwDfzKH+pKbagwq 7qCkZzEL9R9+jQYK4dCnyFU7CJ3XPVValwDIGAK4PkT8FdoZaKQzhB5GmxyMYVn1VqZj /NKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sWlPTCKE5rD/VnB651g0bkSulp16/j6+uITx5Cu2XW0=; b=qsATuBZVS0oSQXZO+1RtOqn+4NfcR9DjMtB5cGkkZh2KZ/EmFwcMD4MQ+wgp0QXH1i ZiAF2jDnywM42Jfd/NmGV+uP4rVjR6eILl0LZwXeJOUoa3zM5PMkr1xu5efrbdZcSz3R pg+qucM0U8223DErQJUI1par6gOeOIex+luSPoGbxIHlUStqmEYSuKkqwL4tNPGLkAEL 252qvGw79ITsIZaZ9nLjU9D53cHwTssU7yF9EsxdeobleMWqHyfSEpLbLaCwVAOrU+Xt tGhR3BEFMuk0Kf7D5UYfiCw0yk0k/2V8Yiot2q25vuEnhEHdAc5e4K1YOHJ5540f4GS8 6MTw== X-Gm-Message-State: APjAAAXiSURLh1giAlNqiF/GC7PGMGAfVt71rnmaaHiyDSA9OtncoGvz 1qHqMr6kABZU1Z43DDEGIWNTBiy8WiUQIw== X-Google-Smtp-Source: APXvYqy7XE9MeKAIn9ltrAytCeSVTYHTgOy/XWOOscy5zN98KxGD9k3zmZp8RyIX+jX2jQjyRlb3jA== X-Received: by 2002:a2e:760f:: with SMTP id r15mr1412888ljc.92.1565837681795; Wed, 14 Aug 2019 19:54:41 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id n17sm214035lfi.37.2019.08.14.19.54.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Aug 2019 19:54:41 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-platforms: PATCH v2 09/10] Marvell/Cn9132Db: Introduce board support Date: Thu, 15 Aug 2019 04:54:13 +0200 Message-Id: <1565837654-13258-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565837654-13258-1-git-send-email-mw@semihalf.com> References: <1565837654-13258-1-git-send-email-mw@semihalf.com> This patch introduces all necessary components required for building EDK2 firmware for CN9132-DB setup A. Note the ACPI is not yet available for this variant, due to the current ICU (CP1xx interrupt controller) support implementation. In order to build this variant, '-D CN9132' flag should be added. Otherwise the default (CN9130) will be compiled. Signed-off-by: Marcin Wojtas --- Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 72 +++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 15 ++- Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf | 29 +++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf | 22 ++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 4 + Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | 135 ++++++++++++++++++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 42 ++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc | 2 + Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 6 - Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 20 ++- 10 files changed, 333 insertions(+), 14 deletions(-) create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc new file mode 100644 index 0000000..a0b90fa --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc @@ -0,0 +1,72 @@ +## @file +# Component description file for the CN9132 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|3 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|4 + + # CP115 #2 MPP + gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000 + gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x9, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0x0, 0x2, 0x2, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 } + # ComPhy1 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: SATA0 5 Gbps + # 3: USB3_HOST1 5 Gbps + # 4: SFI 10.31 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)} + gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 } diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc index 5aca5a1..1b28fae 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -13,7 +13,9 @@ # ################################################################################ [Defines] -!if $(CN9131) +!if $(CN9132) + PLATFORM_NAME = Cn9132DbA +!elseif $(CN9131) PLATFORM_NAME = Cn9131DbA !else PLATFORM_NAME = Cn9130DbA @@ -38,16 +40,25 @@ !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc !include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc -!if $(CN9131) +!if $(CN9131) || $(CN9132) !include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc !endif +!if $(CN9132) +!include Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc +!endif [Components.common] Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf +!ifndef $(CN9132) [Components.AARCH64] Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf +!endif [LibraryClasses.common] +!if $(CN9132) + ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf +!else ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf +!endif NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf new file mode 100644 index 0000000..27a0214 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf @@ -0,0 +1,29 @@ +## @file +# +# Copyright (C) 2019, Marvell International Ltd. and its affiliates
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = Cn9132DbABoardDescLib + FILE_GUID = cf7a0f12-45fe-417b-9c34-053605973b68 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmadaBoardDescLib + +[Sources] + Cn9132DbABoardDescLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf new file mode 100644 index 0000000..c9e3b04 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell CN9130-DB-A platform +# +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = Cn9132DbADeviceTree + FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + cn9132-db-A.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h index 6618737..084bea0 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h @@ -17,5 +17,9 @@ #define CN9130_DB_SDMMC_VCCQ_PIN 15 #define CN9131_DB_VBUS0_PIN 3 #define CN9131_DB_VBUS0_LIMIT_PIN 2 +#define CN9132_DB_VBUS0_PIN 2 +#define CN9132_DB_VBUS0_LIMIT_PIN 0 +#define CN9132_DB_VBUS1_PIN 3 +#define CN9132_DB_VBUS1_LIMIT_PIN 1 #endif diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c new file mode 100644 index 0000000..d2846dd --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c @@ -0,0 +1,135 @@ +/** +* +* Copyright (C) 2019, Marvell International Ltd. and its affiliates. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +// +// GPIO Expander +// +STATIC MV_GPIO_EXPANDER mGpioExpander = { + PCA9555_ID, + 0x21, + 0x0, +}; + + +EFI_STATUS +EFIAPI +ArmadaBoardGpioExpanderGet ( + IN OUT MV_GPIO_EXPANDER **GpioExpanders, + IN OUT UINTN *GpioExpanderCount + ) +{ + *GpioExpanderCount = 1; + *GpioExpanders = &mGpioExpander; + + return EFI_SUCCESS; +} + +// +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] = { + { /* PCIE0 @0xF2640000 */ + .PcieDbiAddress = 0xF2600000, + .ConfigSpaceAddress = 0xD0000000, + .HaveResetGpio = FALSE, + .PcieResetGpio = { 0 }, + .PcieBusMin = 0, + .PcieBusMax = 0xFE, + .PcieIoTranslation = 0xDFF00000, + .PcieIoWinBase = 0x0, + .PcieIoWinSize = 0x10000, + .PcieMmio32Translation = 0, + .PcieMmio32WinBase = 0xC0000000, + .PcieMmio32WinSize = 0x10000000, + .PcieMmio64Translation = 0, + .PcieMmio64WinBase = MAX_UINT64, + .PcieMmio64WinSize = 0, + } +}; + +/** + Return the number and description of PCIE controllers used on the platform. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers = mPcieController; + *PcieControllerCount = ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// +// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib +// +STATIC +MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = { + { /* eMMC 0xF06E0000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + TRUE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x40, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, + { /* SD/MMC 0xF2780000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x19, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, + { /* SD/MMC 0xF6780000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x19, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + } +}; + +EFI_STATUS +EFIAPI +ArmadaBoardDescSdMmcGet ( + OUT UINTN *SdMmcDevCount, + OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + *SdMmcDesc = mSdMmcDescTemplate; + *SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate); + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c index dded150..42dc54a 100644 --- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c @@ -118,6 +118,45 @@ Cp1XhciInit ( MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); } +STATIC CONST MV_GPIO_PIN mCp2XhciVbusPins[] = { + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS0_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS0_LIMIT_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS1_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP2_CONTROLLER0, + CN9132_DB_VBUS1_LIMIT_PIN, + TRUE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp2XhciInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp2XhciVbusPins, + ARRAY_SIZE (mCp2XhciVbusPins), + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER); +} + STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = { { MV_GPIO_DRIVER_TYPE_PCA95XX, @@ -159,6 +198,9 @@ NonDiscoverableDeviceInitializerGet ( return Cp0XhciInit; case 2: return Cp1XhciInit; + case 3: + case 4: + return Cp2XhciInit; } } diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc index 0c321d1..78bdb79 100644 --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc @@ -12,7 +12,9 @@ # DTB INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf +!ifndef $(CN9132) !if $(ARCH) == AARCH64 # ACPI support INF RuleOverride = ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf !endif +!endif diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts index e9464f8..724d7dc 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts @@ -55,12 +55,6 @@ &cp2_sata0 { status = "okay"; - /* SLM-1521-V2, CON4 */ - sata-port@0 { - status = "okay"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy2 0>; - }; }; /* CON 2 on SLM-1683 - microSD */ diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi index 8613607..7dc6c6e 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi @@ -6,15 +6,23 @@ */ #undef CP110_NUM -#undef CP110_PCIE_MEM_SIZE +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE #undef CP110_PCIEx_CPU_MEM_BASE -#undef CP110_PCIEx_BUS_MEM_BASE +#undef CP110_PCIEx_MEM_BASE /* CP110-1 Settings */ +#define CP110_NAME cp2 #define CP110_NUM 2 -#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000) -#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) +#define CP110_BASE f6000000 +#define CP110_PCIE0_BASE f6600000 +#define CP110_PCIE1_BASE f6620000 +#define CP110_PCIE2_BASE f6640000 +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) #include "armada-cp110.dtsi" @@ -124,7 +132,7 @@ &cp2_syscon0 { cp2_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; + compatible = "marvell,armada-7k-pinctrl"; cp2_i2c0_pins: cp2-i2c-pins-0 { marvell,pins = "mpp37", "mpp38"; -- 2.7.4