[edk2-staging/RISC-V PATCH v1 13/14]: RiscVPkg/Library: Add/Update/Remove Library instances for RISC-V platform

["Abner Chang" <abner.chang@hpe.com>]

RiscVCpuLib
- Add general CSR assembly functions for C source code.

RiscVDxeIplHandoffLib
RiscVDxeIplHandoffOpenSbiLib
- Provide DxeIpl platform implementation-specifc library for RISC-V platform. Two libraries are provided in this commit,
  * Defualt library which simply switch stack and transfer
    control to DXE core.
  * Switch stack, privilege mode and then transfer control to
    DXE core through RISC-V opensbi.

RiscvOpensbiLib
- EDK2 RISC-V OpenSBI library which pull in external source files under RiscVPkg/opensbi to the build process.

PeiServicesTablePointerLibOpenSbi
- Library instance of PEI Service Table for RISC-V platform based on OpenSBI.

RiscVPlatformTempMemoryInitLibNull
- NULL lib to return temporary memory information.

RiscVDxeIplHandoffOpenSbiLib
- This is the instance of platform level DXE IPL library based on RISC-V OpenSBI implementation.

RiscVExceptionLib
- Add RISC-V Supervisor Mode trap handler

RiscVTimerLib
- Due to RISC-V timer CSR is platform implementation specific, RISC-V timer library invokes platform level timer library mputo access to timer CSRs.

PeiServicesTablePointerLibScratch
- Remove this library becasue it doesn't comform with RISC-V OpenSBI implementation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
 .../PeiServicesTablePointerLibOpenSbi.inf          |  45 ++++++++
 .../PeiServicesTablePointerLibOpenSbi.uni          | Bin 0 -> 2462 bytes
 .../PeiServicesTablePointerOpenSbi.c               | 127 +++++++++++++++++++++
 .../PeiServicesTablePointerLibScratch.inf          |  46 --------
 .../PeiServicesTablePointerLibScratch.uni          | Bin 2520 -> 0 bytes
 .../PeiServicesTablePointerScratch.c               | 120 -------------------
 RiscVPkg/Library/RiscVCpuLib/Cpu.s                 |  84 +++++++++++---
 .../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c  |  47 ++++++++
 .../RiscVDxeIplHandoffLib.inf                      |  39 +++++++
 .../RiscVDxeIplHandoffOpenSbiLib.c                 | 108 ++++++++++++++++++
 .../RiscVDxeIplHandoffOpenSbiLib.inf               |  39 +++++++
 .../RiscVExceptionLib/CpuExceptionHandler.s        |  94 +++++++++++++++
 .../CpuExceptionHandlerDxeLib.inf                  |   7 +-
 .../RiscVExceptionLib/CpuExceptionHandlerLib.c     |  44 +++----
 .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf    |  65 +++++++++++
 .../Riscv64/TempMemInit.s                          |   4 +-
 .../Library/RiscVTimerLib/BaseRiscVTimerLib.inf    |   3 +-
 17 files changed, 660 insertions(+), 212 deletions(-)
 create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
 create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
 create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
 delete mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.inf
 delete mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.uni
 delete mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerScratch.c
 create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
 create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
 create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
 create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
 create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s
 create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf

diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
new file mode 100644
index 0000000..c49377b
--- /dev/null
+++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
@@ -0,0 +1,45 @@
+## @file
+# Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
+#
+#  PEI Services Table Pointer Library implementation that retrieves a pointer to the
+#  PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
+#
+#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiServicesTablePointerLibOpenSbi
+  MODULE_UNI_FILE                = PeiServicesTablePointerLibOpenSbi.uni
+  FILE_GUID                      = B4054E46-FE75-4290-B442-4836B1265D8F
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = PeiServicesTablePointerLib|PEIM PEI_CORE
+
+  CONSTRUCTOR                    = PeiServicesTablePointerLibOpenSbiConstructor
+
+#
+#  VALID_ARCHITECTURES           = RISCV64
+#
+
+[Sources]
+  PeiServicesTablePointerOpenSbi.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  RiscVPkg/RiscVPkg.dec
+
+[Pcd]
+
+[LibraryClasses]
+  DebugLib
+  RiscVCpuLib
+  RiscVOpensbiLib
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
new file mode 100644
index 0000000000000000000000000000000000000000..e7a0c4702e4b6db9a4dd433d212f34195baf6290
GIT binary patch
literal 2462
zcmchZ+iwy<6vof9iT}fdzNl$IebX2tSZaw{2&Gn^8tx@>%d)igpI3k18J2}wZDXn-
zyR$QMF5i6TGW_^nvXTX!C;WoFv4M?jY<+uZ4_Ga&$6z&^+QL$6Gj@>(HbXjC!>a5B
zJ7z7h3-q<SV5Nm@$E`_f#?BOdNd^1BtixBE=Zg6f4eby4Zes7)-rAmhVpg{~I#X6E
z?&kox#3pv>x_#tkE4$yYUR)#2PH<lcNBErkX(o<GOr&6u_rTY=&jZ-{%o29`uo0PP
zBQd|mK*~Jo<!s*->j3*R@C1C`#@7O#M|S4eg?NCb_zNEEO(p}8+vGBMyc1&6MQ`aR
zyNO>#U``Zu<{><!*nWi0W5(z9)SlT3+vWQZHZGmP)MXl=@7h=1iS^j8uHu+rO|}-u
z2isrqICd`?_sXCK(GFI|;+Qe_uG~`;q_2$ZW4&mv$e*UYz9BzaV3s$<NW2btw^!^=
z9hsslEW#^}lnJVXEA(Q{PMF8s9`QBCTAqJ8pR~tFt2R_e!X$gqzO;KQ4;Or^2J_lk
zx>T&23`z7ganzZW7`-0aSzhW)u}U+&3U##4s_HMtl4HGeF1oybJ*_fY7G*2)C12_Z
z;=V(MWPTNw){3(M>oG#YtQx(JX`7b-yKV0Y9cM)O8W|9xbc0uAT1q5ddZ$tjMs6ja
z`00x1Cd9LJjr#>F9gz3vG27mYSUKm(^IRu6BsW!?O}f!L-evp9TwO}}sj=l<t70d7
zRh{7zJ7TP|o?FP-uhF-vNF2N6I$z3Uy$g)8E2{;@iqAFM-8lOx`@&UskHJonYC5tb
z)@xXmjk<epG81;K$!7~$$;fMzIzU$5zc9XMN61yN>g@6KIz`n!ukGa4YjDvZpX76Y
zgSR}VbhpHtL~D9>)>#v)C-QfOr8+iFuvVpGl{tIdDZ^F^1i$<3c)iHhk{lU&-Y6IL
zuqC7g(EYF5YY3JZ*`+QJ=sv1`^@QvujQuz3{2KGU?K`62T-}{7Wt;9z-Jgwhgm2>P
zcD}Oey`S6tU*4U6cW3@NO6p%nL{Yt}?J?Z$$nox;Akp*gmiI+<sNj9BPX|&*ROip{
cYuyCu^?T?}$q@bb(VZq+`X^K*SF<Yl3Gf+@ZvX%Q

literal 0
HcmV?d00001

diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
new file mode 100644
index 0000000..da68fca
--- /dev/null
+++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
@@ -0,0 +1,127 @@
+/** @file
+  PEI Services Table Pointer Library.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include <PiPei.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/SbiFirmwareContext.h>
+
+/**
+  Caches a pointer PEI Services Table.
+
+  Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
+  in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
+  Pre-EFI Initialization Core Interface Specification.
+
+  If PeiServicesTablePointer is NULL, then ASSERT().
+
+  @param    PeiServicesTablePointer   The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+  IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+  )
+{
+  struct sbi_platform *ThisSbiPlatform;
+  EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+  ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
+  FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context;
+  FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer;
+
+  DEBUG ((EFI_D_ERROR, "[OpenSBI]: Set PEI Service 0x%x at Firmware Context at 0x%x\n",
+           PeiServicesTablePointer,
+           ThisSbiPlatform->firmware_context
+           ));
+}
+
+/**
+  Retrieves the cached value of the PEI Services Table pointer.
+
+  Returns the cached value of the PEI Services Table pointer in a CPU specific manner
+  as specified in the CPU binding section of the Platform Initialization Pre-EFI
+  Initialization Core Interface Specification.
+
+  If the cached PEI Services Table pointer is NULL, then ASSERT().
+
+  @return  The pointer to PeiServices.
+
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+  VOID
+  )
+{
+  struct sbi_platform *ThisSbiPlatform;
+  EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+  ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
+  FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context;
+  return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;
+}
+
+/**
+  The constructor function caches the pointer to PEI services.
+
+  The constructor function caches the pointer to PEI services.
+  It will always return EFI_SUCCESS.
+
+  @param  FileHandle   The handle of FFS header the loaded driver.
+  @param  PeiServices  The pointer to the PEI services.
+
+  @retval EFI_SUCCESS  The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesTablePointerLibOpenSbiConstructor (
+  IN EFI_PEI_FILE_HANDLE        FileHandle,
+  IN CONST EFI_PEI_SERVICES     **PeiServices
+  )
+{
+  SetPeiServicesTablePointer (PeiServices);
+  return EFI_SUCCESS;
+}
+
+/**
+  Perform CPU specific actions required to migrate the PEI Services Table
+  pointer from temporary RAM to permanent RAM.
+
+  For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+  immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+  For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+  immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+  For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
+  a dedicated CPU register.  This means that there is no memory storage
+  associated with storing the PEI Services Table pointer, so no additional
+  migration actions are required for Itanium or ARM CPUs.
+
+**/
+VOID
+EFIAPI
+MigratePeiServicesTablePointer (
+  VOID
+  )
+{
+  //
+  //  PEI Services Table pointer is cached in the global variable. No additional
+  //  migration actions are required.
+  //
+  return;
+}
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.inf b/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.inf
deleted file mode 100644
index 0b7cf65..0000000
--- a/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.inf
+++ /dev/null
@@ -1,46 +0,0 @@
-## @file
-# Instance of PEI Services Table Pointer Library using global variable for the table pointer.
-#
-#  PEI Services Table Pointer Library implementation that retrieves a pointer to the
-#  PEI Services Table from a global variable. Not available to modules that execute from
-#  read-only memory.
-#
-#  Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php.
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = PeiServicesTablePointerLibScratch
-  MODULE_UNI_FILE                = PeiServicesTablePointerLibScratch.uni
-  FILE_GUID                      = A25AEF27-1FA3-43CC-8870-A89D1D2079C2
-  MODULE_TYPE                    = PEIM
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = PeiServicesTablePointerLib|PEIM PEI_CORE
-
-  CONSTRUCTOR                    = PeiServicesTablePointerLibScratchConstructor
-
-#
-#  VALID_ARCHITECTURES           = RISCV64
-#
-
-[Sources]
-  PeiServicesTablePointerScratch.c
-
-[Packages]
-  MdePkg/MdePkg.dec
-  RiscVPkg/RiscVPkg.dec
-
-[Pcd]
-
-[LibraryClasses]
-  DebugLib
-  RiscVCpuLib
-
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.uni b/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.uni
deleted file mode 100644
index 8cc751e99fff60f17030a3078e64cab3b382a90b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2520
zcmdUxQEyT~5QXR2#Q(6NFKSv)AAB&zSPELA7D6G_r{+R|5(}3Awe6o*zcbs*mIiH2
zOw=^@?%kc)nKNh3vi<(8VigNKPxuS=#)dYwGaJ}Ld%&t}4V&7+mX<O0u>{NU3f8hZ
zwqS>>&Fw4uWL>b*!MEp8<dtKYvR_`oJ}~R?mGN9LKWB&RBfdxM$+2dPfr#=M--tED
zsu)W<bsWM}<e9DIDX;LSI{pmau}y5|wN1dFx-y<I*{9dYG!Nh$Fbe;GN+K^A>+3jG
zOTMb;cd-tMpMxiW;V$;dcpTs@Y?*VbJ}3SnjtL$o^h63!C&hHEXJD7C^|7gw0R_a|
z39~BB*u6uHDG}6Naio~)^`@TeVVhwSPa|>(-6OI*W_)f>?U}u>ZNB%3bK$6#?$aVu
z-@fpklQE#gLSZwHwQ!6z-r`=WnmHDENrNrW1lz?TrKRkuS#@Z?G(8}C*<M-I+V*;b
zraE9AJ5$P=Q-hQpJ2G`-g;s^PkB8KwlXS(tsQL->csiu@GomF<RiD^C!&|3ICsCNx
z!x&$?PuyoySI^xmp1cA{%r$Y;MHC@ZyfH|kmc>Lo=f%D%C%wk1PH@7KuwFP9ecnR1
zUad|+p{K}~a_Lt^-1l5nF|Ya}R-?wGM0H4*FL~d_w9bq4mbvbF*ZXrKN1nuS!YZXL
z>BLL_jgvYexALERb!Dob)6dE+?iZ}|KrWrHXD<`wlqcz2mF%NU{R+0NY43RN+DGOM
zxD2qVvBPQug?0I=JHuU0YK`wUK1GDYe#7>#9k5f8n|w*hdY2d#S5ZrhRiA6NeWUgx
z?26j-jKPlZYCEz6)*D1sjHYLAGZS{LDQ5>?`6z4jdW)~Je`b7-MaXqxbvH!ps-kY6
zR&i4F23)kzlXBK>@Rs_dTdCsMwWeolrJ8tpB7et3Y7(PMw7MOGNPLOeUD)b?;AekZ
zbWx{ZMCUW!(w(%hLo6XJf$smi|4J*)?#GwZb_i2aVr$jmO`P4$S8;m({rmR5|HBk_
Q-QT=t<Gu9j`!#j_2jj4t1ONa4

diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerScratch.c b/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerScratch.c
deleted file mode 100644
index eccef62..0000000
--- a/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerScratch.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/** @file
-  PEI Services Table Pointer Library.
-
-  Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#include <PiPei.h>
-#include <Library/PeiServicesTablePointerLib.h>
-#include <Library/DebugLib.h>
-#include <Library/RiscVCpuLib.h>
-
-/**
-  Caches a pointer PEI Services Table.
-
-  Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
-  in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
-  Pre-EFI Initialization Core Interface Specification.
-
-  If PeiServicesTablePointer is NULL, then ASSERT().
-
-  @param    PeiServicesTablePointer   The address of PeiServices pointer.
-**/
-VOID
-EFIAPI
-SetPeiServicesTablePointer (
-  IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
-  )
-{
-  RISCV_MACHINE_MODE_CONTEXT *Context;
-
-  Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
-  //DEBUG ((DEBUG_INFO, "PEI set RISC-V Machine mode context at %x, PEI Service\n", Context, PeiServicesTablePointer));
-  Context->PeiService = (EFI_PHYSICAL_ADDRESS)(UINTN)PeiServicesTablePointer;
-}
-
-/**
-  Retrieves the cached value of the PEI Services Table pointer.
-
-  Returns the cached value of the PEI Services Table pointer in a CPU specific manner
-  as specified in the CPU binding section of the Platform Initialization Pre-EFI
-  Initialization Core Interface Specification.
-
-  If the cached PEI Services Table pointer is NULL, then ASSERT().
-
-  @return  The pointer to PeiServices.
-
-**/
-CONST EFI_PEI_SERVICES **
-EFIAPI
-GetPeiServicesTablePointer (
-  VOID
-  )
-{
-  RISCV_MACHINE_MODE_CONTEXT *Context;
-  EFI_PEI_SERVICES **PeiServices;
-
-  Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
-  PeiServices = (EFI_PEI_SERVICES **)Context->PeiService;
-  //DEBUG ((DEBUG_INFO, "PEI Get RISC-V Machine mode context at %x, PEI Service\n", Context, PeiServices));
-
-  return (CONST EFI_PEI_SERVICES **)PeiServices;
-}
-
-/**
-  The constructor function caches the pointer to PEI services.
-
-  The constructor function caches the pointer to PEI services.
-  It will always return EFI_SUCCESS.
-
-  @param  FileHandle   The handle of FFS header the loaded driver.
-  @param  PeiServices  The pointer to the PEI services.
-
-  @retval EFI_SUCCESS  The constructor always returns EFI_SUCCESS.
-
-**/
-EFI_STATUS
-EFIAPI
-PeiServicesTablePointerLibScratchConstructor (
-  IN EFI_PEI_FILE_HANDLE        FileHandle,
-  IN CONST EFI_PEI_SERVICES     **PeiServices
-  )
-{
-  SetPeiServicesTablePointer (PeiServices);
-  return EFI_SUCCESS;
-}
-
-/**
-  Perform CPU specific actions required to migrate the PEI Services Table
-  pointer from temporary RAM to permanent RAM.
-
-  For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
-  immediately preceding the Interrupt Descriptor Table (IDT) in memory.
-  For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
-  immediately preceding the Interrupt Descriptor Table (IDT) in memory.
-  For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
-  a dedicated CPU register.  This means that there is no memory storage
-  associated with storing the PEI Services Table pointer, so no additional
-  migration actions are required for Itanium or ARM CPUs.
-
-**/
-VOID
-EFIAPI
-MigratePeiServicesTablePointer (
-  VOID
-  )
-{
-  //
-  //  PEI Services Table pointer is cached in the global variable. No additional
-  //  migration actions are required.
-  //
-  return;
-}
diff --git a/RiscVPkg/Library/RiscVCpuLib/Cpu.s b/RiscVPkg/Library/RiscVCpuLib/Cpu.s
index 5dc6bc1..27fc091 100644
--- a/RiscVPkg/Library/RiscVCpuLib/Cpu.s
+++ b/RiscVPkg/Library/RiscVCpuLib/Cpu.s
@@ -2,7 +2,7 @@
 //
 // RISC-V CPU functions.
 //
-// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 //
 // This program and the accompanying materials
 // are licensed and made available under the terms and conditions of the BSD License
@@ -23,10 +23,16 @@
 
 .global ASM_PFX(RiscVSetScratch)
 .global ASM_PFX(RiscVGetScratch)
-.global ASM_PFX(RiscVReadMachineTimer)
-.global ASM_PFX(RiscVSetMachineTimerCmp)
 .global ASM_PFX(RiscVGetMachineTrapCause)
-
+.global ASM_PFX(RiscVReadMachineIE)
+.global ASM_PFX(RiscVReadMachineIP)
+.global ASM_PFX(RiscVReadMachineStatus)
+.global ASM_PFX(RiscVWriteMachineStatus)
+.global ASM_PFX(RiscVReadMachineTvec)
+.global ASM_PFX(RiscVReadMisa)
+.global ASM_PFX(RiscVReadMVendorId)
+.global ASM_PFX(RiscVReadMArchId)
+.global ASM_PFX(RiscVReadMImplId)
 //
 // Set machine mode scratch.
 // @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
@@ -44,24 +50,72 @@ ASM_PFX (RiscVGetScratch):
     ret
 
 //
-// Read machine timer CSR.
-// @retval a0 : 32-bit machine timer.
+// Get machine trap cause CSR.
 //
-ASM_PFX (RiscVReadMachineTimer):
-    csrrs a0, RISCV_CSR_MACHINE_MTIME, 0
+ASM_PFX (RiscVGetMachineTrapCause):
+    csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
     ret
 
 //
-// Set machine timer compare CSR.
-// @param a0 : UINT32
+// Get machine interrupt enable
 //
-ASM_PFX (RiscVSetMachineTimerCmp):
-    csrrw a1, RISCV_CSR_MACHINE_MTIMECMP, a0
+ASM_PFX (RiscVReadMachineIE):
+    csrr a0, RISCV_CSR_MACHINE_MIE
     ret
 
 //
-// Get machine trap cause CSR.
+// Get machine interrupt pending
 //
-ASM_PFX (RiscVGetMachineTrapCause):
-    csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
+ASM_PFX (RiscVReadMachineIP):
+    csrr a0, RISCV_CSR_MACHINE_MIP
+    ret
+
+//
+// Get machine status
+//
+ASM_PFX(RiscVReadMachineStatus):
+    csrr a0, RISCV_CSR_MACHINE_MSTATUS
+    ret
+
+//
+// Set machine status
+//
+ASM_PFX(RiscVWriteMachineStatus):
+    csrw RISCV_CSR_MACHINE_MSTATUS, a0
+    ret
+
+//
+// Get machine trap vector
+//
+ASM_PFX(RiscVReadMachineTvec):
+    csrr a0, RISCV_CSR_MACHINE_MTVEC
+    ret
+
+//
+// Read machine ISA
+//
+ASM_PFX(RiscVReadMisa):
+    csrr a0, RISCV_CSR_MACHINE_MISA
+    ret
+
+//
+// Read machine vendor ID
+//
+ASM_PFX(RiscVReadMVendorId):
+    csrr a0, RISCV_CSR_MACHINE_MVENDORID
     ret
+
+//
+// Read machine architecture ID
+//
+ASM_PFX(RiscVReadMArchId):
+    csrr a0, RISCV_CSR_MACHINE_MARCHID
+    ret
+
+//
+// Read machine implementation ID
+//
+ASM_PFX(RiscVReadMImplId):
+    csrr a0, RISCV_CSR_MACHINE_MIMPID
+    ret
+
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
new file mode 100644
index 0000000..309cb19
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
@@ -0,0 +1,47 @@
+/** @file
+  RISC-V platform level DXE core hand off library
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+/**
+   RISC-V platform DXE IPL to DXE core handoff process.
+
+   This function performs a CPU architecture specific operations to execute
+   the entry point of DxeCore with the parameters of HobList.
+   It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+    
+   @param BaseOfStack        Base address of stack
+   @param TopOfStack         Top address of stack 
+   @param DxeCoreEntryPoint  The entry point of DxeCore.
+   @param HobList            The start of HobList passed to DxeCore.
+
+**/
+
+VOID
+RiscVPlatformHandOffToDxeCore (
+  IN VOID *BaseOfStack,
+  IN VOID *TopOfStack,
+  IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+  IN EFI_PEI_HOB_POINTERS HobList
+  )
+{
+
+  //
+  // Transfer the control to the entry point of DxeCore.
+  //
+  SwitchStack (
+    (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
+    HobList.Raw,
+    NULL,
+    TopOfStack
+    );
+}
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
new file mode 100644
index 0000000..62599ac
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
@@ -0,0 +1,39 @@
+## @file
+#  Instance of RISC-V DXE IPL to DXE core handoff platform library
+#
+#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = RiscVPlatformDxeIplLib
+  FILE_GUID                      = 2A77EE71-9F55-43F9-8773-7854A5B56086
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RiscVPlatformDxeIplLib|PEIM PEI_CORE
+
+#
+#  VALID_ARCHITECTURES           = RISCV64
+#
+
+[Sources]
+  RiscVDxeIplHandoffLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+  DebugLib
+  RiscVCpuLib
+  RiscVOpensbiLib
+
+[Pcd]
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
new file mode 100644
index 0000000..37b4d32
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
@@ -0,0 +1,108 @@
+/** @file
+  RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution. The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+
+#include <sbi/sbi.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_init.h>
+#include <sbi/riscv_encoding.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/RiscVPlatformDxeIpl.h>
+
+/**
+   RISC-V platform DXE IPL to DXE OpenSBI mdoe switch handler. 
+   This function is executed in RISC-V Supervisor mode.
+
+   This function performs a CPU architecture specific operations to execute
+   the entry point of DxeCore with the parameters of HobList.
+   It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+    
+   @param BaseOfStack        Base address of stack
+   @param TopOfStack         Top address of stack 
+   @param DxeCoreEntryPoint  The entry point of DxeCore.
+   @param HobList            The start of HobList passed to DxeCore.
+
+**/
+VOID
+RiscVDxeIplHandoffOpenSbiHandler (
+  IN UINTN HardId,
+  IN OPENSBI_SWITCH_MODE_CONTEXT *ThisSwitchContext
+  )
+{
+  DEBUG ((EFI_D_INFO, "[OpenSBI]: OpenSBI mode switch DXE IPL Handoff handler entry\n"));
+
+  SwitchStack (
+    (SWITCH_STACK_ENTRY_POINT)(UINTN)ThisSwitchContext->DxeCoreEntryPoint,
+    ThisSwitchContext->HobList.Raw,
+    NULL,
+    ThisSwitchContext->TopOfStack
+    );
+
+  //
+  // Shold never came back.
+  //
+  __builtin_unreachable();
+}
+
+
+/**
+   RISC-V platform DXE IPL to DXE core handoff process.
+
+   This function performs a CPU architecture specific operations to execute
+   the entry point of DxeCore with the parameters of HobList.
+   It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+    
+   @param BaseOfStack        Base address of stack
+   @param TopOfStack         Top address of stack 
+   @param DxeCoreEntryPoint  The entry point of DxeCore.
+   @param HobList            The start of HobList passed to DxeCore.
+
+**/
+VOID
+RiscVPlatformHandOffToDxeCore (
+  IN VOID *BaseOfStack,
+  IN VOID *TopOfStack,
+  IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+  IN EFI_PEI_HOB_POINTERS HobList
+  )
+{
+  struct sbi_scratch *ThisScratch;
+  OPENSBI_SWITCH_MODE_CONTEXT OpenSbiSwitchModeContext;
+
+  DEBUG ((EFI_D_INFO, "[OpenSBI]: DXE IPL to DXE Core using OpenSBI\n"));
+  //
+  // Setup next address in OpenSBI scratch
+  //
+  OpenSbiSwitchModeContext.BaseOfStack = BaseOfStack;
+  OpenSbiSwitchModeContext.TopOfStack = TopOfStack;
+  OpenSbiSwitchModeContext.HobList = HobList;
+  OpenSbiSwitchModeContext.DxeCoreEntryPoint = DxeCoreEntryPoint;
+  ThisScratch = sbi_scratch_thishart_ptr ();
+  ThisScratch->next_arg1 = (unsigned long)(UINTN)&OpenSbiSwitchModeContext;
+  ThisScratch->next_addr = (unsigned long)(UINTN)RiscVDxeIplHandoffOpenSbiHandler;
+  ThisScratch->next_mode = PRV_S;
+
+  DEBUG ((EFI_D_INFO, "          Base address of satck: 0x%x\n", BaseOfStack));
+  DEBUG ((EFI_D_INFO, "          Top address of satck: 0x%x\n", TopOfStack));
+  DEBUG ((EFI_D_INFO, "          HOB list address: 0x%x\n", &HobList));
+  DEBUG ((EFI_D_INFO, "          DXE core entry pointer: 0x%x\n", DxeCoreEntryPoint));
+  DEBUG ((EFI_D_INFO, "          OpenSBI Switch mode arg1: 0x%x\n", (UINTN)&OpenSbiSwitchModeContext));
+  DEBUG ((EFI_D_INFO, "          OpenSBI Switch mode handler address: 0x%x\n", (UINTN)RiscVDxeIplHandoffOpenSbiHandler));
+  DEBUG ((EFI_D_INFO, "          OpenSBI Switch mode to privilege 0x%x\n", PRV_S));
+  sbi_init (ThisScratch);
+}
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
new file mode 100644
index 0000000..3ddfe41
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
@@ -0,0 +1,39 @@
+## @file
+#  Instance of RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
+#
+#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = RiscVPlatformDxeIplLib
+  FILE_GUID                      = 906A4BB9-8DE2-4CE0-A609-23818A8FF514 
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RiscVPlatformDxeIplLib|PEIM PEI_CORE
+
+#
+#  VALID_ARCHITECTURES           = RISCV64
+#
+
+[Sources]
+  RiscVDxeIplHandoffOpenSbiLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+  DebugLib
+  RiscVCpuLib
+  RiscVOpensbiLib
+
+[Pcd]
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s
new file mode 100644
index 0000000..a987c9b
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s
@@ -0,0 +1,94 @@
+/** @file
+  RISC-V Processor supervisor mode trap handler
+   
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>  
+
+  This program and the accompanying materials are licensed and made available under 
+  the terms and conditions of the BSD License that accompanies this distribution.  
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.                                          
+    
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+**/
+
+#include <Base.h>
+#include <RiscV.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_trap.h>
+
+  .align 3
+  .section .entry, "ax", %progbits
+  .globl _strap_handler
+_strap_handler:
+  addi sp, sp, -34*8
+ /* Save all general regisers except SP and T0 */
+  sd	ra, 1*8(sp)
+  sd	gp, 2*8(sp)
+  sd	tp, 3*8(sp)
+  sd	t1, 4*8(sp)
+  sd	t2, 5*8(sp)
+  sd	s0, 6*8(sp)
+  sd	s1, 7*8(sp)
+  sd	a0, 8*8(sp)
+  sd	a1, 9*8(sp)
+  sd	a2, 10*8(sp)
+  sd	a3, 11*8(sp)
+  sd	a4, 12*8(sp)
+  sd	a5, 13*8(sp)
+  sd	a6, 14*8(sp)
+  sd	a7, 15*8(sp)
+  sd	s2, 16*8(sp)
+  sd	s3, 17*8(sp)
+  sd	s4, 18*8(sp)
+  sd	s5, 19*8(sp)
+  sd	s6, 20*8(sp)
+  sd	s7, 21*8(sp)
+  sd	s8, 22*8(sp)
+  sd	s9, 23*8(sp)
+  sd	s10, 24*8(sp)
+  sd	s11, 25*8(sp)
+  sd	t3, 26*8(sp)
+  sd	t4, 27*8(sp)
+  sd	t5, 28*8(sp)
+  sd	t6, 29*8(sp)
+
+  /* Call C routine */
+  call	RiscVSupervisorModeTrapHandler
+
+  /* Restore all general regisers except SP and T0 */
+  ld	ra, 1*8(sp)
+  ld	gp, 2*8(sp)
+  ld	tp, 3*8(sp)
+  ld	t1, 4*8(sp)
+  ld	t2, 5*8(sp)
+  ld	s0, 6*8(sp)
+  ld	s1, 7*8(sp)
+  ld	a0, 8*8(sp)
+  ld	a1, 9*8(sp)
+  ld	a2, 10*8(sp)
+  ld	a3, 11*8(sp)
+  ld	a4, 12*8(sp)
+  ld	a5, 13*8(sp)
+  ld	a6, 14*8(sp)
+  ld	a7, 15*8(sp)
+  ld	s2, 16*8(sp)
+  ld	s3, 17*8(sp)
+  ld	s4, 18*8(sp)
+  ld	s5, 19*8(sp)
+  ld	s6, 20*8(sp)
+  ld	s7, 21*8(sp)
+  ld	s8, 22*8(sp)
+  ld	s9, 23*8(sp)
+  ld	s10, 24*8(sp)
+  ld	s11, 25*8(sp)
+  ld	t3, 26*8(sp)
+  ld	t4, 27*8(sp)
+  ld	t5, 28*8(sp)
+  ld	t6, 29*8(sp)
+  addi sp, sp, 34*8
+  sret
\ No newline at end of file
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
index f9bcd01..04bdd6a 100644
--- a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
@@ -1,7 +1,7 @@
 ## @file
 #  RISC-V CPU Exception Handler Library
 #
-#  Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -25,9 +25,12 @@
 #
 # The following information is for reference only and not required by the build tools.
 #
-#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC
+#  VALID_ARCHITECTURES           = RISCV64
 #
 
+[Sources.RISCV64]
+  CpuExceptionHandler.s
+
 [Sources.common]
   CpuExceptionHandlerLib.c
 
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
index d185ce1..e3d42b3 100644
--- a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
@@ -1,7 +1,7 @@
 /** @file
   RISC-V Exception Handler library implementition.
 
-  Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -16,7 +16,13 @@
 #include <Library/CpuExceptionHandlerLib.h>
 #include <Library/DebugLib.h>
 #include <Library/RiscVCpuLib.h>
+#include <sbi/sbi_types.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
 
+
+extern void _strap_handler(void);
+EFI_CPU_INTERRUPT_HANDLER gInterruptHandlers[2];
 /**
   Initializes all CPU exceptions entries and provides the default exception handlers.
 
@@ -97,15 +103,9 @@ RegisterCpuInterruptHandler (
   IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
   )
 {
-  RISCV_MACHINE_MODE_CONTEXT *Context;
-  EFI_PHYSICAL_ADDRESS *InterruptHandlerPtr;
-  //
-  // Set machine mode interrupt handler.
-  //
-  Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
+
   DEBUG ((DEBUG_INFO, "RegisterCpuInterruptHandler: Type:%x Handler: %x\n", InterruptType, InterruptHandler));
-  InterruptHandlerPtr = &Context->MModeHandler.IntHandlerContext.SoftwareIntHandler;
-  *(InterruptHandlerPtr + InterruptType) = (EFI_PHYSICAL_ADDRESS)(UINTN)InterruptHandler;
+  gInterruptHandlers[InterruptType] = InterruptHandler;
   return EFI_SUCCESS;
 }
 /**
@@ -113,26 +113,18 @@ RegisterCpuInterruptHandler (
 
 **/
 VOID
-RiscVMachineModeTrapHandler (
+RiscVSupervisorModeTrapHandler (
   VOID
   )
 {
-  RISCV_MACHINE_MODE_CONTEXT *Context;
-  EFI_PHYSICAL_ADDRESS InterruptHandlerPtr;
   EFI_SYSTEM_CONTEXT RiscVSystemContext;
 
-  Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
-
   //
-  // Check machine casue register.
+  // Check scasue register.
   //
-
-  InterruptHandlerPtr = Context->MModeHandler.IntHandlerContext.TimerIntHandler;
-  ((EFI_CPU_INTERRUPT_HANDLER)InterruptHandlerPtr) (
-                               EXCEPT_RISCV_TIMER_INT,
-                               (CONST EFI_SYSTEM_CONTEXT)RiscVSystemContext
-                               );
-
+  if(gInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL) {
+    gInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, (CONST EFI_SYSTEM_CONTEXT)RiscVSystemContext);
+  }
 }
 
 /**
@@ -153,12 +145,10 @@ CpuExceptionHandlerLibConstructor (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  RISCV_MACHINE_MODE_CONTEXT *Context;
   //
-  // Set machine trap handler.
+  // Set Superviosr mode trap handler.
   //
-  Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
-  Context->MachineModeTrapHandler = (EFI_PHYSICAL_ADDRESS)(UINTN)RiscVMachineModeTrapHandler;
-  DEBUG((DEBUG_INFO, "RISC-V context at 0x%x, MachineModeTrapHandler = 0x%x\n", Context, Context->MachineModeTrapHandler));
+  csr_write(CSR_STVEC, _strap_handler);
+
   return EFI_SUCCESS;
 }
diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
new file mode 100644
index 0000000..05180da
--- /dev/null
+++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
@@ -0,0 +1,65 @@
+## @file
+# RISC-V Opensbi Library Instance.
+#
+#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+#  This program and the accompanying materials are licensed and made
+#  available under the terms and conditions of the BSD License which
+#  accompanies this distribution.   The full text of the license may
+#  be found at http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION    = 0x00010005
+  BASE_NAME      = RiscVOpensbiLib
+  FILE_GUID      = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
+  MODULE_TYPE    = BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = RiscVOpensbiLib
+
+[Sources]
+  ../../opensbi/lib/sbi/riscv_asm.c
+  ../../opensbi/lib/sbi/riscv_atomic.c
+  ../../opensbi/lib/sbi/riscv_hardfp.S
+  ../../opensbi/lib/sbi/riscv_locks.c
+  ../../opensbi/lib/sbi/riscv_unpriv.c
+  ../../opensbi/lib/sbi/sbi_console.c
+  ../../opensbi/lib/sbi/sbi_ecall.c
+  ../../opensbi/lib/sbi/sbi_emulate_csr.c
+  ../../opensbi/lib/sbi/sbi_fifo.c
+  ../../opensbi/lib/sbi/sbi_hart.c
+  ../../opensbi/lib/sbi/sbi_illegal_insn.c
+  ../../opensbi/lib/sbi/sbi_init.c
+  ../../opensbi/lib/sbi/sbi_ipi.c
+  ../../opensbi/lib/sbi/sbi_misaligned_ldst.c
+  ../../opensbi/lib/sbi/sbi_scratch.c
+  ../../opensbi/lib/sbi/sbi_string.c
+  ../../opensbi/lib/sbi/sbi_system.c
+  ../../opensbi/lib/sbi/sbi_timer.c
+  ../../opensbi/lib/sbi/sbi_tlb.c
+  ../../opensbi/lib/sbi/sbi_trap.c
+  ../../opensbi/lib/utils/sys/clint.c
+  ../../opensbi/lib/utils/irqchip/plic.c
+  ../../opensbi/lib/utils/serial/sifive-uart.c
+  ../../opensbi/lib/utils/serial/uart8250.c
+  ../../opensbi/lib/utils/libfdt/fdt.c
+  ../../opensbi/lib/utils/libfdt/fdt_ro.c
+  ../../opensbi/lib/utils/libfdt/fdt_wip.c
+  ../../opensbi/lib/utils/libfdt/fdt_rw.c
+  ../../opensbi/lib/utils/libfdt/fdt_sw.c
+  ../../opensbi/lib/utils/libfdt/fdt_strerror.c
+  ../../opensbi/lib/utils/libfdt/fdt_empty_tree.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  PcdLib
+  RiscVCpuLib
+
diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s
index 61b02c3..22ff329 100644
--- a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s
+++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s
@@ -2,7 +2,7 @@
 //
 // RISC-V RiscVPlatformTemporaryMemInit.
 //
-// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 // This program and the accompanying materials
 // are licensed and made available under the terms and conditions of the BSD License
 // which accompanies this distribution.  The full text of the license may be found at
@@ -26,4 +26,6 @@
 //          a1 Temporary memory size.
 //
 ASM_PFX(RiscVPlatformTemporaryMemInit):
+    li      a0, FixedPcdGet32 (PcdRiscVSecPeiTempRamBase)
+    li      a1, FixedPcdGet32 (PcdRiscVSecPeiTempRamSize)
     ret
diff --git a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
index 06e4497..66e821b 100644
--- a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
@@ -1,7 +1,7 @@
 ## @file
 # RISC-V Timer Library Instance.
 #
-#  Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
 #  This program and the accompanying materials are licensed and made
 #  available under the terms and conditions of the BSD License which
@@ -36,4 +36,5 @@
   BaseLib
   PcdLib
   RiscVCpuLib
+  RiscVPlatformTimerLib
 
-- 
2.7.4