[edk2-staging/RISC-V PATCH v1 4/14]: MdePkg/Include: Update SmBios header file.

["Abner Chang" <abner.chang@hpe.com>]

Update SmBios header file to conform with SMBIOS v3.3.0.
The major update is to add definitions of SMBIOS Type 44h record.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
 MdePkg/Include/IndustryStandard/SmBios.h | 76 ++++++++++++++++++++++++++++++--
 1 file changed, 73 insertions(+), 3 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h
index c66422f..fd91a79 100644
--- a/MdePkg/Include/IndustryStandard/SmBios.h
+++ b/MdePkg/Include/IndustryStandard/SmBios.h
@@ -2,7 +2,7 @@
   Industry Standard Definitions of SMBIOS Table Specification v3.0.0.
 
 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
+(C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development LP<BR>
 This program and the accompanying materials are licensed and made available under 
 the terms and conditions of the BSD License that accompanies this distribution.  
 The full text of the license may be found at
@@ -52,7 +52,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF
 
 //
-// SMBIOS type macros which is according to SMBIOS 2.7 specification.
+// SMBIOS type macros which is according to SMBIOS 3.3.0 specification.
 //
 #define SMBIOS_TYPE_BIOS_INFORMATION                     0
 #define SMBIOS_TYPE_SYSTEM_INFORMATION                   1
@@ -97,6 +97,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define SMBIOS_TYPE_ADDITIONAL_INFORMATION               40
 #define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41
 #define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42
+#define SMBIOS_TYPE_TPM_DEVICE                           43
+#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION     44
 
 ///
 /// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.
@@ -696,7 +698,10 @@ typedef enum {
   ProcessorFamilyMII                   = 0x012E,
   ProcessorFamilyWinChip               = 0x0140,
   ProcessorFamilyDSP                   = 0x015E,
-  ProcessorFamilyVideoProcessor        = 0x01F4
+  ProcessorFamilyVideoProcessor        = 0x01F4,
+  ProcessorFamilyRiscvRV32             = 0x0200,  ///< SMBIOS spec 3.3.0 added
+  ProcessorFamilyRiscVRV64             = 0x0201,  ///< SMBIOS spec 3.3.0 added
+  ProcessorFamilyRiscVRV128            = 0x0202   ///< SMBIOS spec 3.3.0 added
 } PROCESSOR_FAMILY2_DATA;
 
 ///
@@ -814,6 +819,19 @@ typedef struct {
 } PROCESSOR_FEATURE_FLAGS;
 
 typedef struct {
+  UINT32  ProcessorReserved1             :1;
+  UINT32  ProcessorUnknown               :1;
+  UINT32  Processor64BitCapble           :1;
+  UINT32  ProcessorMultiCore             :1;
+  UINT32  ProcessorHardwareThread        :1;
+  UINT32  ProcessorExecuteProtection     :1;
+  UINT32  ProcessorEnhancedVirtulization :1;
+  UINT32  ProcessorPowerPerformanceCtrl  :1;
+  UINT32  Processor128bitCapble          :1;
+  UINT32  ProcessorReserved2             :7;
+} PROCESSOR_CHARACTERISTIC_FLAGS;
+
+typedef struct {
   PROCESSOR_SIGNATURE     Signature;
   PROCESSOR_FEATURE_FLAGS FeatureFlags;
 } PROCESSOR_ID_DATA;
@@ -2358,6 +2376,57 @@ typedef struct {
   UINT8                             MCHostInterfaceData[1]; ///< This field has a minimum of four bytes
 } SMBIOS_TABLE_TYPE42;
 
+
+///
+/// Processor Specific Block - Processor Architecture Type
+///
+typedef enum{
+  ProcessorSpecificBlockArchTypeReserved   = 0x00,
+  ProcessorSpecificBlockArchTypeIa32       = 0x01,
+  ProcessorSpecificBlockArchTypeX64        = 0x02,
+  ProcessorSpecificBlockArchTypeItanium    = 0x03,
+  ProcessorSpecificBlockArchTypeAarch32    = 0x04,
+  ProcessorSpecificBlockArchTypeAarch64    = 0x05,
+  ProcessorSpecificBlockArchTypeRiscVRV32  = 0x06,
+  ProcessorSpecificBlockArchTypeRiscVRV64  = 0x07,
+  ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08
+} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE;
+
+///
+/// Processor Specific Block is the standard container of processor-specific data.
+///
+typedef struct {
+  UINT8                              Length;
+  UINT8                              ProcessorArchType;
+  ///
+  /// Below followed by Processor-specific data
+  ///
+  ///
+} PROCESSOR_SPECIFIC_BLOCK;
+
+///
+/// Processor Additional Information(Type 44).
+///
+/// The information in this structure defines the processor additional information in case 
+/// SMBIOS type 4 is not sufficient to describe processor characteristics.
+/// The SMBIOS type 44 structure has a reference handle field to link back to the related 
+/// SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structures linked to the 
+/// same SMBIOS type 4 structure. For example, when cores are not identical in a processor, 
+/// SMBIOS type 44 structures describe different core-specific information.
+/// 
+/// SMBIOS type 44 defines the standard header for the processor-specific block, while the
+/// contents of processor-specific data are maintained by processor 
+/// architecture workgroups or vendors in separate documents.
+///
+typedef struct {
+  SMBIOS_STRUCTURE                  Hdr;
+  SMBIOS_HANDLE                     RefHandle;                 ///< This field refer to associated SMBIOS type 4
+  ///
+  /// Below followed by Processor-specific block
+  ///
+  PROCESSOR_SPECIFIC_BLOCK          ProcessorSpecificBlock;
+} SMBIOS_TABLE_TYPE44;
+
 ///
 /// Inactive (Type 126)
 ///
@@ -2420,6 +2489,7 @@ typedef union {
   SMBIOS_TABLE_TYPE40   *Type40;
   SMBIOS_TABLE_TYPE41   *Type41;
   SMBIOS_TABLE_TYPE42   *Type42;
+  SMBIOS_TABLE_TYPE44   *Type44;
   SMBIOS_TABLE_TYPE126  *Type126;
   SMBIOS_TABLE_TYPE127  *Type127;
   UINT8                 *Raw;
-- 
2.7.4