* [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform
@ 2019-08-27 6:00 Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 2/14]: BaseTools/Conf: Update build flags for RISC-V RV64 Abner Chang
` (12 more replies)
0 siblings, 13 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Elf64Convert.c
- Relocation process to hadnle below opcodes,
* PCRELHI20
* PCRELLO12
* ADD32
* SUB32
GenFvInternalLib.c
- This atches jump instrcution at the position of first instrcution fetched by RISC-V processor after Zeroth Stage Boot Loader (ZSBL).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 311 ++++++++++++----------------
BaseTools/Source/C/GenFw/Elf64Convert.c | 68 ++++++
2 files changed, 197 insertions(+), 182 deletions(-)
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 01da00c..92abb7c 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -1956,157 +1956,6 @@ Returns:
return EFI_UNSUPPORTED;
}
-EFI_STATUS
-UpdateRiscvResetVectorIfNeeded (
- MEMORY_FILE *FvImage,
- FV_INFO *FvInfo,
- EFI_FFS_FILE_HEADER *VtfFileImage
- )
-/*++
-
-Routine Description:
- This parses the FV looking for SEC and patches that address into the
- beginning of the FV header.
-
- For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
-
-Arguments:
- FvImage Memory file for the FV memory image/
- FvInfo Information read from INF file.
- VtfFileImage Instance of VTF file.
-
-Returns:
-
- EFI_SUCCESS Function Completed successfully.
- EFI_ABORTED Error encountered.
- EFI_INVALID_PARAMETER A required parameter was NULL.
- EFI_NOT_FOUND PEI Core file not found.
-
---*/
-{
- EFI_FFS_FILE_HEADER *PeiCoreFile;
- EFI_FFS_FILE_HEADER *SecCoreFile;
- EFI_STATUS Status;
- EFI_FILE_SECTION_POINTER Pe32Section;
- UINT32 EntryPoint;
- UINT32 BaseOfCode;
- UINT16 MachineType;
- EFI_PHYSICAL_ADDRESS PeiCorePhysicalAddress;
- EFI_PHYSICAL_ADDRESS SecCorePhysicalAddress;
- EFI_PHYSICAL_ADDRESS TrapAddress;
-
- //
- // Verify input parameters
- //
- if (FvImage == NULL || FvInfo == NULL) {
- Error (NULL, 0, 3000, "Invalid", "FvImage or FvInfo is NULL");
- return EFI_INVALID_PARAMETER;
- }
- //
- // Initialize FV library
- //
- InitializeFvLib (FvImage->FileImage, FvInfo->Size);
-
- //
- // Find the Sec Core
- //
- Status = GetFileByType (EFI_FV_FILETYPE_SECURITY_CORE, 1, &SecCoreFile);
- if (EFI_ERROR (Status) || SecCoreFile == NULL) {
- //
- // Maybe hardware does SEC job and we only have PEI Core?
- //
-
- //
- // Find the PEI Core. It may not exist if SEC loads DXE core directly
- //
- PeiCorePhysicalAddress = 0;
- Status = GetFileByType (EFI_FV_FILETYPE_PEI_CORE, 1, &PeiCoreFile);
- if (!EFI_ERROR(Status) && PeiCoreFile != NULL) {
- //
- // PEI Core found, now find PE32 or TE section
- //
- Status = GetSectionByType (PeiCoreFile, EFI_SECTION_PE32, 1, &Pe32Section);
- if (Status == EFI_NOT_FOUND) {
- Status = GetSectionByType (PeiCoreFile, EFI_SECTION_TE, 1, &Pe32Section);
- }
-
- if (EFI_ERROR (Status)) {
- Error (NULL, 0, 3000, "Invalid", "could not find either a PE32 or a TE section in PEI core file!");
- return EFI_ABORTED;
- }
-
- Status = GetPe32Info (
- (VOID *) ((UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader)),
- &EntryPoint,
- &BaseOfCode,
- &MachineType
- );
-
- if (EFI_ERROR (Status)) {
- Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for the PEI core!");
- return EFI_ABORTED;
- }
- //
- // Physical address is FV base + offset of PE32 + offset of the entry point
- //
- PeiCorePhysicalAddress = FvInfo->BaseAddress;
- PeiCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN) FvImage->FileImage;
- PeiCorePhysicalAddress += EntryPoint;
- DebugMsg (NULL, 0, 9, "PeiCore physical entry point address", "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
- RiscvPatchVtf (VtfFileImage, (UINT32)PeiCorePhysicalAddress);
- }
- return EFI_SUCCESS;
- }
-
- //
- // Sec Core found, now find PE32 section
- //
- Status = GetSectionByType (SecCoreFile, EFI_SECTION_PE32, 1, &Pe32Section);
- if (Status == EFI_NOT_FOUND) {
- Status = GetSectionByType (SecCoreFile, EFI_SECTION_TE, 1, &Pe32Section);
- }
-
- if (EFI_ERROR (Status)) {
- Error (NULL, 0, 3000, "Invalid", "could not find a PE32 section in the SEC core file.");
- return EFI_ABORTED;
- }
-
- Status = GetPe32Info (
- (VOID *) ((UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader)),
- &EntryPoint,
- &BaseOfCode,
- &MachineType
- );
- if (EFI_ERROR (Status)) {
- Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for the SEC core.");
- return EFI_ABORTED;
- }
-
- if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) && (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
- //
- // If SEC is not RISC-V we have nothing to do
- //
- return EFI_SUCCESS;
- }
-
- //
- // Physical address is FV base + offset of PE32 + offset of the entry point
- //
- SecCorePhysicalAddress = FvInfo->BaseAddress;
- SecCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN) FvImage->FileImage;
- SecCorePhysicalAddress += EntryPoint;
- DebugMsg (NULL, 0, 0x14, "SecCore physical entry point address", "Address = 0x%llX", (unsigned long long) SecCorePhysicalAddress);
- RiscvPatchVtf (VtfFileImage, (UINT32)SecCorePhysicalAddress);
- //
- // Update RISC-V trap handler.
- //
- TrapAddress = (UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader) + EntryPoint;
- TrapAddress -= 40;
- RiscvPatchVtfTrapHandler (VtfFileImage, TrapAddress);
-
- DebugMsg (NULL, 0, 9, "Update Reset vector in FV Header", NULL);
- return EFI_SUCCESS;
-}
EFI_STATUS
FindCorePeSection(
@@ -2581,6 +2430,106 @@ Returns:
}
EFI_STATUS
+UpdateRiscvResetVectorIfNeeded (
+ MEMORY_FILE *FvImage,
+ FV_INFO *FvInfo
+ )
+/*++
+
+Routine Description:
+ This parses the FV looking for SEC and patches that address into the
+ beginning of the FV header.
+
+ For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
+
+Arguments:
+ FvImage Memory file for the FV memory image/
+ FvInfo Information read from INF file.
+
+Returns:
+
+ EFI_SUCCESS Function Completed successfully.
+ EFI_ABORTED Error encountered.
+ EFI_INVALID_PARAMETER A required parameter was NULL.
+ EFI_NOT_FOUND PEI Core file not found.
+
+--*/
+{
+ EFI_STATUS Status;
+ UINT16 MachineType;
+ EFI_FILE_SECTION_POINTER SecPe32;
+ EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
+
+ UINT32 bSecCore;
+ UINT32 tmp;
+
+
+ //
+ // Verify input parameters
+ //
+ if (FvImage == NULL || FvInfo == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Initialize FV library
+ //
+ InitializeFvLib (FvImage->FileImage, FvInfo->Size);
+
+ //
+ // Find the Sec Core
+ //
+ Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
+ if(EFI_ERROR(Status)) {
+ printf("skip because Secutiry Core not found\n");
+ return EFI_SUCCESS;
+ }
+
+ DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
+
+ Status = GetCoreMachineType(SecPe32, &MachineType);
+ if(EFI_ERROR(Status)) {
+ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type for SEC core.");
+ return EFI_ABORTED;
+ }
+
+ if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) && (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
+ Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because Machine type is not RiscV.");
+ return EFI_ABORTED;
+ }
+
+ Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe32, &SecCoreEntryAddress);
+ if(EFI_ERROR(Status)) {
+ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point address for SEC Core.");
+ return EFI_ABORTED;
+ }
+
+ VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned long long) SecCoreEntryAddress);
+ VerboseMsg("BaseAddress = 0x%llX", (unsigned long long) FvInfo->BaseAddress);
+ bSecCore = (SecCoreEntryAddress - FvInfo->BaseAddress);
+ VerboseMsg("offset = 0x%llX", bSecCore);
+
+ if(bSecCore > 0x0fffff) {
+ Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of start of the FV");
+ return EFI_ABORTED;
+ }
+
+ tmp = bSecCore;
+ bSecCore = 0;
+ //J-type
+ bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
+ bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
+ bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
+ bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
+ bSecCore |= 0x6F; //JAL opcode
+
+ memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
+
+ return EFI_SUCCESS;
+}
+
+
+
+EFI_STATUS
GetPe32Info (
IN UINT8 *Pe32,
OUT UINT32 *EntryPoint,
@@ -3037,7 +2986,6 @@ Returns:
FvHeader->Checksum = 0;
FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
}
-
//
// Add files to FV
//
@@ -3069,39 +3017,22 @@ Returns:
goto Finish;
}
- if (mRiscV) {
+ if (!mArm && !mRiscV) {
//
- // Update RISCV reset vector.
+ // Update reset vector (SALE_ENTRY for IPF)
+ // Now for IA32 and IA64 platform, the fv which has bsf file must have the
+ // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to update the
+ // reset vector. If the PEI Core is found, the VTF file will probably get
+ // corrupted by updating the entry point.
//
- DebugMsg (NULL, 0, INFO_LOG_LEVEL, "Update RISCV reset vector", NULL);
- Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile, &mFvDataInfo, VtfFileImage);
- if (EFI_ERROR (Status)) {
- Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for RISC-V.");
+ if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) == FV_IMAGES_TOP_ADDRESS) {
+ Status = UpdateResetVector (&FvImageMemoryFile, &mFvDataInfo, VtfFileImage);
+ if (EFI_ERROR(Status)) {
+ Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector.");
goto Finish;
- }
- //
- // Update Checksum for FvHeader
- //
- FvHeader->Checksum = 0;
- FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
- } else {
- if (!mArm) {
- //
- // Update reset vector (SALE_ENTRY for IPF)
- // Now for IA32 and IA64 platform, the fv which has bsf file must have the
- // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to update the
- // reset vector. If the PEI Core is found, the VTF file will probably get
- // corrupted by updating the entry point.
- //
- if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) == FV_IMAGES_TOP_ADDRESS) {
- Status = UpdateResetVector (&FvImageMemoryFile, &mFvDataInfo, VtfFileImage);
- if (EFI_ERROR(Status)) {
- Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector.");
- goto Finish;
- }
- DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
- }
}
+ DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
+ }
}
}
@@ -3119,6 +3050,22 @@ Returns:
FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
}
+ if (mRiscV) {
+ //
+ // Update RISCV reset vector.
+ //
+ Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile, &mFvDataInfo);
+ if (EFI_ERROR (Status)) {
+ Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for RISC-V.");
+ goto Finish;
+ }
+ //
+ // Update Checksum for FvHeader
+ //
+ FvHeader->Checksum = 0;
+ FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
+ }
+
//
// Update FV Alignment attribute to the largest alignment of all the FFS files in the FV
//
@@ -3853,7 +3800,7 @@ Returns:
ImageContext.DestinationAddress = NewPe32BaseAddress;
Status = PeCoffLoaderRelocateImage (&ImageContext);
if (EFI_ERROR (Status)) {
- Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of %s", FileName);
+ Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of %s Status=%d", FileName, Status);
free ((VOID *) MemoryImagePointer);
return Status;
}
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 4857485..77b4d53 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -946,8 +946,60 @@ WriteSections64 (
RiscvSymSecIndex = 0;
break;
+ case R_RISCV_PCREL_HI20:
+ RiscvHi20Targ = Targ;
+ RiscvHi20Sym = SymShdr;
+ RiscvSymSecIndex = Sym->st_shndx;
+
+ Value = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
+ printf("PCREL_HI20 Sym:[%s] value:0x%x SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
+ break;
+ case R_RISCV_PCREL_LO12_I:
+ if (RiscvHi20Targ != NULL && RiscvHi20Sym != NULL && RiscvSymSecIndex != 0) {
+ int i;
+ Value2 = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
+ Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+ if(Value & (RISCV_IMM_REACH/2)) {
+ Value |= ~(RISCV_IMM_REACH-1);
+ }
+ printf("PCREL_LO12_I Sym:[%s] value:0x%x SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
+ Value = Value - RiscvHi20Sym->sh_addr + mCoffSectionsOffset[RiscvSymSecIndex];
+ if(-2048 > (INT32)Value) {
+ i = (-Value / 4096);
+ //Error (NULL, 0, 3000, "Invalid", "WriteSections64(): PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
+ printf("WriteSections64(): PCREL_LO12_I relocation out of range. Value:%d Value2:%d i=%d\n", Value, Value2, i);
+ Value2 -= i;
+ Value += 4096 * i;
+ if(-2048 > (INT32)Value) {
+ Value2 -= 1;
+ Value += 4096;
+ }
+ }
+ else if( 2047 < (INT32)Value) {
+ i = (Value / 4096);
+ //Error (NULL, 0, 3000, "Invalid", "WriteSections64(): PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
+ printf("WriteSections64(): PCREL_LO12_I relocation out of range. Value:%d Value2:%d i=%d\n", Value, Value2, i);
+ Value2 += i;
+ Value -= 4096 * i;
+ if(2047 < (INT32)Value) {
+ Value2 += 1;
+ Value -= 4096;
+ }
+ }
+
+ *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+ *(UINT32 *)RiscvHi20Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)RiscvHi20Targ, 0, 12));
+ printf("PCREL_LO12_I Sym:[%s] relocated value:0x%x(%d) value2:0x%x(%d) SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym), Value, Value, Value2, Value2, SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
+ }
+ RiscvHi20Sym = NULL;
+ RiscvHi20Targ = NULL;
+ RiscvSymSecIndex = 0;
+ break;
+
case R_RISCV_ADD64:
case R_RISCV_SUB64:
+ case R_RISCV_ADD32:
+ case R_RISCV_SUB32:
case R_RISCV_BRANCH:
case R_RISCV_JAL:
case R_RISCV_GPREL_I:
@@ -1120,6 +1172,20 @@ WriteRelocations64 (
EFI_IMAGE_REL_BASED_ABSOLUTE);
break;
+ case R_RISCV_ADD32:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_SUB32:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
case R_RISCV_BRANCH:
CoffAddFixup(
(UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
@@ -1145,6 +1211,8 @@ WriteRelocations64 (
case R_RISCV_SET8:
case R_RISCV_SET16:
case R_RISCV_SET32:
+ case R_RISCV_PCREL_HI20:
+ case R_RISCV_PCREL_LO12_I:
break;
default:
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 2/14]: BaseTools/Conf: Update build flags for RISC-V RV64
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 4/14]: MdePkg/Include: Update SmBios header file Abner Chang
` (11 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Update build flags for RISC-V RV64 architecture.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
BaseTools/Conf/tools_def.template | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 682d8b3..a6f45f4 100644
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -4470,18 +4470,18 @@ DEFINE GCC53RISCV_RISCV64_DLINK_FLAGS = DEF(GCC53RISCV_RISCV32_RISCV64_DLI
DEFINE GCC53RISCV_RISCV64_DLINK2_FLAGS = DEF(GCC49_X64_DLINK2_FLAGS)
DEFINE GCC53RISCV_ASM_FLAGS = DEF(GCC49_ASM_FLAGS)
-DEFINE GCC711RISCV_RISCV32_ARCH = rv32imafd
-DEFINE GCC711RISCV_RISCV64_ARCH = rv64imafd
+DEFINE GCC711RISCV_RISCV32_ARCH = rv32imafdc
+DEFINE GCC711RISCV_RISCV64_ARCH = rv64imafdc
DEFINE GCC711RISCV_CC_FLAGS_WARNING_DISABLE = -Wno-tautological-compare -Wno-pointer-compare
DEFINE GCC711RISCV_RISCV32_CC_FLAGS = DEF(GCC44_ALL_CC_FLAGS) DEF(GCC711RISCV_CC_FLAGS_WARNING_DISABLE) -march=DEF(GCC711RISCV_RISCV32_ARCH) -malign-double -fno-stack-protector -D EFI32 -fno-asynchronous-unwind-tables -Wno-address -Wno-unused-but-set-variable -fpack-struct=8
-DEFINE GCC711RISCV_RISCV64_CC_FLAGS = DEF(GCC44_ALL_CC_FLAGS) DEF(GCC711RISCV_CC_FLAGS_WARNING_DISABLE) -march=DEF(GCC711RISCV_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno-asynchronous-unwind-tables -Wno-unused-but-set-variable -fpack-struct=8
+DEFINE GCC711RISCV_RISCV64_CC_FLAGS = DEF(GCC44_ALL_CC_FLAGS) DEF(GCC711RISCV_CC_FLAGS_WARNING_DISABLE) -march=DEF(GCC711RISCV_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno-asynchronous-unwind-tables -Wno-unused-but-set-variable -fpack-struct=8 -mcmodel=medany -mabi=lp64
DEFINE GCC711RISCV_RISCV32_RISCV64_DLINK_COMMON = -nostdlib -n -q --gc-sections -z common-page-size=0x40
DEFINE GCC711RISCV_RISCV32_RISCV64_ASLDLINK_FLAGS = DEF(GCC53RISCV_RISCV32_RISCV64_DLINK_COMMON) --entry ReferenceAcpiTable -u ReferenceAcpiTable
DEFINE GCC711RISCV_RISCV32_RISCV64_DLINK_FLAGS = DEF(GCC53RISCV_RISCV32_RISCV64_DLINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
DEFINE GCC711RISCV_RISCV32_DLINK2_FLAGS = DEF(GCC49_IA32_DLINK2_FLAGS)
DEFINE GCC711RISCV_RISCV64_DLINK_FLAGS = DEF(GCC53RISCV_RISCV32_RISCV64_DLINK_FLAGS) -melf64lriscv --oformat=elf64-littleriscv --no-relax
DEFINE GCC711RISCV_RISCV64_DLINK2_FLAGS = DEF(GCC49_X64_DLINK2_FLAGS)
-DEFINE GCC711RISCV_ASM_FLAGS = DEF(GCC49_ASM_FLAGS)
+DEFINE GCC711RISCV_ASM_FLAGS = DEF(GCC49_ASM_FLAGS) -march=DEF(GCC711RISCV_RISCV64_ARCH) -mcmodel=medany -mabi=lp64
####################################################################################
#
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 4/14]: MdePkg/Include: Update SmBios header file.
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 2/14]: BaseTools/Conf: Update build flags for RISC-V RV64 Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 5/14]: RiscVPkg/Include: Add/Update header files of RISC-V CPU package Abner Chang
` (10 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Update SmBios header file to conform with SMBIOS v3.3.0.
The major update is to add definitions of SMBIOS Type 44h record.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdePkg/Include/IndustryStandard/SmBios.h | 76 ++++++++++++++++++++++++++++++--
1 file changed, 73 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h
index c66422f..fd91a79 100644
--- a/MdePkg/Include/IndustryStandard/SmBios.h
+++ b/MdePkg/Include/IndustryStandard/SmBios.h
@@ -2,7 +2,7 @@
Industry Standard Definitions of SMBIOS Table Specification v3.0.0.
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
+(C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development LP<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
@@ -52,7 +52,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF
//
-// SMBIOS type macros which is according to SMBIOS 2.7 specification.
+// SMBIOS type macros which is according to SMBIOS 3.3.0 specification.
//
#define SMBIOS_TYPE_BIOS_INFORMATION 0
#define SMBIOS_TYPE_SYSTEM_INFORMATION 1
@@ -97,6 +97,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define SMBIOS_TYPE_ADDITIONAL_INFORMATION 40
#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41
#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42
+#define SMBIOS_TYPE_TPM_DEVICE 43
+#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44
///
/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.
@@ -696,7 +698,10 @@ typedef enum {
ProcessorFamilyMII = 0x012E,
ProcessorFamilyWinChip = 0x0140,
ProcessorFamilyDSP = 0x015E,
- ProcessorFamilyVideoProcessor = 0x01F4
+ ProcessorFamilyVideoProcessor = 0x01F4,
+ ProcessorFamilyRiscvRV32 = 0x0200, ///< SMBIOS spec 3.3.0 added
+ ProcessorFamilyRiscVRV64 = 0x0201, ///< SMBIOS spec 3.3.0 added
+ ProcessorFamilyRiscVRV128 = 0x0202 ///< SMBIOS spec 3.3.0 added
} PROCESSOR_FAMILY2_DATA;
///
@@ -814,6 +819,19 @@ typedef struct {
} PROCESSOR_FEATURE_FLAGS;
typedef struct {
+ UINT32 ProcessorReserved1 :1;
+ UINT32 ProcessorUnknown :1;
+ UINT32 Processor64BitCapble :1;
+ UINT32 ProcessorMultiCore :1;
+ UINT32 ProcessorHardwareThread :1;
+ UINT32 ProcessorExecuteProtection :1;
+ UINT32 ProcessorEnhancedVirtulization :1;
+ UINT32 ProcessorPowerPerformanceCtrl :1;
+ UINT32 Processor128bitCapble :1;
+ UINT32 ProcessorReserved2 :7;
+} PROCESSOR_CHARACTERISTIC_FLAGS;
+
+typedef struct {
PROCESSOR_SIGNATURE Signature;
PROCESSOR_FEATURE_FLAGS FeatureFlags;
} PROCESSOR_ID_DATA;
@@ -2358,6 +2376,57 @@ typedef struct {
UINT8 MCHostInterfaceData[1]; ///< This field has a minimum of four bytes
} SMBIOS_TABLE_TYPE42;
+
+///
+/// Processor Specific Block - Processor Architecture Type
+///
+typedef enum{
+ ProcessorSpecificBlockArchTypeReserved = 0x00,
+ ProcessorSpecificBlockArchTypeIa32 = 0x01,
+ ProcessorSpecificBlockArchTypeX64 = 0x02,
+ ProcessorSpecificBlockArchTypeItanium = 0x03,
+ ProcessorSpecificBlockArchTypeAarch32 = 0x04,
+ ProcessorSpecificBlockArchTypeAarch64 = 0x05,
+ ProcessorSpecificBlockArchTypeRiscVRV32 = 0x06,
+ ProcessorSpecificBlockArchTypeRiscVRV64 = 0x07,
+ ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08
+} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE;
+
+///
+/// Processor Specific Block is the standard container of processor-specific data.
+///
+typedef struct {
+ UINT8 Length;
+ UINT8 ProcessorArchType;
+ ///
+ /// Below followed by Processor-specific data
+ ///
+ ///
+} PROCESSOR_SPECIFIC_BLOCK;
+
+///
+/// Processor Additional Information(Type 44).
+///
+/// The information in this structure defines the processor additional information in case
+/// SMBIOS type 4 is not sufficient to describe processor characteristics.
+/// The SMBIOS type 44 structure has a reference handle field to link back to the related
+/// SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structures linked to the
+/// same SMBIOS type 4 structure. For example, when cores are not identical in a processor,
+/// SMBIOS type 44 structures describe different core-specific information.
+///
+/// SMBIOS type 44 defines the standard header for the processor-specific block, while the
+/// contents of processor-specific data are maintained by processor
+/// architecture workgroups or vendors in separate documents.
+///
+typedef struct {
+ SMBIOS_STRUCTURE Hdr;
+ SMBIOS_HANDLE RefHandle; ///< This field refer to associated SMBIOS type 4
+ ///
+ /// Below followed by Processor-specific block
+ ///
+ PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock;
+} SMBIOS_TABLE_TYPE44;
+
///
/// Inactive (Type 126)
///
@@ -2420,6 +2489,7 @@ typedef union {
SMBIOS_TABLE_TYPE40 *Type40;
SMBIOS_TABLE_TYPE41 *Type41;
SMBIOS_TABLE_TYPE42 *Type42;
+ SMBIOS_TABLE_TYPE44 *Type44;
SMBIOS_TABLE_TYPE126 *Type126;
SMBIOS_TABLE_TYPE127 *Type127;
UINT8 *Raw;
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 5/14]: RiscVPkg/Include: Add/Update header files of RISC-V CPU package
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 2/14]: BaseTools/Conf: Update build flags for RISC-V RV64 Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 4/14]: MdePkg/Include: Update SmBios header file Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 6/14]: RiscVPkg/opesbi: Add opensbi-HOWTO.txt Abner Chang
` (9 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
RiscV.h
- Update RiscV.h to conform with RISC-V Privilege Spec v1.10.
sbi.h
sbi_bits.h
sbi_types.h
- Add definitions for RISC-V OpenSBI EDK2 port.
RealTimeClockLib.h
- Header file of platform level Real Time Clock library.
SbiFirmwareContext.h
- Header file of RISC-V OpenSBI Firmware Context of UEFI EDK2 implementation.
RiscVPlatformTempMemoryInitLib.h
- Header file of temporary memory functions.
RiscVPlatformDxeIplLib
- Header file for supporting platform level DXE IPL on RISC-V platform.
ProcessorSpecificDataHob.h
- Header file of RISC-V processor specific information data hob. This information is built up by platform and consumed by RISC-V generic SMBIOS DXE driver for building up SMBIOS records.
SmbiosPrcessorSpecificData.h
- Header file of RISC-V processor specific information for SMBIOS type 44 record.
RiscVCpuLib.h
- Add defitions of generic CSR functions
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/Include/Library/RealTimeClockLib.h | 136 +++++++++++++++++++++
RiscVPkg/Include/Library/RiscVCpuLib.h | 37 +++++-
RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 47 +++++++
.../Library/RiscVPlatformTempMemoryInitLib.h | 8 +-
RiscVPkg/Include/ProcessorSpecificDataHob.h | 99 +++++++++++++++
RiscVPkg/Include/RiscV.h | 60 +++++++--
RiscVPkg/Include/SmbiosProcessorSpecificData.h | 64 ++++++++++
RiscVPkg/Include/sbi/SbiFirmwareContext.h | 44 +++++++
RiscVPkg/Include/sbi/sbi.h | 103 ++++++++++++++++
RiscVPkg/Include/sbi/sbi_bits.h | 23 ++++
RiscVPkg/Include/sbi/sbi_types.h | 24 ++++
11 files changed, 627 insertions(+), 18 deletions(-)
create mode 100644 RiscVPkg/Include/Library/RealTimeClockLib.h
create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h
create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h
create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h
create mode 100644 RiscVPkg/Include/sbi/sbi.h
create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h
create mode 100644 RiscVPkg/Include/sbi/sbi_types.h
diff --git a/RiscVPkg/Include/Library/RealTimeClockLib.h b/RiscVPkg/Include/Library/RealTimeClockLib.h
new file mode 100644
index 0000000..2815b44
--- /dev/null
+++ b/RiscVPkg/Include/Library/RealTimeClockLib.h
@@ -0,0 +1,136 @@
+/** @file
+ Implement EFI RealTimeClock runtime services via RISC-V platform Lib.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __REAL_TIME_CLOCK_LIB__
+#define __REAL_TIME_CLOCK_LIB__
+
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ );
+
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ );
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ );
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ );
+
+
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+
+#endif
+
diff --git a/RiscVPkg/Include/Library/RiscVCpuLib.h b/RiscVPkg/Include/Library/RiscVCpuLib.h
index b4323bf..7a8e75a 100644
--- a/RiscVPkg/Include/Library/RiscVCpuLib.h
+++ b/RiscVPkg/Include/Library/RiscVCpuLib.h
@@ -1,7 +1,7 @@
/** @file
RISC-V package definitions.
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -35,9 +35,40 @@ RiscVGetScratch (VOID);
UINT32
RiscVGetTrapCause (VOID);
-UINT32
+UINT64
RiscVReadMachineTimer (VOID);
VOID
-RiscVSetMachineTimerCmp (UINT32);
+RiscVSetMachineTimerCmp (UINT64);
+
+UINT64
+RiscVReadMachineTimerCmp(VOID);
+
+UINT64
+RiscVReadMachineIE(VOID);
+
+UINT64
+RiscVReadMachineIP(VOID);
+
+UINT64
+RiscVReadMachineStatus(VOID);
+
+VOID
+RiscVWriteMachineStatus(UINT64);
+
+UINT64
+RiscVReadMachineTvec(VOID);
+
+UINT64
+RiscVReadMisa (VOID);
+
+UINT64
+RiscVReadMVendorId (VOID);
+
+UINT64
+RiscVReadMArchId (VOID);
+
+UINT64
+RiscVReadMImplId (VOID);
+
#endif
diff --git a/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
new file mode 100644
index 0000000..69ad310
--- /dev/null
+++ b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
@@ -0,0 +1,47 @@
+/** @file
+ Header file of RISC-V platform DXE IPL
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP.All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#ifndef __RISC_V_PLATFORM_DXEIPL_H__
+#define __RISC_V_PLATFORM_DXEIPL_H__
+
+typedef struct {
+ VOID *TopOfStack;
+ VOID *BaseOfStack;
+ EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint;
+ EFI_PEI_HOB_POINTERS HobList;
+} OPENSBI_SWITCH_MODE_CONTEXT;
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ );
+#endif
+
diff --git a/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h b/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
index 0037e44..0ed3a6e 100644
--- a/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
+++ b/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
@@ -1,7 +1,7 @@
/** @file
RISC-V package definitions.
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -17,7 +17,7 @@
#include "RiscV.h"
-VOID
-EFIAPI
-RiscVPlatformTemporaryMemInit (VOID);
+VOID EFIAPI RiscVPlatformTemporaryMemInit (VOID);
+UINT32 EFIAPI RiscVPlatformTemporaryMemSize(VOID);
+UINT32 EFIAPI RiscVPlatformTemporaryMemBase(VOID);
#endif
diff --git a/RiscVPkg/Include/ProcessorSpecificDataHob.h b/RiscVPkg/Include/ProcessorSpecificDataHob.h
new file mode 100644
index 0000000..4512277
--- /dev/null
+++ b/RiscVPkg/Include/ProcessorSpecificDataHob.h
@@ -0,0 +1,99 @@
+/** @file
+ Definition of Processor Specific Data HOB.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H__
+#define __RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H__
+
+#include <IndustryStandard/SmBios.h>
+
+#define TO_BE_FILLED 0
+#define TO_BE_FILLED_BY_VENDOR 0
+#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
+#define TO_BE_FILLED_BY_CODE 0
+
+#pragma pack(1)
+
+///
+/// RISC-V processor specific data HOB
+///
+typedef struct {
+ EFI_GUID ParentPrcessorGuid;
+ UINTN ParentProcessorUid;
+ EFI_GUID CoreGuid;
+ VOID *Context; // The additional information of this core which
+ // built in PEI phase and carried to DXE phase.
+ // The content is pocessor or platform specific.
+ SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
+} RISC_V_PROCESSOR_SPECIFIC_DATA_HOB;
+
+///
+/// RISC-V SMBIOS type 4 (Processor) GUID data HOB
+///
+typedef struct {
+ EFI_GUID PrcessorGuid;
+ UINTN ProcessorUid;
+ SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
+} RISC_V_PROCESSOR_TYPE4_DATA_HOB;
+
+#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
+
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
+
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
+#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+///
+/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
+///
+typedef struct {
+ EFI_GUID PrcessorGuid;
+ UINTN ProcessorUid;
+ SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
+} RISC_V_PROCESSOR_TYPE7_DATA_HOB;
+
+///
+/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
+///
+typedef struct {
+ RISC_V_PROCESSOR_TYPE4_DATA_HOB *Processor;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCache;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1DataCache;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2Cache;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *L3Cache;
+} RISC_V_PROCESSOR_SMBIOS_DATA_HOB;
+
+#pragma pack()
+
+#endif
diff --git a/RiscVPkg/Include/RiscV.h b/RiscVPkg/Include/RiscV.h
index e9612cb..f894429 100644
--- a/RiscVPkg/Include/RiscV.h
+++ b/RiscVPkg/Include/RiscV.h
@@ -1,7 +1,7 @@
/** @file
RISC-V package definitions.
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -24,29 +24,59 @@
#else
#endif
+#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
+#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1)
+#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2)
+#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3)
+#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
+#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5)
+#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6)
+#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
+#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8)
+#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9)
+#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
+#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11)
+#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12)
+#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13)
+#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
+#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15)
+#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16)
+#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
+#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18)
+#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19)
+#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20)
+#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
+#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
+#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23)
+#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
+#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
+
//
// RISC-V CSR definitions.
//
//
-// Machine Trap Setup.
+// Machine information
//
-#define RISCV_CSR_MACHINE_MCPUID 0xF00
-#define RISCV_CSR_MACHINE_MIMPID 0xF01
-#define RISCV_CSR_MACHINE_MHARTID 0xF10
+#define RISCV_CSR_MACHINE_MVENDORID 0xF11
+#define RISCV_CSR_MACHINE_MARCHID 0xF12
+#define RISCV_CSR_MACHINE_MIMPID 0xF13
+#define RISCV_CSR_MACHINE_HARRID 0xF14
//
// Machine Trap Setup.
//
#define RISCV_CSR_MACHINE_MSTATUS 0x300
-#define RISCV_CSR_MACHINE_MTVEC 0x301
-#define RISCV_CSR_MACHINE_MTDELEG 0x302
+#define RISCV_CSR_MACHINE_MISA 0x301
+#define RISCV_CSR_MACHINE_MEDELEG 0x302
+#define RISCV_CSR_MACHINE_MIDELEG 0x303
#define RISCV_CSR_MACHINE_MIE 0x304
-#define RISCV_CSR_MACHINE_MTIMECMP 0x321
- #define RISCV_TIMER_COMPARE_BITS 32
+#define RISCV_CSR_MACHINE_MTVEC 0x305
+
+#define RISCV_TIMER_COMPARE_BITS 32
//
// Machine Timer and Counter.
//
-#define RISCV_CSR_MACHINE_MTIME 0x701
-#define RISCV_CSR_MACHINE_MTIMEH 0x741
+//#define RISCV_CSR_MACHINE_MTIME 0x701
+//#define RISCV_CSR_MACHINE_MTIMEH 0x741
//
// Machine Trap Handling.
//
@@ -78,6 +108,14 @@
#define RISCV_CSR_MTOHOST 0x780
#define RISCV_CSR_MFROMHOST 0x781
+//
+// Structure for 128-bit value
+//
+typedef struct {
+ UINT64 Value64_L;
+ UINT64 Value64_H;
+} RISCV_UINT128;
+
#define RISCV_MACHINE_CONTEXT_SIZE 0x1000
typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT;
diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
new file mode 100644
index 0000000..8669b37
--- /dev/null
+++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
@@ -0,0 +1,64 @@
+/** @file
+ Industry Standard Definitions of RISC-V Processor Specific data defined in
+ below link for complaiant with SMBIOS Table Specification v3.3.0.
+ https://github.com/riscv/riscv-smbios
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H__
+#define __SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H__
+
+#include <IndustryStandard/SmBios.h>
+
+#include <RiscV.h>
+
+#pragma pack(1)
+
+typedef enum{
+ RegisterUnsupported = 0x00,
+ RegisterLen32 = 0x01,
+ RegisterLen64 = 0x02,
+ RegisterLen128 = 0x03
+} RISC_V_REGISTER_LENGTH;
+
+#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100
+
+#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0)
+#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)
+#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)
+#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)
+
+///
+/// RISC-V processor specific data for SMBIOS type 44
+///
+typedef struct {
+ UINT16 Revision;
+ UINT8 Length;
+ RISCV_UINT128 HartId;
+ UINT8 BootHartId;
+ RISCV_UINT128 MachineVendorId;
+ RISCV_UINT128 MachineArchId;
+ RISCV_UINT128 MachineImplId;
+ UINT32 InstSetSupported;
+ UINT8 PrivilegeModeSupported;
+ RISCV_UINT128 MModeExcepDelegation;
+ RISCV_UINT128 MModeInterruptDelegation;
+ UINT8 HartXlen;
+ UINT8 MachineModeXlen;
+ UINT8 Reserved;
+ UINT8 SupervisorModeXlen;
+ UINT8 UserModeXlen;
+} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;
+
+#pragma pack()
+#endif
+
diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
new file mode 100644
index 0000000..eedaa44
--- /dev/null
+++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
@@ -0,0 +1,44 @@
+/** @file
+ RISC-V OpesbSBI Platform Firmware context definition
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SBI_FIRMWARE_CONTEXT_H__
+#define __SBI_FIRMWARE_CONTEXT_H__
+
+#include <RiscV.h>
+
+#define RISC_V_MAX_HART_SUPPORTED 16
+
+//
+// keep the structure member in 64-bit alignment.
+//
+#pragma pack(push)
+#pragma pack(8)
+
+typedef struct {
+ UINT64 IsaExtensionSupported; // The ISA extension this core supported.
+ RISCV_UINT128 MachineVendorId; // Machine vendor ID
+ RISCV_UINT128 MachineArchId; // Machine Architecture ID
+ RISCV_UINT128 MachineImplId; // Machine Implementation ID
+} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
+
+#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7)
+
+typedef struct {
+ VOID *PeiServiceTable; // PEI Service table
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
+} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
+
+#pragma pack(pop)
+#endif
+
diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h
new file mode 100644
index 0000000..537973b
--- /dev/null
+++ b/RiscVPkg/Include/sbi/sbi.h
@@ -0,0 +1,103 @@
+/** @file
+ SBI inline function calls.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SBI_H__
+#define __SBI_H__
+
+#include <sbi/sbi_types.h>
+#include <sbi/riscv_asm.h>
+
+#define SBI_SET_TIMER 0
+#define SBI_CONSOLE_PUTCHAR 1
+#define SBI_CONSOLE_GETCHAR 2
+#define SBI_CLEAR_IPI 3
+#define SBI_SEND_IPI 4
+#define SBI_REMOTE_FENCE_I 5
+#define SBI_REMOTE_SFENCE_VMA 6
+#define SBI_REMOTE_SFENCE_VMA_ASID 7
+#define SBI_SHUTDOWN 8
+
+
+#define SBI_CALL(which, arg0, arg1, arg2) ({ \
+ register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
+ register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
+ register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
+ register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
+ asm volatile ("ecall" \
+ : "+r" (a0) \
+ : "r" (a1), "r" (a2), "r" (a7) \
+ : "memory"); \
+ a0; \
+})
+
+#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)
+#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)
+#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
+
+static inline void sbi_console_putchar(int ch)
+{
+ SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
+}
+
+static inline int sbi_console_getchar(void)
+{
+ return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
+}
+
+static inline void sbi_set_timer(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+ SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
+#else
+ SBI_CALL_1(SBI_SET_TIMER, stime_value);
+#endif
+}
+
+static inline void sbi_shutdown(void)
+{
+ SBI_CALL_0(SBI_SHUTDOWN);
+}
+
+static inline void sbi_clear_ipi(void)
+{
+ SBI_CALL_0(SBI_CLEAR_IPI);
+}
+
+static inline void sbi_send_ipi(const unsigned long *hart_mask)
+{
+ SBI_CALL_1(SBI_SEND_IPI, hart_mask);
+}
+
+static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
+{
+ SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size)
+{
+ SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+ unsigned long start,
+ unsigned long size,
+ unsigned long asid)
+{
+ SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask);
+}
+
+#endif
\ No newline at end of file
diff --git a/RiscVPkg/Include/sbi/sbi_bits.h b/RiscVPkg/Include/sbi/sbi_bits.h
new file mode 100644
index 0000000..4116ee6
--- /dev/null
+++ b/RiscVPkg/Include/sbi/sbi_bits.h
@@ -0,0 +1,23 @@
+/** @file
+ RISC-V OpesbSBI header file reference.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __EDK2_SBI_BITS_H__
+#define __EDK2_SBI_BITS_H__
+
+#undef MAX
+#undef MIN
+
+#include "../opensbi/include/sbi/sbi_bits.h"
+
+#endif
\ No newline at end of file
diff --git a/RiscVPkg/Include/sbi/sbi_types.h b/RiscVPkg/Include/sbi/sbi_types.h
new file mode 100644
index 0000000..fe877f2
--- /dev/null
+++ b/RiscVPkg/Include/sbi/sbi_types.h
@@ -0,0 +1,24 @@
+/** @file
+ RISC-V OpesbSBI header file reference.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __EDK2_SBI_TYPES_H__
+#define __EDK2_SBI_TYPES_H__
+
+#undef TRUE
+#undef FALSE
+#undef NULL
+
+#include "../opensbi/include/sbi/sbi_types.h"
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 6/14]: RiscVPkg/opesbi: Add opensbi-HOWTO.txt
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
` (2 preceding siblings ...)
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 5/14]: RiscVPkg/Include: Add/Update header files of RISC-V CPU package Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 7/14]: RiscVPkg/RealTimeClockRuntimeDxe: Add RISC-V RTC Runtime Driver Abner Chang
` (8 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Add opensbi-HOWTO.txt for users to build RISC-V platform with RISC-V OpenSBI library.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/opensbi/opensbi-HOWTO.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 RiscVPkg/opensbi/opensbi-HOWTO.txt
diff --git a/RiscVPkg/opensbi/opensbi-HOWTO.txt b/RiscVPkg/opensbi/opensbi-HOWTO.txt
new file mode 100644
index 0000000..aff7a69
--- /dev/null
+++ b/RiscVPkg/opensbi/opensbi-HOWTO.txt
@@ -0,0 +1,17 @@
+================================================================================
+ Instroduction
+================================================================================
+RISC-V Open Source Supervisor Binary Interface (OpenSBI) is an open source
+implementation (Refer to https://github.com/riscv/opensbi) of RISC-V SBI spec
+(Refer to https://github.com/riscv/riscv-sbi-doc), whcih is designed for the
+platform-specific firmwares executing in RISC-V Machine mode (M-mode).
+EDK2 RISC-V port leverage OpenSBI source files and build it into EDK2 RISC-V
+OpenSBI library (RiscVPkg/Library/RiscVOpensbiLib) using edk2 toolchain.
+
+User has to get OpenSBI source code and put it under RiscVPkg/opensbi using below
+command before building RISC-V platform in EDK2 build environment.
+
+Current supported RISC-V OpenSBI version on EDK2 is v0.4
+
+ $ git clone https://github.com/riscv/opensbi
+ $ git checkout tags/v0.4
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 7/14]: RiscVPkg/RealTimeClockRuntimeDxe: Add RISC-V RTC Runtime Driver
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
` (3 preceding siblings ...)
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 6/14]: RiscVPkg/opesbi: Add opensbi-HOWTO.txt Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 8/14]: RiscVPkg/Universal: Remove stale moudles Abner Chang
` (7 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
This is the abstract driver which incorporate with platform level RTC library (RealTimeClockLib) to provide Real Time Clock Architecture Protocol.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RealTimeClockRuntimeDxe/RealTimeClock.c | 157 +++++++++++++++++++++
.../RealTimeClockRuntimeDxe.inf | 44 ++++++
2 files changed, 201 insertions(+)
create mode 100644 RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClock.c
create mode 100644 RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
diff --git a/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClock.c b/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClock.c
new file mode 100644
index 0000000..c3d04e7
--- /dev/null
+++ b/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClock.c
@@ -0,0 +1,157 @@
+/** @file
+ Implementation of EFI RealTimeClock runtime services via platform RTC Lib.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Protocol/RealTimeClock.h>
+
+EFI_HANDLE mHandle = NULL;
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+GetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ return LibGetTime (Time, Capabilities);
+}
+
+
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+SetTime (
+ IN EFI_TIME *Time
+ )
+{
+ return LibSetTime (Time);
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+GetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ return LibGetWakeupTime (Enabled, Pending, Time);
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+SetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ return LibSetWakeupTime (Enabled, Time);
+}
+
+
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeRealTimeClock (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = LibRtcInitialize (ImageHandle, SystemTable);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ SystemTable->RuntimeServices->GetTime = GetTime;
+ SystemTable->RuntimeServices->SetTime = SetTime;
+ SystemTable->RuntimeServices->GetWakeupTime = GetWakeupTime;
+ SystemTable->RuntimeServices->SetWakeupTime = SetWakeupTime;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mHandle,
+ &gEfiRealTimeClockArchProtocolGuid,
+ NULL,
+ NULL
+ );
+
+ return Status;
+}
+
diff --git a/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf b/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
new file mode 100644
index 0000000..afc1bca
--- /dev/null
+++ b/RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
@@ -0,0 +1,44 @@
+#/** @file
+# This driver installs RTC Architecture Protocol
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RealTimeClock
+ FILE_GUID = C641D483-B367-40EF-96B3-860B75A4604E
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeRealTimeClock
+
+[Sources.common]
+ RealTimeClock.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ DebugLib
+ RealTimeClockLib
+
+[Protocols]
+ gEfiRealTimeClockArchProtocolGuid
+
+[Depex]
+ TRUE
+
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 8/14]: RiscVPkg/Universal: Remove stale moudles
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
` (4 preceding siblings ...)
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 7/14]: RiscVPkg/RealTimeClockRuntimeDxe: Add RISC-V RTC Runtime Driver Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 9/14]: RiscVPkg/CpuDxe: Use RISC-V platform level timer library Abner Chang
` (6 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
- Remove Timer DXE driver from RISC-V package becasue it is platform level driver has platform-specific implementation.
- Remove SEC module from RISC-V package because this is RISC-V processor-implementation specific. RISC-V platform code should provide this module.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/Universal/Sec/Riscv64/SecEntry.s | 109 ------
RiscVPkg/Universal/Sec/SecMain.c | 563 -----------------------------
RiscVPkg/Universal/Sec/SecMain.h | 56 ---
RiscVPkg/Universal/Sec/SecMain.inf | 72 ----
RiscVPkg/Universal/Sec/TrapHandler.c | 99 -----
RiscVPkg/Universal/TimerDxe/Timer.c | 288 ---------------
RiscVPkg/Universal/TimerDxe/Timer.h | 179 ---------
RiscVPkg/Universal/TimerDxe/Timer.uni | Bin 1678 -> 0 bytes
RiscVPkg/Universal/TimerDxe/TimerDxe.inf | 54 ---
| Bin 1374 -> 0 bytes
10 files changed, 1420 deletions(-)
delete mode 100644 RiscVPkg/Universal/Sec/Riscv64/SecEntry.s
delete mode 100644 RiscVPkg/Universal/Sec/SecMain.c
delete mode 100644 RiscVPkg/Universal/Sec/SecMain.h
delete mode 100644 RiscVPkg/Universal/Sec/SecMain.inf
delete mode 100644 RiscVPkg/Universal/Sec/TrapHandler.c
delete mode 100644 RiscVPkg/Universal/TimerDxe/Timer.c
delete mode 100644 RiscVPkg/Universal/TimerDxe/Timer.h
delete mode 100644 RiscVPkg/Universal/TimerDxe/Timer.uni
delete mode 100644 RiscVPkg/Universal/TimerDxe/TimerDxe.inf
delete mode 100644 RiscVPkg/Universal/TimerDxe/TimerExtra.uni
diff --git a/RiscVPkg/Universal/Sec/Riscv64/SecEntry.s b/RiscVPkg/Universal/Sec/Riscv64/SecEntry.s
deleted file mode 100644
index cc4ca6d..0000000
--- a/RiscVPkg/Universal/Sec/Riscv64/SecEntry.s
+++ /dev/null
@@ -1,109 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// RISC-V Sec module.
-//
-// Copyright (c) 2016-2017, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php.
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-#include <Base.h>
-#include <RiscV.h>
-
-.data
-
-.text
-.align 3
-
-.global ASM_PFX(_ModuleEntryPoint)
-
-.dword ASM_PFX(TrapFromUserModeHandler)
-.align 3
-.dword ASM_PFX(TrapFromSupervisorModeHandler)
-.align 3
-.dword ASM_PFX(TrapFromHypervisorModeHandler)
-.align 3
-.dword ASM_PFX(TrapFromMachineModeHandler)
-.align 3
-.dword ASM_PFX(NmiHandler)
-.align 3
-ASM_PFX(_ModuleEntryPoint):
- //
- // Set vector base to.
- //
-// li a0, 0xfffffec0
-// csrrw a1, 0x301, a0 // Machine vector base.
-// li a0, 0xfffffe80
-// csrrw a1, 0x201, a0 // Hypervisor vector base.
-// li a0, 0xfffffe40
-// csrrw a1, 0x101, a0 // Supervisor vector base.
- li a0, 0xfffffe00
- csrrw a1, RISCV_CSR_MACHINE_MTVEC, a0 // Machine vector base.
-
- //
- // Platform SEC PEI temporary memory init.
- //
- call RiscVPlatformTemporaryMemInit
- //
- // Set up temporary memory for SEC and PEI phase.
- // PcdOvmfSecPeiTempRamBase and PcdOvmfSecPeiTempRamSize
- // map to the specific region within system memory.
- //
- li a0, FixedPcdGet32 (PcdRiscVSecPeiTempRamBase)
- li a1, FixedPcdGet32 (PcdRiscVSecPeiTempRamSize)
- add a2, a0, a1 // a2 is top of temporary memory.
- add sp, a0, a1 // Set stack pointer to top of temporary memory.
-
- //
- // Call startup with stack
- //
- li a1, 0x20
- sub sp, sp, a1
- li a0, FixedPcdGet32 (PcdRiscVPeiFvBase) // Load boot FV in a0.
- add a1, a2, 0 // Load top of stack in a1.
- call SecCoreStartupWithStack
- //
- // Never return here.
- //
-
-//
-// User mode trap handler.
-//
-ASM_PFX(TrapFromUserModeHandler):
- call RiscVUserModeTrapHandler
- mret
-
-//
-//Supervisor mode trap handler.
-//
-ASM_PFX(TrapFromSupervisorModeHandler):
- call RiscVSupervisorModeTrapHandler
- mret
-
-//
-// Hypervisor mode trap handler.
-//
-ASM_PFX(TrapFromHypervisorModeHandler):
- call RiscVHypervisorModeTrapHandler
- mret
-
-//
-// Machine mode trap handler.
-//
-ASM_PFX(TrapFromMachineModeHandler):
- call RiscVMachineModeTrapHandler
- mret
-
-//
-// NMI trap handler.
-//
-ASM_PFX(NmiHandler):
- call RiscVNmiHandler
- mret
-
diff --git a/RiscVPkg/Universal/Sec/SecMain.c b/RiscVPkg/Universal/Sec/SecMain.c
deleted file mode 100644
index be87ce1..0000000
--- a/RiscVPkg/Universal/Sec/SecMain.c
+++ /dev/null
@@ -1,563 +0,0 @@
-/** @file
- RISC-V SEC phase module.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#include "SecMain.h"
-
-EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = {
- TemporaryRamMigration
-};
-
-EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi = {
- TemporaryRamDone
-};
-
-EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gEfiTemporaryRamSupportPpiGuid,
- &mTemporaryRamSupportPpi
- },
- {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiTemporaryRamDonePpiGuid,
- &mTemporaryRamDonePpi
- },
-};
-
-/**
- Locates a section within a series of sections
- with the specified section type.
-
- The Instance parameter indicates which instance of the section
- type to return. (0 is first instance, 1 is second...)
-
- @param[in] Sections The sections to search
- @param[in] SizeOfSections Total size of all sections
- @param[in] SectionType The section type to locate
- @param[in] Instance The section instance number
- @param[out] FoundSection The FFS section if found
-
- @retval EFI_SUCCESS The file and section was found
- @retval EFI_NOT_FOUND The file and section was not found
- @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
-
-**/
-EFI_STATUS
-FindFfsSectionInstance (
- IN VOID *Sections,
- IN UINTN SizeOfSections,
- IN EFI_SECTION_TYPE SectionType,
- IN UINTN Instance,
- OUT EFI_COMMON_SECTION_HEADER **FoundSection
- )
-{
- EFI_PHYSICAL_ADDRESS CurrentAddress;
- UINT32 Size;
- EFI_PHYSICAL_ADDRESS EndOfSections;
- EFI_COMMON_SECTION_HEADER *Section;
- EFI_PHYSICAL_ADDRESS EndOfSection;
-
- //
- // Loop through the FFS file sections within the PEI Core FFS file
- //
- EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN) Sections;
- EndOfSections = EndOfSection + SizeOfSections;
- for (;;) {
- if (EndOfSection == EndOfSections) {
- break;
- }
- CurrentAddress = (EndOfSection + 3) & ~(3ULL);
- if (CurrentAddress >= EndOfSections) {
- return EFI_VOLUME_CORRUPTED;
- }
-
- Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;
-
- Size = SECTION_SIZE (Section);
- if (Size < sizeof (*Section)) {
- return EFI_VOLUME_CORRUPTED;
- }
-
- EndOfSection = CurrentAddress + Size;
- if (EndOfSection > EndOfSections) {
- return EFI_VOLUME_CORRUPTED;
- }
-
- //
- // Look for the requested section type
- //
- if (Section->Type == SectionType) {
- if (Instance == 0) {
- *FoundSection = Section;
- return EFI_SUCCESS;
- } else {
- Instance--;
- }
- }
- }
-
- return EFI_NOT_FOUND;
-}
-
-/**
- Locates a section within a series of sections
- with the specified section type.
-
- @param[in] Sections The sections to search
- @param[in] SizeOfSections Total size of all sections
- @param[in] SectionType The section type to locate
- @param[out] FoundSection The FFS section if found
-
- @retval EFI_SUCCESS The file and section was found
- @retval EFI_NOT_FOUND The file and section was not found
- @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
-
-**/
-EFI_STATUS
-FindFfsSectionInSections (
- IN VOID *Sections,
- IN UINTN SizeOfSections,
- IN EFI_SECTION_TYPE SectionType,
- OUT EFI_COMMON_SECTION_HEADER **FoundSection
- )
-{
- return FindFfsSectionInstance (
- Sections,
- SizeOfSections,
- SectionType,
- 0,
- FoundSection
- );
-}
-
-/**
- Locates a FFS file with the specified file type and a section
- within that file with the specified section type.
-
- @param[in] Fv The firmware volume to search
- @param[in] FileType The file type to locate
- @param[in] SectionType The section type to locate
- @param[out] FoundSection The FFS section if found
-
- @retval EFI_SUCCESS The file and section was found
- @retval EFI_NOT_FOUND The file and section was not found
- @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
-
-**/
-EFI_STATUS
-FindFfsFileAndSection (
- IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
- IN EFI_FV_FILETYPE FileType,
- IN EFI_SECTION_TYPE SectionType,
- OUT EFI_COMMON_SECTION_HEADER **FoundSection
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS CurrentAddress;
- EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;
- EFI_FFS_FILE_HEADER *File;
- UINT32 Size;
- EFI_PHYSICAL_ADDRESS EndOfFile;
-
- if (Fv->Signature != EFI_FVH_SIGNATURE) {
- DEBUG ((EFI_D_ERROR, "FV at %p does not have FV header signature\n", Fv));
- return EFI_VOLUME_CORRUPTED;
- }
-
- CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) Fv;
- EndOfFirmwareVolume = CurrentAddress + Fv->FvLength;
-
- //
- // Loop through the FFS files in the Boot Firmware Volume
- //
- for (EndOfFile = CurrentAddress + Fv->HeaderLength; ; ) {
-
- CurrentAddress = (EndOfFile + 7) & ~(7ULL);
- if (CurrentAddress > EndOfFirmwareVolume) {
- return EFI_VOLUME_CORRUPTED;
- }
-
- File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;
- Size = *(UINT32*) File->Size & 0xffffff;
- if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) {
- return EFI_VOLUME_CORRUPTED;
- }
-
- EndOfFile = CurrentAddress + Size;
- if (EndOfFile > EndOfFirmwareVolume) {
- return EFI_VOLUME_CORRUPTED;
- }
-
- //
- // Look for the request file type
- //
- if (File->Type != FileType) {
- continue;
- }
-
- Status = FindFfsSectionInSections (
- (VOID*) (File + 1),
- (UINTN) EndOfFile - (UINTN) (File + 1),
- SectionType,
- FoundSection
- );
- if (!EFI_ERROR (Status) || (Status == EFI_VOLUME_CORRUPTED)) {
- return Status;
- }
- }
-}
-
-/**
- Locates the PEI Core entry point address
-
- @param[in] Fv The firmware volume to search
- @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
-
- @retval EFI_SUCCESS The file and section was found
- @retval EFI_NOT_FOUND The file and section was not found
- @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
-
-**/
-EFI_STATUS
-FindPeiCoreImageBaseInFv (
- IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
- OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
- )
-{
- EFI_STATUS Status;
- EFI_COMMON_SECTION_HEADER *Section;
-
- Status = FindFfsFileAndSection (
- Fv,
- EFI_FV_FILETYPE_PEI_CORE,
- EFI_SECTION_PE32,
- &Section
- );
- if (EFI_ERROR (Status)) {
- Status = FindFfsFileAndSection (
- Fv,
- EFI_FV_FILETYPE_PEI_CORE,
- EFI_SECTION_TE,
- &Section
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "Unable to find PEI Core image\n"));
- return Status;
- }
- }
- DEBUG ((EFI_D_ERROR, "PeiCoreImageBase found\n"));
- *PeiCoreImageBase = (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1);
- return EFI_SUCCESS;
-}
-
-/**
- Reads 8-bits of CMOS data.
-
- Reads the 8-bits of CMOS data at the location specified by Index.
- The 8-bit read value is returned.
-
- @param Index The CMOS location to read.
-
- @return The value read.
-
-**/
-STATIC
-UINT8
-CmosRead8 (
- IN UINTN Index
- )
-{
- IoWrite8 (0x70, (UINT8) Index);
- return IoRead8 (0x71);
-}
-
-STATIC
-BOOLEAN
-IsS3Resume (
- VOID
- )
-{
- return (CmosRead8 (0xF) == 0xFE);
-}
-
-/**
- Locates the PEI Core entry point address
-
- @param[in,out] Fv The firmware volume to search
- @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
-
- @retval EFI_SUCCESS The file and section was found
- @retval EFI_NOT_FOUND The file and section was not found
- @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
-
-**/
-VOID
-FindPeiCoreImageBase (
- IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv,
- OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
- )
-{
- *PeiCoreImageBase = 0;
-
- if (IsS3Resume ()) {
- DEBUG ((EFI_D_VERBOSE, "SEC: S3 resume not supported.\n"));
- ASSERT (FALSE);
- } else {
- DEBUG ((EFI_D_VERBOSE, "SEC: Normal boot\n"));
- }
- DEBUG ((EFI_D_INFO, "FindPeiCoreImageBaseInFv\n"));
- FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase);
-}
-
-/*
- Find and return Pei Core entry point.
-
- It also find SEC and PEI Core file debug inforamtion. It will report them if
- remote debug is enabled.
-
-**/
-VOID
-FindAndReportEntryPoints (
- IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr,
- OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PeiCoreImageBase;
-
- DEBUG ((EFI_D_INFO, "FindAndReportEntryPoints\n"));
-
- FindPeiCoreImageBase (BootFirmwareVolumePtr, &PeiCoreImageBase);
- //
- // Find PEI Core entry point
- //
- Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);
- if (EFI_ERROR(Status)) {
- *PeiCoreEntryPoint = 0;
- }
- DEBUG ((EFI_D_INFO, "PeCoffLoaderGetEntryPoint success: %x\n", *PeiCoreEntryPoint));
-
- return;
-}
-
-VOID
-EFIAPI
-SecCoreStartupWithStack (
- IN EFI_FIRMWARE_VOLUME_HEADER *BootFv,
- IN VOID *TopOfCurrentStack
- )
-{
- EFI_SEC_PEI_HAND_OFF SecCoreData;
- RISCV_MACHINE_MODE_CONTEXT *RiscvContext;
-
- ProcessLibraryConstructorList (NULL, NULL);
- DEBUG ((EFI_D_INFO,
- "SecCoreStartupWithStack(0x%x, 0x%x)\n",
- (UINT32)(UINTN)BootFv,
- (UINT32)(UINTN)TopOfCurrentStack
- ));
-
- //
- // Initialize SEC hand-off state
- //
- SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
-
- //
- // Temporary memory usage
- //
- // (TemporaryRamBase + TemporaryRamSize) = --> |==============================
- // | ^
- // | |
- // | 1/2 * (TemporaryRamSize - RISCV_MACHINE_MODE_CONTEXT)
- // | |
- // | v
- // StackBase = --> |==============================
- // | ^
- // | |
- // | 1/2 * (TemporaryRamSize - RISCV_MACHINE_MODE_CONTEXT)
- // | |
- // | v
- // PeiTemporaryRamBase ----> |==============================
- // |
- //TemporaryRamBase = RISCV_MACHINE_MODE_CONTEXT-> ==============================
-
- SecCoreData.TemporaryRamSize = (UINTN) PcdGet32 (PcdRiscVSecPeiTempRamSize) - RISCV_MACHINE_CONTEXT_SIZE;
- SecCoreData.TemporaryRamBase = (VOID*)((UINT8 *)TopOfCurrentStack - SecCoreData.TemporaryRamSize);
-
- SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
- SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize >> 1;
-
- SecCoreData.StackBase = (UINT8 *)SecCoreData.TemporaryRamBase +
- (SecCoreData.TemporaryRamSize >> 1);
- SecCoreData.StackSize = (SecCoreData.TemporaryRamSize >> 1);
-
- SecCoreData.BootFirmwareVolumeBase = BootFv;
- SecCoreData.BootFirmwareVolumeSize = (UINTN) BootFv->FvLength;
-
- //
- // Setup RISCV_MACHINE_MODE_CONTEXT.
- //
- RiscvContext = (RISCV_MACHINE_MODE_CONTEXT *)(SecCoreData.TemporaryRamBase - RISCV_MACHINE_CONTEXT_SIZE);
- RiscvContext->MachineModeTrapHandler = (EFI_PHYSICAL_ADDRESS)(UINTN)SecMachineModeTrapHandler;
- RiscVSetScratch (RiscvContext);
- DEBUG ((DEBUG_INFO, "RISC-V Machine mode context at %x\n", RiscVGetScratch ()));
-
- //
- // Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.
- //
- InitializeDebugAgent(DEBUG_AGENT_INIT_PREMEM_SEC, &SecCoreData, SecStartupPhase2);
-}
-
-/**
- Caller provided function to be invoked at the end of InitializeDebugAgent().
-
- Entry point to the C language phase of SEC. After the SEC assembly
- code has initialized some temporary memory and set up the stack,
- the control is transferred to this function.
-
- @param[in] Context The first input parameter of InitializeDebugAgent().
-
-**/
-VOID
-EFIAPI
-SecStartupPhase2(
- IN VOID *Context
- )
-{
- EFI_SEC_PEI_HAND_OFF *SecCoreData;
- EFI_FIRMWARE_VOLUME_HEADER *BootFv;
- EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
-
- DEBUG ((EFI_D_INFO, "SecStartupPhase2\n"));
-
- SecCoreData = (EFI_SEC_PEI_HAND_OFF *) Context;
-
- //
- // Find PEI Core entry point. It will report SEC and Pei Core debug information if remote debug
- // is enabled.
- //
- BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase;
- FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint);
- SecCoreData->BootFirmwareVolumeBase = BootFv;
- SecCoreData->BootFirmwareVolumeSize = (UINTN) BootFv->FvLength;
-
- DEBUG ((EFI_D_INFO, "Transfer the control to the PEI core BootFv:%x , FvLength:%x\n", BootFv, BootFv->FvLength));
- //
- // Transfer the control to the PEI core
- //
- (*PeiCoreEntryPoint) (SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateDispatchTable);
-
- //
- // If we get here then the PEI Core returned, which is not recoverable.
- //
- ASSERT (FALSE);
- //CpuDeadLoop ();
-}
-
-EFI_STATUS
-EFIAPI
-TemporaryRamMigration (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
- IN UINTN CopySize
- )
-{
- VOID *OldHeap;
- VOID *NewHeap;
- VOID *OldStack;
- VOID *NewStack;
- DEBUG_AGENT_CONTEXT_POSTMEM_SEC DebugAgentContext;
- BOOLEAN OldStatus;
- BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
-
- DEBUG ((EFI_D_INFO,
- "TemporaryRamMigration(0x%Lx, 0x%Lx, 0x%Lx)\n",
- TemporaryMemoryBase,
- PermanentMemoryBase,
- (UINT64)CopySize
- ));
-
- OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
- NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));
-
- OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));
- NewStack = (VOID*)(UINTN)PermanentMemoryBase;
-
- DebugAgentContext.HeapMigrateOffset = (UINTN)NewHeap - (UINTN)OldHeap;
- DebugAgentContext.StackMigrateOffset = (UINTN)NewStack - (UINTN)OldStack;
-
- OldStatus = SaveAndSetDebugTimerInterrupt (FALSE);
- InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, (VOID *) &DebugAgentContext, NULL);
-
- CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap
- CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack
-
- //
- // Use SetJump()/LongJump() to switch to a new stack.
- //
- if (SetJump (&JumpBuffer) == 0) {
- DEBUG ((EFI_D_INFO,"Return from SetJump\n"));
- JumpBuffer.SP = JumpBuffer.SP + DebugAgentContext.StackMigrateOffset;
- LongJump (&JumpBuffer, (UINTN)-1);
- //
- // LongJump will return to before TemporaryRamMigration.
- //
- }
-
- SaveAndSetDebugTimerInterrupt (OldStatus);
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EFIAPI
-TemporaryRamDone (
- VOID
- )
-{
- EFI_PEI_SERVICES **PeiServices;
- EFI_STATUS Status;
- RISCV_MACHINE_MODE_CONTEXT *MachineModeContext;
- RISCV_MACHINE_MODE_CONTEXT *OldMachineModeContext;
- EFI_HOB_GUID_TYPE *HobGuid;
-
- DEBUG ((EFI_D_INFO, "TemporaryRamDone\n"));
-
- OldMachineModeContext = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
- PeiServices = (EFI_PEI_SERVICES **)(UINTN)OldMachineModeContext->PeiService;
-
- //
- // Copy RISCV_MACHINE_MODE_CONTEXT to HOB.
- //
- Status = (*PeiServices)->CreateHob (
- (const EFI_PEI_SERVICES**)PeiServices,
- EFI_HOB_TYPE_GUID_EXTENSION,
- sizeof (EFI_HOB_GUID_TYPE) + sizeof (RISCV_MACHINE_MODE_CONTEXT),
- (VOID **)&HobGuid
- );
- ASSERT (!EFI_ERROR (Status));
- HobGuid->Name = gUefiRiscVMachineContextGuid;
- OldMachineModeContext = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
- MachineModeContext = (RISCV_MACHINE_MODE_CONTEXT *)(HobGuid + 1);
- CopyMem (MachineModeContext, OldMachineModeContext, sizeof (RISCV_MACHINE_MODE_CONTEXT));
- RiscVSetScratch (MachineModeContext);
- DEBUG ((DEBUG_INFO, "New RISCV_MACHINE_MODE_CONTEXT at %x.\n", RiscVGetScratch ()));
-
- //
- // Platform temporary memory done.
- //
- //RiscVPlatformTemporaryRamDone ();
- return EFI_SUCCESS;
-}
diff --git a/RiscVPkg/Universal/Sec/SecMain.h b/RiscVPkg/Universal/Sec/SecMain.h
deleted file mode 100644
index 5863351..0000000
--- a/RiscVPkg/Universal/Sec/SecMain.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/** @file
- RISC-V SEC phase module definitions..
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-#include <PiPei.h>
-#include <Library/PeimEntryPoint.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DebugAgentLib.h>
-#include <Library/IoLib.h>
-#include <Library/PeCoffLib.h>
-#include <Library/PeCoffGetEntryPointLib.h>
-#include <Library/PeCoffExtraActionLib.h>
-#include <Library/ExtractGuidedSectionLib.h>
-#include <Library/HobLib.h>
-#include <Ppi/TemporaryRamSupport.h>
-#include <Ppi/TemporaryRamDone.h>
-#include <Library/RiscVCpuLib.h>
-
-VOID
-SecMachineModeTrapHandler (
- IN VOID
- );
-
-VOID
-EFIAPI
-SecStartupPhase2 (
- IN VOID *Context
- );
-
-EFI_STATUS
-EFIAPI
-TemporaryRamMigration (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
- IN UINTN CopySize
- );
-
-EFI_STATUS
-EFIAPI
-TemporaryRamDone (
- VOID
- );
diff --git a/RiscVPkg/Universal/Sec/SecMain.inf b/RiscVPkg/Universal/Sec/SecMain.inf
deleted file mode 100644
index cb678a5..0000000
--- a/RiscVPkg/Universal/Sec/SecMain.inf
+++ /dev/null
@@ -1,72 +0,0 @@
-## @file
-# RISC-V SEC module.
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = SecMain
- FILE_GUID = df1ccef6-f301-4a63-9661-fc6030dcc880
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- ENTRY_POINT = SecMain
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64 RISCV32 EBC
-#
-
-[Sources]
- SecMain.c
- TrapHandler.c
-
-[Sources.RISCV32]
-
-[Sources.RISCV64]
- Riscv64/SecEntry.s
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- OvmfPkg/OvmfPkg.dec
- RiscVPkg/RiscVPkg.dec
- RiscVVirtPkg/RiscVVirtPkg.dec
-
-[LibraryClasses]
- BaseLib
- DebugLib
- BaseMemoryLib
- PcdLib
- DebugAgentLib
- IoLib
- PeCoffLib
- PeCoffGetEntryPointLib
- PeCoffExtraActionLib
- ExtractGuidedSectionLib
- RiscVPlatformTempMemoryInitLib
- RiscVCpuLib
-
-[Ppis]
- gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED
- gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED
-
-[Guids]
- gUefiRiscVMachineContextGuid
-
-[Pcd]
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVPeiFvBase
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVPeiFvSize
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVSecPeiTempRamSize
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVSecPeiTempRamBase
-
diff --git a/RiscVPkg/Universal/Sec/TrapHandler.c b/RiscVPkg/Universal/Sec/TrapHandler.c
deleted file mode 100644
index 6783501..0000000
--- a/RiscVPkg/Universal/Sec/TrapHandler.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/** @file
- RISC-V trap handler.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "SecMain.h"
-
-/**
- RISC-V User mode trap handler.
-
-**/
-VOID
-RiscVUserModeTrapHandler (
- VOID
- )
-{
- DEBUG ((EFI_D_INFO, "Enter RISC-V User Mode Trap Handler.\n"));
- //while (TRUE);
-}
-
-/**
- RISC-V Supervisor mode trap handler.
-
-**/
-VOID
-RiscVSupervisorModeTrapHandler (
- VOID
- )
-{
- DEBUG ((EFI_D_INFO, "Enter RISC-V Supervisor Mode Trap Handler.\n"));
- //while (TRUE);
-}
-
-/**
- RISC-V Hypervisor mode trap handler.
-
-**/
-VOID
-RiscVHypervisorModeTrapHandler (
- VOID
- )
-{
- DEBUG ((EFI_D_INFO, "Enter RISC-V Hypervisor Mode Trap Handler.\n"));
- //while (TRUE);
-}
-
-/**
- RISC-V Machine mode trap handler.
-
-**/
-VOID
-RiscVMachineModeTrapHandler (
- VOID
- )
-{
- RISCV_TRAP_HANDLER TrapHandle;
- RISCV_MACHINE_MODE_CONTEXT *Context;
-
- //DEBUG ((EFI_D_INFO, "Enter RISC-V Machine Mode Trap Handler.\n"));
- Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
- TrapHandle = (RISCV_TRAP_HANDLER)(UINTN)Context->MachineModeTrapHandler;
- TrapHandle ();
-}
-
-/**
- RISC-V NMI trap handler.
-
-**/
-VOID
-RiscVNmiHandler (
- VOID
- )
-{
- DEBUG ((EFI_D_INFO, "Enter RISC-V NMI Trap Handler.\n"));
- //while (TRUE);
-}
-
-/**
- SEC RISC-V Machine mode trap handler.
-
-**/
-VOID
-SecMachineModeTrapHandler (
- IN VOID
- )
-{
- //DEBUG ((EFI_D_INFO, "SEC RISC-V Machine Mode Trap Handler.\n"));
- //while (TRUE);
-}
diff --git a/RiscVPkg/Universal/TimerDxe/Timer.c b/RiscVPkg/Universal/TimerDxe/Timer.c
deleted file mode 100644
index 1a454c2..0000000
--- a/RiscVPkg/Universal/TimerDxe/Timer.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/** @file
- RISC-V Timer Architectural Protocol as defined in the DXE CIS
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#include "Timer.h"
-
-//
-// The handle onto which the Timer Architectural Protocol will be installed
-//
-EFI_HANDLE mTimerHandle = NULL;
-
-//
-// The Timer Architectural Protocol that this driver produces
-//
-EFI_TIMER_ARCH_PROTOCOL mTimer = {
- TimerDriverRegisterHandler,
- TimerDriverSetTimerPeriod,
- TimerDriverGetTimerPeriod,
- TimerDriverGenerateSoftInterrupt
-};
-
-//
-// Pointer to the CPU Architectural Protocol instance
-//
-EFI_CPU_ARCH_PROTOCOL *mCpu;
-
-//
-// The notification function to call on every timer interrupt.
-// A bug in the compiler prevents us from initializing this here.
-//
-EFI_TIMER_NOTIFY mTimerNotifyFunction;
-
-//
-// The current period of the timer interrupt
-//
-volatile UINT64 mTimerPeriod = 0;
-
-/**
- 8254 Timer #0 Interrupt Handler.
-
- @param InterruptType The type of interrupt that occured
- @param SystemContext A pointer to the system context when the interrupt occured
-**/
-VOID
-EFIAPI
-TimerInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
- )
-{
- EFI_TPL OriginalTPL;
- UINT32 RiscvTimer;
-
- OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
- if (mTimerPeriod == 0) {
- gBS->RestoreTPL (OriginalTPL);
- return;
- }
- if (mTimerNotifyFunction != NULL) {
- mTimerNotifyFunction (mTimerPeriod);
- }
- RiscvTimer = RiscVReadMachineTimer();
- RiscvTimer += ((mTimerPeriod * 100) / PcdGet64 (PcdRiscVMachineTimerTickInNanoSecond));
- RiscVSetMachineTimerCmp (RiscvTimer); // Clear previous interrupt status and also set another timer.
- gBS->RestoreTPL (OriginalTPL);
-}
-
-/**
-
- This function registers the handler NotifyFunction so it is called every time
- the timer interrupt fires. It also passes the amount of time since the last
- handler call to the NotifyFunction. If NotifyFunction is NULL, then the
- handler is unregistered. If the handler is registered, then EFI_SUCCESS is
- returned. If the CPU does not support registering a timer interrupt handler,
- then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
- when a handler is already registered, then EFI_ALREADY_STARTED is returned.
- If an attempt is made to unregister a handler when a handler is not registered,
- then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
- register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
- is returned.
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param NotifyFunction The function to call when a timer interrupt fires. This
- function executes at TPL_HIGH_LEVEL. The DXE Core will
- register a handler for the timer interrupt, so it can know
- how much time has passed. This information is used to
- signal timer based events. NULL will unregister the handler.
-
- @retval EFI_SUCCESS The timer handler was registered.
- @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
- @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
- registered.
- @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
- previously registered.
- @retval EFI_DEVICE_ERROR The timer handler could not be registered.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverRegisterHandler (
- IN EFI_TIMER_ARCH_PROTOCOL *This,
- IN EFI_TIMER_NOTIFY NotifyFunction
- )
-{
- DEBUG ((DEBUG_INFO, "TimerDriverRegisterHandler\n"));
- mTimerNotifyFunction = NotifyFunction;
- return EFI_SUCCESS;
-}
-
-/**
-
- This function adjusts the period of timer interrupts to the value specified
- by TimerPeriod. If the timer period is updated, then the selected timer
- period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
- If an error occurs while attempting to update the timer period, then the
- timer hardware will be put back in its state prior to this call, and
- EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
- is disabled. This is not the same as disabling the CPU's interrupts.
- Instead, it must either turn off the timer hardware, or it must adjust the
- interrupt controller so that a CPU interrupt is not generated when the timer
- interrupt fires.
-
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is
- returned. If the timer is programmable, then the timer period
- will be rounded up to the nearest timer period that is supported
- by the timer hardware. If TimerPeriod is set to 0, then the
- timer interrupts will be disabled.
-
- @retval EFI_SUCCESS The timer period was changed.
- @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
- @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverSetTimerPeriod (
- IN EFI_TIMER_ARCH_PROTOCOL *This,
- IN UINT64 TimerPeriod
- )
-{
- UINT32 RiscvTimer;
-
- TimerPeriod = 10 *1000 * 50;
- mTimerPeriod = TimerPeriod;
- if (TimerPeriod == 0) {
- return EFI_SUCCESS;
- }
- RiscvTimer = RiscVReadMachineTimer();
- RiscvTimer += ((TimerPeriod * 100) / PcdGet64 (PcdRiscVMachineTimerTickInNanoSecond));
- RiscVSetMachineTimerCmp (RiscvTimer);
- return EFI_SUCCESS;
-}
-
-/**
-
- This function retrieves the period of timer interrupts in 100 ns units,
- returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
- is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
- returned, then the timer is currently disabled.
-
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
- 0 is returned, then the timer is currently disabled.
-
- @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
- @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverGetTimerPeriod (
- IN EFI_TIMER_ARCH_PROTOCOL *This,
- OUT UINT64 *TimerPeriod
- )
-{
- DEBUG ((DEBUG_INFO, "TimerDriverGetTimerPeriod\n"));
- *TimerPeriod = mTimerPeriod;
- return EFI_SUCCESS;
-}
-
-/**
-
- This function generates a soft timer interrupt. If the platform does not support soft
- timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
- If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
- service, then a soft timer interrupt will be generated. If the timer interrupt is
- enabled when this service is called, then the registered handler will be invoked. The
- registered handler should not be able to distinguish a hardware-generated timer
- interrupt from a software-generated timer interrupt.
-
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
-
- @retval EFI_SUCCESS The soft timer interrupt was generated.
- @retval EFI_UNSUPPORTEDT The platform does not support the generation of soft timer interrupts.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverGenerateSoftInterrupt (
- IN EFI_TIMER_ARCH_PROTOCOL *This
- )
-{
- return EFI_SUCCESS;
-}
-
-/**
- Initialize the Timer Architectural Protocol driver
-
- @param ImageHandle ImageHandle of the loaded driver
- @param SystemTable Pointer to the System Table
-
- @retval EFI_SUCCESS Timer Architectural Protocol created
- @retval EFI_OUT_OF_RESOURCES Not enough resources available to initialize driver.
- @retval EFI_DEVICE_ERROR A device error occured attempting to initialize the driver.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
-
- //
- // Initialize the pointer to our notify function.
- //
- mTimerNotifyFunction = NULL;
-
- //
- // Make sure the Timer Architectural Protocol is not already installed in the system
- //
- ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiTimerArchProtocolGuid);
-
- //
- // Find the CPU architectural protocol.
- //
- Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **) &mCpu);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Force the timer to be disabled
- //
- Status = TimerDriverSetTimerPeriod (&mTimer, 0);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Install interrupt handler for RISC-V Timer.
- //
- Status = mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_TIMER_INT, TimerInterruptHandler);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Force the timer to be enabled at its default period
- //
- Status = TimerDriverSetTimerPeriod (&mTimer, DEFAULT_TIMER_TICK_DURATION);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Install the Timer Architectural Protocol onto a new handle
- //
- Status = gBS->InstallMultipleProtocolInterfaces (
- &mTimerHandle,
- &gEfiTimerArchProtocolGuid, &mTimer,
- NULL
- );
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
-
diff --git a/RiscVPkg/Universal/TimerDxe/Timer.h b/RiscVPkg/Universal/TimerDxe/Timer.h
deleted file mode 100644
index cae30b6..0000000
--- a/RiscVPkg/Universal/TimerDxe/Timer.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/** @file
- RISC-V Timer Architectural Protocol definitions.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#ifndef _TIMER_H_
-#define _TIMER_H_
-
-#include <PiDxe.h>
-
-#include <Protocol/Cpu.h>
-#include <Protocol/Timer.h>
-
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/RiscVCpuLib.h>
-
-//
-// RISC-V use 100us timer.
-// The default timer tick duration is set to 10 ms = 10 * 1000 * 10 100 ns units
-//
-#define DEFAULT_TIMER_TICK_DURATION 100000
-
-extern VOID RiscvSetTimerPeriod (UINT32 TimerPeriod);
-
-//
-// Function Prototypes
-//
-/**
- Initialize the Timer Architectural Protocol driver
-
- @param ImageHandle ImageHandle of the loaded driver
- @param SystemTable Pointer to the System Table
-
- @retval EFI_SUCCESS Timer Architectural Protocol created
- @retval EFI_OUT_OF_RESOURCES Not enough resources available to initialize driver.
- @retval EFI_DEVICE_ERROR A device error occured attempting to initialize the driver.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-;
-
-/**
-
- This function adjusts the period of timer interrupts to the value specified
- by TimerPeriod. If the timer period is updated, then the selected timer
- period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
- If an error occurs while attempting to update the timer period, then the
- timer hardware will be put back in its state prior to this call, and
- EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
- is disabled. This is not the same as disabling the CPU's interrupts.
- Instead, it must either turn off the timer hardware, or it must adjust the
- interrupt controller so that a CPU interrupt is not generated when the timer
- interrupt fires.
-
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param NotifyFunction The rate to program the timer interrupt in 100 nS units. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is
- returned. If the timer is programmable, then the timer period
- will be rounded up to the nearest timer period that is supported
- by the timer hardware. If TimerPeriod is set to 0, then the
- timer interrupts will be disabled.
-
- @retval EFI_SUCCESS The timer period was changed.
- @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
- @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverRegisterHandler (
- IN EFI_TIMER_ARCH_PROTOCOL *This,
- IN EFI_TIMER_NOTIFY NotifyFunction
- )
-;
-
-/**
-
- This function adjusts the period of timer interrupts to the value specified
- by TimerPeriod. If the timer period is updated, then the selected timer
- period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
- If an error occurs while attempting to update the timer period, then the
- timer hardware will be put back in its state prior to this call, and
- EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
- is disabled. This is not the same as disabling the CPU's interrupts.
- Instead, it must either turn off the timer hardware, or it must adjust the
- interrupt controller so that a CPU interrupt is not generated when the timer
- interrupt fires.
-
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is
- returned. If the timer is programmable, then the timer period
- will be rounded up to the nearest timer period that is supported
- by the timer hardware. If TimerPeriod is set to 0, then the
- timer interrupts will be disabled.
-
- @retval EFI_SUCCESS The timer period was changed.
- @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
- @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverSetTimerPeriod (
- IN EFI_TIMER_ARCH_PROTOCOL *This,
- IN UINT64 TimerPeriod
- )
-;
-
-/**
-
- This function retrieves the period of timer interrupts in 100 ns units,
- returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
- is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
- returned, then the timer is currently disabled.
-
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
- @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
- 0 is returned, then the timer is currently disabled.
-
- @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
- @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverGetTimerPeriod (
- IN EFI_TIMER_ARCH_PROTOCOL *This,
- OUT UINT64 *TimerPeriod
- )
-;
-
-/**
-
- This function generates a soft timer interrupt. If the platform does not support soft
- timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
- If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
- service, then a soft timer interrupt will be generated. If the timer interrupt is
- enabled when this service is called, then the registered handler will be invoked. The
- registered handler should not be able to distinguish a hardware-generated timer
- interrupt from a software-generated timer interrupt.
-
-
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.
-
- @retval EFI_SUCCESS The soft timer interrupt was generated.
- @retval EFI_UNSUPPORTEDT The platform does not support the generation of soft timer interrupts.
-
-**/
-EFI_STATUS
-EFIAPI
-TimerDriverGenerateSoftInterrupt (
- IN EFI_TIMER_ARCH_PROTOCOL *This
- )
-;
-
-#endif
diff --git a/RiscVPkg/Universal/TimerDxe/Timer.uni b/RiscVPkg/Universal/TimerDxe/Timer.uni
deleted file mode 100644
index 173c8f47c316cbff43773e0f44d7c373f0bca3bb..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001
literal 1678
zcmd6nPjAye5XI+=#CNdL3!pXu4jd3dB*Z{OsiV}Pa6<WC3nxK|Ny(Q7es4C8n<_{>
zBFnq8yR&cJyq(=YzZ=%Di2n&+WN&P0ndLUIhxUNk#=eiNXC1q=w{~Wq@l5fX<F~?Y
z(vIvJ>j&1-3jPs)&di$83g3mzu<Lug5<dcQ$-b?7%|I#G^@#nC>7UzEduA`}6#E0w
zZk$`;K3yB&^__NQW7cD06wXL2GNMhGZPRY}bB`j%@`~)-y08)V+<9t8h`wfag`f7X
zeD4^~SJpy-*GKrLa8|T3`x(0iXcN&coLPZ~xQMTGnUk;9wmV%SW(GU%8CDKjrH}H{
z?i}wC*20-7;}T!H$GZp{Y@Oi1hP2xE(^-U*DwzbG=FYlA5i{}4V3N75oR(BX#7xMb
zMFq4OpC53kxZb!Hp%(6Do54ni!U}pRR#_iIc$RT>E~>B)bIM9MBeDL4*IibJ$^<pH
zcnv-ODLDiUq*!rFS=Cy>S-kX0R}}_z<*$mKaPCX28S95J*31myKIS$YuGB%f=C3rV
ztdts#;nk&*5_?bEv`>t6uT-h(Q@>{|>tn^Pb>A-NW9FqvK&Z~4!~KczxOC(MOEs;w
zMlW2U*63S4*68#WyDQd(ns~&>uJGzPvkT@spb8`L=siZ_t~td_@s*FF2CsMcD*9LY
zkF1Ef?ryw`60(Tx%O0mf@1RAO%2Les(U(GRRCtl3ss59F{pfv(U?Kg!fs}yJ2Q6mQ
zB=@k=M6DFRe|;yMrtZUx3K-Dp{-`F-z!K9M=u)tJ1y!--D>$Z7GJh}hCaTI+ZRM-5
lVNG{*&CLDY&YEX<|14D_VkU;&{ka^=^nc2-j;7^l{srBn12O;r
diff --git a/RiscVPkg/Universal/TimerDxe/TimerDxe.inf b/RiscVPkg/Universal/TimerDxe/TimerDxe.inf
deleted file mode 100644
index 406994b..0000000
--- a/RiscVPkg/Universal/TimerDxe/TimerDxe.inf
+++ /dev/null
@@ -1,54 +0,0 @@
-## @file
-# RISC-V Timer Arch protocol module.
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = Timer
- MODULE_UNI_FILE = Timer.uni
- FILE_GUID = f2765dec-6b41-11d5-8e71-00902707b35e
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = TimerDriverInitialize
-
-[Packages]
- MdePkg/MdePkg.dec
- RiscVPkg/RiscVPkg.dec
-
-[LibraryClasses]
- UefiBootServicesTableLib
- BaseLib
- DebugLib
- UefiDriverEntryPoint
- IoLib
- RiscVCpuLib
-
-[Sources]
- Timer.h
- Timer.c
-
-[Protocols]
- gEfiCpuArchProtocolGuid ## CONSUMES
- gEfiTimerArchProtocolGuid ## PRODUCES
-
-[Pcd]
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
-
-[Depex]
- gEfiCpuArchProtocolGuid
-
-[UserExtensions.TianoCore."ExtraFiles"]
- TimerExtra.uni
diff --git a/RiscVPkg/Universal/TimerDxe/TimerExtra.uni b/RiscVPkg/Universal/TimerDxe/TimerExtra.uni
deleted file mode 100644
index 0db560f27965e588e37f60f42ff6a9910786c80a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001
literal 1374
zcmZXUTW=Ck6ovP*iT`0jU(~dqKKNja5z1(ZElenQd1?k|=|m`Gz*hY6>bLgHnW31;
zoXftfz0Nv&=I@`DwJhR&!4ugByRpm`c5P4X30C<=Se96F*5|gesij0@_8Z#_+of&s
zWp-zC+pter$$m=g9lmQH174U5|Jrt*JGWaRBYOt=bLQ9f(q7pcJ7#?b!h>_#dQ3uv
zsr_Kgy-r+K$!+ae8{#ADGT!qpV6k@o;-V8I)?{wuSul%vQC-|~GL)Zt?u^KH*0G_z
zuk@(-kKmm7iB)$6N)D$bC_#ZO5#l1gQzDiyk#AS36=6wTA+eCEo2rho#3sU;ku4R)
zOv(m)WzWhA_pEhusZAJ__md2Hb#H-*ZX>7a{ymAAA~T{gU(36q6Y9JUx7=la{)kJh
z#e-`xW&HoN88w9{4uxK-wPCMQPv9Bq>R!}ug=#l=iaQePUql_UdaO*L=8mWd@e%x2
zr3T`(-BVV*w&gC~dWWk&3Uw8qyVgx|b8fVCp#BES1nx6CIq)<=x#bO-gjwe~vlu=J
zeKfF7jBUGM-$PUNspb*Z9-TI36}!@7>odpLYlQk1dVF0m5toiUV5N@M*kBf}P#er0
z-)nbVaf|FLe(@T3MeW;E60<(`9;m_?c=aJWahFXsM?@(`Rg0*P#47VU^JhF_t}iz(
zs}!e*?OTOYqxaAvp|4c4%l8&^3v=Xurk2}fJE}TI{~P^%q}^4iZUV}%I>8m#15n4{
z$HequdBG}jv?Fd%U(%dgPZ`xS>Vp&F#ZT25ph>$^tY5J0{|mdEM_66&WBqG#;*}NN
EfA`naA^-pY
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 9/14]: RiscVPkg/CpuDxe: Use RISC-V platform level timer library
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
` (5 preceding siblings ...)
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 8/14]: RiscVPkg/Universal: Remove stale moudles Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 10/14]: RiscVPkg/SmbiosDxe: RISC-V platform generic SMBIOS DXE driver Abner Chang
` (5 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Due to RISC-V timer CSR is platform implementation specific, RISC-V CPU DXE driver invokes platform level timer library
to access to timer CSRs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.inf b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
index f33bcb9..93638e7 100644
--- a/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
@@ -1,7 +1,7 @@
## @file
# RISC-V CPU DXE module.
#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -43,6 +43,7 @@
HobLib
ReportStatusCodeLib
RiscVCpuLib
+ RiscVPlatformTimerLib
[Sources]
CpuDxe.c
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 10/14]: RiscVPkg/SmbiosDxe: RISC-V platform generic SMBIOS DXE driver
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
` (6 preceding siblings ...)
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 9/14]: RiscVPkg/CpuDxe: Use RISC-V platform level timer library Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 11/14]: RiscVPkg: Updates for supporting RISC-V OpenSBI Abner Chang
` (4 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7 and type 44 records.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 343 +++++++++++++++++++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 38 +++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 63 ++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | Bin 0 -> 1542 bytes
| Bin 0 -> 1438 bytes
5 files changed, 444 insertions(+)
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
new file mode 100644
index 0000000..b59af1a
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
@@ -0,0 +1,343 @@
+/** @file
+ RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and type 44 records.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials are
+ licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "RiscVSmbiosDxe.h"
+
+#define RISCV_SMBIOS_DEBUG_INFO 1
+
+EFI_SMBIOS_PROTOCOL *Smbios;
+
+/**
+ This function builds SMBIOS type 7 record according to
+ the given RISC_V_PROCESSOR_TYPE7_DATA_HOB.
+
+ @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB
+ @param Type7DataHob Pointer to RISC_V_PROCESSOR_TYPE7_DATA_HOB
+ @param SmbiosHandle Pointer to SMBIOS_HANDLE
+
+ @retval EFI_STATUS
+
+**/
+static
+EFI_STATUS
+BuildSmbiosType7 (
+ IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
+ IN RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7DataHob,
+ OUT SMBIOS_HANDLE *SmbiosHandle
+)
+{
+ EFI_STATUS Status;
+ SMBIOS_HANDLE Handle;
+
+ if (!CompareGuid (&Type4DataHob->PrcessorGuid, &Type7DataHob->PrcessorGuid) ||
+ Type4DataHob->ProcessorUid != Type7DataHob->ProcessorUid) {
+ return EFI_INVALID_PARAMETER;
+ }
+ Handle = SMBIOS_HANDLE_PI_RESERVED;
+ Type7DataHob->SmbiosType7Cache.Hdr.Type = SMBIOS_TYPE_CACHE_INFORMATION;
+ Type7DataHob->SmbiosType7Cache.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE7);
+ Type7DataHob->SmbiosType7Cache.Hdr.Handle = 0;
+ Status = Smbios->Add (Smbios, NULL, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type 7\n"));
+ return Status;
+ }
+ DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Handle));
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((EFI_D_INFO, " Cache belone to processor GUID: %g\n", &Type7DataHob->PrcessorGuid));
+ DEBUG ((EFI_D_INFO, " Cache belone processor UID: %d\n", Type7DataHob->ProcessorUid));
+ DEBUG ((EFI_D_INFO, " ==============================\n"));
+ DEBUG ((EFI_D_INFO, " Socket Designation: %d\n", Type7DataHob->SmbiosType7Cache.SocketDesignation));
+ DEBUG ((EFI_D_INFO, " Cache Configuration: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheConfiguration));
+ DEBUG ((EFI_D_INFO, " Maximum Cache Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.MaximumCacheSize));
+ DEBUG ((EFI_D_INFO, " Installed Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.InstalledSize));
+ DEBUG ((EFI_D_INFO, " Supported SRAM Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SupportedSRAMType));
+ DEBUG ((EFI_D_INFO, " Current SRAMT ype: 0x%x\n", Type7DataHob->SmbiosType7Cache.CurrentSRAMType));
+ DEBUG ((EFI_D_INFO, " Cache Speed: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheSpeed));
+ DEBUG ((EFI_D_INFO, " Error Correction Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.ErrorCorrectionType));
+ DEBUG ((EFI_D_INFO, " System Cache Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SystemCacheType));
+ DEBUG ((EFI_D_INFO, " Associativity: 0x%x\n", Type7DataHob->SmbiosType7Cache.Associativity));
+#endif
+
+ *SmbiosHandle = Handle;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function builds SMBIOS type 4 record according to
+ the given RISC_V_PROCESSOR_TYPE4_DATA_HOB.
+
+ @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB
+ @param SmbiosHandle Pointer to SMBIOS_HANDLE
+
+ @retval EFI_STATUS
+
+**/
+static
+EFI_STATUS
+BuildSmbiosType4 (
+ IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
+ OUT SMBIOS_HANDLE *SmbiosHandle
+ )
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_TYPE7_DATA_HOB *Type7HobData;
+ SMBIOS_HANDLE Cache;
+ SMBIOS_HANDLE Processor;
+ EFI_STATUS Status;
+
+ DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: Building Type 4.\n"));
+ DEBUG ((EFI_D_INFO, " Processor GUID: %g\n", &Type4DataHob->PrcessorGuid));
+ DEBUG ((EFI_D_INFO, " Processor UUID: %d\n", Type4DataHob->ProcessorUid));
+
+ Type4DataHob->SmbiosType4Processor.L1CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ Type4DataHob->SmbiosType4Processor.L2CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ Type4DataHob->SmbiosType4Processor.L3CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS Type7 data HOB found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processors.
+ //
+ do {
+ Type7HobData = (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)GET_GUID_HOB_DATA (GuidHob);
+ Status = BuildSmbiosType7 (Type4DataHob, Type7HobData, &Cache);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {
+ Type4DataHob->SmbiosType4Processor.L1CacheHandle = Cache;
+ } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {
+ Type4DataHob->SmbiosType4Processor.L2CacheHandle = Cache;
+ } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {
+ Type4DataHob->SmbiosType4Processor.L3CacheHandle = Cache;
+ } else {
+ DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: Improper cache level of SMBIOS handle %d\n", Cache));
+ }
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+
+ //
+ // Build SMBIOS Type 4 record
+ //
+ Processor = SMBIOS_HANDLE_PI_RESERVED;
+ Type4DataHob->SmbiosType4Processor.Hdr.Type = SMBIOS_TYPE_PROCESSOR_INFORMATION;
+ Type4DataHob->SmbiosType4Processor.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE4);
+ Type4DataHob->SmbiosType4Processor.Hdr.Handle = 0;
+ Status = Smbios->Add (Smbios, NULL, &Processor, &Type4DataHob->SmbiosType4Processor.Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type 4\n"));
+ return Status;
+ }
+ DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Processor));
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((EFI_D_INFO, " Socket StringID: %d\n", Type4DataHob->SmbiosType4Processor.Socket));
+ DEBUG ((EFI_D_INFO, " Processor Type: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorType));
+ DEBUG ((EFI_D_INFO, " Processor Family: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorFamily));
+ DEBUG ((EFI_D_INFO, " Processor Manufacture StringID: %d\n", Type4DataHob->SmbiosType4Processor.ProcessorManufacture));
+ DEBUG ((EFI_D_INFO, " Processor Id: 0x%x:0x%x\n", \
+ Type4DataHob->SmbiosType4Processor.ProcessorId.Signature, Type4DataHob->SmbiosType4Processor.ProcessorId.FeatureFlags));
+ DEBUG ((EFI_D_INFO, " Processor Version StringID: %d\n", Type4DataHob->SmbiosType4Processor.ProcessorVersion));
+ DEBUG ((EFI_D_INFO, " Voltage: 0x%x\n", Type4DataHob->SmbiosType4Processor.Voltage));
+ DEBUG ((EFI_D_INFO, " External Clock: 0x%x\n", Type4DataHob->SmbiosType4Processor.ExternalClock));
+ DEBUG ((EFI_D_INFO, " Max Speed: 0x%x\n", Type4DataHob->SmbiosType4Processor.MaxSpeed));
+ DEBUG ((EFI_D_INFO, " Current Speed: 0x%x\n", Type4DataHob->SmbiosType4Processor.CurrentSpeed));
+ DEBUG ((EFI_D_INFO, " Status: 0x%x\n", Type4DataHob->SmbiosType4Processor.Status));
+ DEBUG ((EFI_D_INFO, " ProcessorUpgrade: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorUpgrade));
+ DEBUG ((EFI_D_INFO, " L1 Cache Handle: 0x%x\n", Type4DataHob->SmbiosType4Processor.L1CacheHandle));
+ DEBUG ((EFI_D_INFO, " L2 Cache Handle: 0x%x\n",Type4DataHob->SmbiosType4Processor.L2CacheHandle));
+ DEBUG ((EFI_D_INFO, " L3 Cache Handle: 0x%x\n", Type4DataHob->SmbiosType4Processor.L3CacheHandle));
+ DEBUG ((EFI_D_INFO, " Serial Number StringID: %d\n", Type4DataHob->SmbiosType4Processor.SerialNumber));
+ DEBUG ((EFI_D_INFO, " Asset Tag StringID: %d\n", Type4DataHob->SmbiosType4Processor.AssetTag));
+ DEBUG ((EFI_D_INFO, " Part Number StringID: %d\n", Type4DataHob->SmbiosType4Processor.PartNumber));
+ DEBUG ((EFI_D_INFO, " Core Count: %d\n", Type4DataHob->SmbiosType4Processor.CoreCount));
+ DEBUG ((EFI_D_INFO, " Enabled CoreCount: %d\n", Type4DataHob->SmbiosType4Processor.EnabledCoreCount));
+ DEBUG ((EFI_D_INFO, " Thread Count: %d\n", Type4DataHob->SmbiosType4Processor.ThreadCount));
+ DEBUG ((EFI_D_INFO, " Processor Characteristics: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorCharacteristics));
+ DEBUG ((EFI_D_INFO, " Processor Family2: 0x%x\n", Type4DataHob->SmbiosType4Processor.ProcessorFamily2));
+ DEBUG ((EFI_D_INFO, " Core Count 2: %d\n", Type4DataHob->SmbiosType4Processor.CoreCount2));
+ DEBUG ((EFI_D_INFO, " Enabled CoreCount : %d\n", Type4DataHob->SmbiosType4Processor.EnabledCoreCount2));
+ DEBUG ((EFI_D_INFO, " Thread Count 2: %d\n", Type4DataHob->SmbiosType4Processor.ThreadCount2));
+#endif
+
+ *SmbiosHandle = Processor;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function builds SMBIOS type 44 record according..
+
+ @param Type4DataHob Pointer to RISC_V_PROCESSOR_TYPE4_DATA_HOB
+ @param Type4Handle SMBIOS handle of type 4
+
+ @retval EFI_STATUS
+
+**/
+EFI_STATUS
+BuildSmbiosType44 (
+ IN RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4DataHob,
+ IN SMBIOS_HANDLE Type4Handle
+ )
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecificData;
+ SMBIOS_HANDLE RiscVType44;
+ SMBIOS_TABLE_TYPE44 *Type44Ptr;
+ EFI_STATUS Status;
+
+ DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: Building Type 44 for...\n"));
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((EFI_D_INFO, " Processor GUID: %g\n", &Type4DataHob->PrcessorGuid));
+ DEBUG ((EFI_D_INFO, " Processor UUID: %d\n", Type4DataHob->ProcessorUid));
+#endif
+
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: No RISC_V_PROCESSOR_SPECIFIC_DATA_HOB found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Go through each RISC_V_PROCESSOR_SPECIFIC_DATA_HOB for multiple cores.
+ //
+ do {
+ ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)GET_GUID_HOB_DATA (GuidHob);
+ if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4DataHob->PrcessorGuid) ||
+ ProcessorSpecificData->ParentProcessorUid != Type4DataHob->ProcessorUid) {
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+ if (GuidHob == NULL) {
+ break;
+ }
+ continue;
+ }
+
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((EFI_D_INFO, "[ ================================\n"));
+ DEBUG ((EFI_D_INFO, "[ Core GUID: %g\n", &ProcessorSpecificData->CoreGuid));
+#endif
+
+ Type44Ptr = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA));
+ if (Type44Ptr == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ Type44Ptr->Hdr.Type = SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
+ Type44Ptr->Hdr.Handle = 0;
+ Type44Ptr->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ Type44Ptr->RefHandle = Type4Handle;
+ Type44Ptr->ProcessorSpecificBlock.Length = sizeof(RISC_V_PROCESSOR_SPECIFIC_DATA_HOB);
+ Type44Ptr->ProcessorSpecificBlock.ProcessorArchType = Type4DataHob->SmbiosType4Processor.ProcessorFamily2 -
+ ProcessorFamilyRiscvRV32 + \
+ ProcessorSpecificBlockArchTypeRiscVRV32;
+ CopyMem ((VOID *)(Type44Ptr + 1), (VOID *)&ProcessorSpecificData->ProcessorSpecificData, sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA));
+
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((EFI_D_INFO, "[ Core type: %d\n", Type44Ptr->ProcessorSpecificBlock.ProcessorArchType));
+ DEBUG ((EFI_D_INFO, " HartId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartId.Value64_L));
+ DEBUG ((EFI_D_INFO, " Is Boot Hart? = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->BootHartId));
+ DEBUG ((EFI_D_INFO, " PrivilegeModeSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->PrivilegeModeSupported));
+ DEBUG ((EFI_D_INFO, " MModeExcepDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeExcepDelegation.Value64_L));
+ DEBUG ((EFI_D_INFO, " MModeInterruptDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeInterruptDelegation.Value64_L));
+ DEBUG ((EFI_D_INFO, " HartXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartXlen));
+ DEBUG ((EFI_D_INFO, " MachineModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineModeXlen));
+ DEBUG ((EFI_D_INFO, " SupervisorModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->SupervisorModeXlen));
+ DEBUG ((EFI_D_INFO, " UserModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->UserModeXlen));
+ DEBUG ((EFI_D_INFO, " InstSetSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->InstSetSupported));
+ DEBUG ((EFI_D_INFO, " MachineVendorId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineVendorId.Value64_L));
+ DEBUG ((EFI_D_INFO, " MachineArchId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineArchId.Value64_L));
+ DEBUG ((EFI_D_INFO, " MachineImplId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineImplId.Value64_L));
+#endif
+
+ //
+ // Add to SMBIOS table.
+ //
+ RiscVType44 = SMBIOS_HANDLE_PI_RESERVED;
+ Status = Smbios->Add (Smbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: Fail to add SMBIOS Type 44\n"));
+ return Status;
+ }
+ DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n", RiscVType44));
+
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+ return EFI_SUCCESS;
+}
+
+/**
+ Entry point of RISC-V SMBIOS builder.
+
+ @param ImageHandle Image handle this driver.
+ @param SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS Thread can be successfully created
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Cannot create the thread
+
+**/
+EFI_STATUS
+EFIAPI
+RiscVSmbiosBuilderEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_TYPE4_DATA_HOB *Type4HobData;
+ SMBIOS_HANDLE Processor;
+
+ DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: %a entry\n", __FUNCTION__));
+
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **)&Smbios
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: Locate SMBIOS Protocol fail\n"));
+ return Status;
+ }
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS information found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ Type4HobData = (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)GET_GUID_HOB_DATA (GuidHob);
+ Status = EFI_NOT_FOUND;
+ //
+ // Go through each RISC_V_PROCESSOR_TYPE4_DATA_HOB for multiple processors.
+ //
+ do {
+ Status = BuildSmbiosType4 (Type4HobData, &Processor);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS type 4 created.\n"));
+ ASSERT (FALSE);
+ }
+ Status = BuildSmbiosType44 (Type4HobData, Processor);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "[RISC-V SMBIOS Builder]: No RISC-V SMBIOS type 44 found.\n"));
+ ASSERT (FALSE);
+ }
+
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+ DEBUG ((EFI_D_INFO, "[RISC-V SMBIOS Builder]: %a exit\n", __FUNCTION__));
+ return Status;
+}
+
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
new file mode 100644
index 0000000..9f7577f
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
@@ -0,0 +1,38 @@
+/** @file
+ RISC-V SMBIOS Builder DXE module header file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials are
+ licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _RISC_V_SMBIOS_DXE_H_
+#define _RISC_V_SMBIOS_DXE_H_
+
+#include <PiDxe.h>
+
+#include <Protocol/Cpu.h>
+#include <Protocol/Smbios.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/HobLib.h>
+
+#include <SmbiosProcessorSpecificData.h>
+#include <ProcessorSpecificDataHob.h>
+
+#endif
+
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
new file mode 100644
index 0000000..5624226
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
@@ -0,0 +1,63 @@
+## @file
+# RISC-V SMBIOS DXE module.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RiscVSmbiosDxe
+ MODULE_UNI_FILE = RiscVSmbiosDxe.uni
+ FILE_GUID = 5FC01647-AADD-42E1-AD99-DF4CB89F5A92
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = RiscVSmbiosBuilderEntry
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ CpuLib
+ DebugLib
+ DxeServicesTableLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+ HobLib
+
+[Sources]
+ RiscVSmbiosDxe.c
+ RiscVSmbiosDxe.h
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # Consumed
+
+[Guids]
+
+
+[Pcd]
+
+[FixedPcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
+
+[Depex]
+ gEfiSmbiosProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RiscVSmbiosDxeExtra.uni
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
new file mode 100644
index 0000000000000000000000000000000000000000..e35ce629d3c92f24ef55f9ac136059716f2a81bb
GIT binary patch
literal 1542
zcmb7^TW`}q6ok(+68~Y9z5r?yK$Q>(A(GZW1k_gIP<X0xZ7q_fvO`P%Jn+qN9ESix
zmF2z8&Y7J(yFY)ltYv}!5nr&^HnYs;Hnsb9kI~kq4t8WqyRuu$L7dx#t-wF9u|1@I
zYLD%SJ-2<@?^u1~94p5pHU#yRGPeoykzF!ArFZ3A1?^zRl-K-okFua8RIm@0Sd+TV
z%$&N8UU+Y6TA%yc3CNe$v7Wu!=&tq=EJbq$I(XbAd&tqWpg$y*l&wHWi}a4su>h&L
zTh?8I4~z`g+A~^n*lK?5Ppjvk$F5(>#9Q%e^<*94nzo!C+K5u?zPSqRrB+h<v~blG
zi<C)khLX(N+S8JgtJig`kE3#LTT89=#=RI*{<+%>HDZ(-rC*9w(3kfkbXIY7E~T&1
zKVzmmBdPulYFE|o&XjK6f*Se$XY8T$K$=!t&MMbdoW%>zNM)h2qi}rgUN>pyoKS1W
z{eqDZ$cY{7%rs%S;IBQYTPZmlp(`PiVtY&3wvY6?xT;K5oif@b*9NpA_j+I_)Dh$I
zq-3biq09Y=K=hqCrlp)#*`OA$SR2$G@2j`JrS6n@vBn-T*eR%<D?4Gl3#&L{kKUsv
z?HW_e6s$0cTB6>7RrD{^@0pQu-Q8#%rQAhipEo=;dlxSfGD|U!xp9?mRUP~-DPIna
z>EGMrPkE0@|IT2F;TXUc*%^xDmz-_mR*If~eS4gy?!!45Go)1hDJKr#lF|koa`1?e
zPxKSAW9gYvc;4ua^@-jA75j<~OuCP{pE>LArd;Q)Xo{L_y#AZ||0}PRggfsd<*m}~
a2zKb_`OM2hdU`ph{;KH}E;zS(kG}wCE9rRv
literal 0
HcmV?d00001
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
new file mode 100644
index 0000000000000000000000000000000000000000..ccfdb2aa9e6bb05715d27beb7c5d1edec7aca7cf
GIT binary patch
literal 1438
zcmZ{kTW=FV42AuS#D5s2FM!$vcmp9s(kwKhO`=@5JXN`nbVY93q%Gmc1K;uPWR(J1
z?Tp9cIX?E-^ZQrLY8LpP@dbNlGfQn@-|VqHLaV)=wXARFc4nVg_3g?UXgWv%>DKM1
zoXA*T+S(>I0wJ}Z=%#*R$6jhHo7<N42ub>LY*)6!N@MgF=X`%-dp|q38*G9-0sSfS
zOM7lF?3JA&Ux0A$oOf>1#lytDGiL55DZFI1ajY%&!J3SB{0mrYY>6ZmilA#%<~lnI
zW--sbi+hHh&S!phisc(}(6hJy;6H$K>JiKD8k7u9OHg74c36mu_)f4`!bE%fB3l8?
z2v+i!A}v5G^P~85TDhJet(=)M8}W5oHzUm*zixJ9V@Bz2IT7zIGRb`{opnSJGg+oE
zNnKVZ)>KMBlSj~?8k(#xkGPav?>!e2#=oOYVIxFg<@u7YEo((RhG+DvdkHoue9qX(
z??|kFVD*sIac1&t?y(ws{4-+6b0AJ-1qSd{NgI3Z9iaNivn%_|b6w?Z#*Nk<WPgih
z4EHJBa_qed$_;<aNt_kWg(a}+Qb!&8z*wipf_I(jRNXi5E^OEkDe+7Xt<9XEFA>UH
zXwh8>7JWzVAgQ7?R+#$*dWE^+Yxy`ma0~Vsuj18lk6PF9BxY^&El`Egaqm4=;x3(h
z4zQAqyyjN#vDL}1%pchib9HV~c*&zk?8^bCL~oIcE_EfJP5Le7EzZGTuA1wmJ2_O2
z-W$DF%H4I5-7YA-Lj>1gcR(G2pJ3C5<rPwJv=eSnJuv6iM~vzj)xjC|;wNtv(Ek5A
c_OMs?<nPeKx3WpR^40V@*ISf<C)D`=0ZK&O-T(jq
literal 0
HcmV?d00001
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 11/14]: RiscVPkg: Updates for supporting RISC-V OpenSBI
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
` (7 preceding siblings ...)
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 10/14]: RiscVPkg/SmbiosDxe: RISC-V platform generic SMBIOS DXE driver Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 12/14]: RiscVVirtPkg: Remove RISC-V virtual package Abner Chang
` (3 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
The changes are made to support RISC-V OpenSBI and RISC-V platforms
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVPkg/RiscVPkg.dec | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
index d7a3472..acf71fe 100644
--- a/RiscVPkg/RiscVPkg.dec
+++ b/RiscVPkg/RiscVPkg.dec
@@ -1,7 +1,7 @@
## @file RiscVPkg.dec
# This Package provides UEFI RISC-V modules and libraries.
#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License which accompanies this distribution.
@@ -22,6 +22,8 @@
[Includes]
Include
+ opensbi/include
+ opensbi/lib/utils/libfdt
[LibraryClasses]
@@ -32,12 +34,13 @@
gUefiRiscVMachineContextGuid = { 0xdad19cd5, 0x9d1f, 0x4f38, { 0xbc, 0xba, 0x10, 0x81, 0xe4, 0xcd, 0xb7, 0x3f}}
[PcdsFixedAtBuild]
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVSecPeiTempRamBase|0x0|UINT32|0x00001000
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVSecPeiTempRamSize|0x0|UINT32|0x00001001
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVPeiFvBase|0x0|UINT32|0x00001002
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005
+ # Processor Specific Data GUID HOB GUID
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid|{0x20, 0x72, 0xD5, 0x2F, 0xCF, 0x3C, 0x4C, 0xBC, 0xB1, 0x65, 0x94, 0x90, 0xDC, 0xF2, 0xFA, 0x93}|VOID*|0x00001000
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid|{0x0F, 0x34, 0x00, 0x92, 0x04, 0x12, 0x45, 0x4A, 0x9C, 0x11, 0xB8, 0x8B, 0xDF, 0xC6, 0xFA, 0x6F}|VOID*|0x00001001
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid|{0x5B, 0x36, 0xEA, 0x23, 0x79, 0x6D, 0x4F, 0xCF, 0x9C, 0x22, 0x25, 0xC0, 0x89, 0x8C, 0x25, 0xB9}|VOID*|0x00001002
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid|{0xBF, 0xB4, 0x6D, 0x1B, 0x7E, 0x10, 0x47, 0x44, 0xB8, 0xBD, 0xFF, 0x1E, 0xDD, 0xDF, 0x71, 0x65}|VOID*|0x00001003
+
+
#
# 1000000000
# PcdRiscVMachineTimerTickInNanoSecond = ---------------------------------------
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 12/14]: RiscVVirtPkg: Remove RISC-V virtual package
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
` (8 preceding siblings ...)
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 11/14]: RiscVPkg: Updates for supporting RISC-V OpenSBI Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 13/14]: RiscVPkg/Library: Add/Update/Remove Library instances for RISC-V platform Abner Chang
` (2 subsequent siblings)
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
The implementation of RISC-V virtual package is out of date and is not compliant with latest RISC-V specification.
We decide to remove this package for now and create a new one later.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
RiscVVirtPkg/Contributions.txt | 218 --
.../Library/PlatformBootManagerLib/MemoryTest.c | 1110 ---------
.../PlatformBootManagerLib/PlatformBootManager.c | 269 --
.../PlatformBootManagerLib/PlatformBootManager.h | 140 --
.../PlatformBootManagerLib.inf | 72 -
.../Library/PlatformBootManagerLib/PlatformData.c | 79 -
.../Library/PlatformBootManagerLib/Strings.uni | Bin 3922 -> 0 bytes
.../Library/PlatformDebugLibIoPort/DebugLib.c | 283 ---
.../PlatformDebugLibIoPort.inf | 51 -
.../Library/QemuFwCfgLib/Ia32/IoLibExAsm.nasm | 55 -
RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c | 332 ---
RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf | 50 -
.../Library/QemuFwCfgLib/QemuFwCfgPeiDxe.c | 92 -
RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c | 81 -
.../Library/QemuFwCfgLib/QemuFwCfgSecLib.inf | 48 -
.../Library/QemuFwCfgLib/X64/IoLibExAsm.nasm | 52 -
.../Library/ResetSystemLib/ResetSystemLib.c | 89 -
.../Library/ResetSystemLib/ResetSystemLib.inf | 39 -
RiscVVirtPkg/License.txt | 55 -
RiscVVirtPkg/README | 101 -
RiscVVirtPkg/RiscVVirt.fdf.inc | 38 -
RiscVVirtPkg/RiscVVirt64.dsc | 598 -----
RiscVVirtPkg/RiscVVirt64.fdf | 418 ----
RiscVVirtPkg/RiscVVirtPkg.dec | 41 -
RiscVVirtPkg/Universal/Logo/Logo.uni | Bin 1948 -> 0 bytes
| Bin 1342 -> 0 bytes
RiscVVirtPkg/Universal/Logo/RiscVLogo.bmp | Bin 12446 -> 0 bytes
RiscVVirtPkg/Universal/Logo/RiscVLogo.inf | 34 -
.../Universal/PciHostBridgeDxe/Ia32/IoFifo.S | 134 -
.../Universal/PciHostBridgeDxe/Ia32/IoFifo.asm | 140 --
RiscVVirtPkg/Universal/PciHostBridgeDxe/IoFifo.h | 176 --
.../Universal/PciHostBridgeDxe/PciHostBridge.c | 1551 ------------
.../Universal/PciHostBridgeDxe/PciHostBridge.h | 651 -----
.../PciHostBridgeDxe/PciHostBridgeDxe.inf | 65 -
.../Universal/PciHostBridgeDxe/PciRootBridgeIo.c | 2628 --------------------
.../Universal/PciHostBridgeDxe/X64/IoFifo.S | 122 -
.../Universal/PciHostBridgeDxe/X64/IoFifo.asm | 126 -
RiscVVirtPkg/Universal/PlatformPei/Cmos.c | 63 -
RiscVVirtPkg/Universal/PlatformPei/Cmos.h | 57 -
RiscVVirtPkg/Universal/PlatformPei/Fv.c | 76 -
RiscVVirtPkg/Universal/PlatformPei/MemDetect.c | 263 --
RiscVVirtPkg/Universal/PlatformPei/Platform.c | 433 ----
RiscVVirtPkg/Universal/PlatformPei/Platform.h | 111 -
RiscVVirtPkg/Universal/PlatformPei/PlatformPei.inf | 92 -
RiscVVirtPkg/Universal/PlatformPei/Xen.c | 177 --
RiscVVirtPkg/Universal/PlatformPei/Xen.h | 46 -
.../Universal/RiscVBadgingDxe/RiscVBadging.c | 107 -
.../Universal/RiscVBadgingDxe/RiscVBadging.h | 32 -
.../Universal/RiscVBadgingDxe/RiscVBadgingDxe.inf | 54 -
RiscVVirtPkg/VarStore.fdf.inc | 92 -
50 files changed, 11541 deletions(-)
delete mode 100644 RiscVVirtPkg/Contributions.txt
delete mode 100644 RiscVVirtPkg/Library/PlatformBootManagerLib/MemoryTest.c
delete mode 100644 RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
delete mode 100644 RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
delete mode 100644 RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
delete mode 100644 RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformData.c
delete mode 100644 RiscVVirtPkg/Library/PlatformBootManagerLib/Strings.uni
delete mode 100644 RiscVVirtPkg/Library/PlatformDebugLibIoPort/DebugLib.c
delete mode 100644 RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
delete mode 100644 RiscVVirtPkg/Library/QemuFwCfgLib/Ia32/IoLibExAsm.nasm
delete mode 100644 RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c
delete mode 100644 RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
delete mode 100644 RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgPeiDxe.c
delete mode 100644 RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c
delete mode 100644 RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf
delete mode 100644 RiscVVirtPkg/Library/QemuFwCfgLib/X64/IoLibExAsm.nasm
delete mode 100644 RiscVVirtPkg/Library/ResetSystemLib/ResetSystemLib.c
delete mode 100644 RiscVVirtPkg/Library/ResetSystemLib/ResetSystemLib.inf
delete mode 100644 RiscVVirtPkg/License.txt
delete mode 100644 RiscVVirtPkg/README
delete mode 100644 RiscVVirtPkg/RiscVVirt.fdf.inc
delete mode 100644 RiscVVirtPkg/RiscVVirt64.dsc
delete mode 100644 RiscVVirtPkg/RiscVVirt64.fdf
delete mode 100644 RiscVVirtPkg/RiscVVirtPkg.dec
delete mode 100644 RiscVVirtPkg/Universal/Logo/Logo.uni
delete mode 100644 RiscVVirtPkg/Universal/Logo/LogoExtra.uni
delete mode 100644 RiscVVirtPkg/Universal/Logo/RiscVLogo.bmp
delete mode 100644 RiscVVirtPkg/Universal/Logo/RiscVLogo.inf
delete mode 100644 RiscVVirtPkg/Universal/PciHostBridgeDxe/Ia32/IoFifo.S
delete mode 100644 RiscVVirtPkg/Universal/PciHostBridgeDxe/Ia32/IoFifo.asm
delete mode 100644 RiscVVirtPkg/Universal/PciHostBridgeDxe/IoFifo.h
delete mode 100644 RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridge.c
delete mode 100644 RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridge.h
delete mode 100644 RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridgeDxe.inf
delete mode 100644 RiscVVirtPkg/Universal/PciHostBridgeDxe/PciRootBridgeIo.c
delete mode 100644 RiscVVirtPkg/Universal/PciHostBridgeDxe/X64/IoFifo.S
delete mode 100644 RiscVVirtPkg/Universal/PciHostBridgeDxe/X64/IoFifo.asm
delete mode 100644 RiscVVirtPkg/Universal/PlatformPei/Cmos.c
delete mode 100644 RiscVVirtPkg/Universal/PlatformPei/Cmos.h
delete mode 100644 RiscVVirtPkg/Universal/PlatformPei/Fv.c
delete mode 100644 RiscVVirtPkg/Universal/PlatformPei/MemDetect.c
delete mode 100644 RiscVVirtPkg/Universal/PlatformPei/Platform.c
delete mode 100644 RiscVVirtPkg/Universal/PlatformPei/Platform.h
delete mode 100644 RiscVVirtPkg/Universal/PlatformPei/PlatformPei.inf
delete mode 100644 RiscVVirtPkg/Universal/PlatformPei/Xen.c
delete mode 100644 RiscVVirtPkg/Universal/PlatformPei/Xen.h
delete mode 100644 RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadging.c
delete mode 100644 RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadging.h
delete mode 100644 RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadgingDxe.inf
delete mode 100644 RiscVVirtPkg/VarStore.fdf.inc
diff --git a/RiscVVirtPkg/Contributions.txt b/RiscVVirtPkg/Contributions.txt
deleted file mode 100644
index f87cbd7..0000000
--- a/RiscVVirtPkg/Contributions.txt
+++ /dev/null
@@ -1,218 +0,0 @@
-
-======================
-= Code Contributions =
-======================
-
-To make a contribution to a TianoCore project, follow these steps.
-1. Create a change description in the format specified below to
- use in the source control commit log.
-2. Your commit message must include your "Signed-off-by" signature,
- and "Contributed-under" message.
-3. Your "Contributed-under" message explicitly states that the
- contribution is made under the terms of the specified
- contribution agreement. Your "Contributed-under" message
- must include the name of contribution agreement and version.
- For example: Contributed-under: TianoCore Contribution Agreement 1.0
- The "TianoCore Contribution Agreement" is included below in
- this document.
-4. Submit your code to the TianoCore project using the process
- that the project documents on its web page. If the process is
- not documented, then submit the code on development email list
- for the project.
-5. It is preferred that contributions are submitted using the same
- copyright license as the base project. When that is not possible,
- then contributions using the following licenses can be accepted:
- * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause
- * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause
- * MIT: http://opensource.org/licenses/MIT
- * Python-2.0: http://opensource.org/licenses/Python-2.0
- * Zlib: http://opensource.org/licenses/Zlib
-
- Contributions of code put into the public domain can also be
- accepted.
-
- Contributions using other licenses might be accepted, but further
- review will be required.
-
-=====================================================
-= Change Description / Commit Message / Patch Email =
-=====================================================
-
-Your change description should use the standard format for a
-commit message, and must include your "Signed-off-by" signature
-and the "Contributed-under" message.
-
-== Sample Change Description / Commit Message =
-
-=== Start of sample patch email message ===
-
-From: Contributor Name <contributor@example.com>
-Subject: [PATCH] CodeModule: Brief-single-line-summary
-
-Full-commit-message
-
-Contributed-under: TianoCore Contribution Agreement 1.0
-Signed-off-by: Contributor Name <contributor@example.com>
----
-
-An extra message for the patch email which will not be considered part
-of the commit message can be added here.
-
-Patch content inline or attached
-
-=== End of sample patch email message ===
-
-=== Notes for sample patch email ===
-
-* The first line of commit message is taken from the email's subject
- line following [PATCH]. The remaining portion of the commit message
- is the email's content until the '---' line.
-* git format-patch is one way to create this format
-
-=== Definitions for sample patch email ===
-
-* "CodeModule" is a short idenfier for the affected code. For
- example MdePkg, or MdeModulePkg UsbBusDxe.
-* "Brief-single-line-summary" is a short summary of the change.
-* The entire first line should be less than ~70 characters.
-* "Full-commit-message" a verbose multiple line comment describing
- the change. Each line should be less than ~70 characters.
-* "Contributed-under" explicitely states that the contribution is
- made under the terms of the contribtion agreement. This
- agreement is included below in this document.
-* "Signed-off-by" is the contributor's signature identifying them
- by their real/legal name and their email address.
-
-========================================
-= TianoCore Contribution Agreement 1.0 =
-========================================
-
-INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,
-INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE
-PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE
-TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE
-TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR
-REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE
-CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS
-OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED
-BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS
-AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE
-AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT
-USE THE CONTENT.
-
-Unless otherwise indicated, all Content made available on the TianoCore
-site is provided to you under the terms and conditions of the BSD
-License ("BSD"). A copy of the BSD License is available at
-http://opensource.org/licenses/bsd-license.php
-or when applicable, in the associated License.txt file.
-
-Certain other content may be made available under other licenses as
-indicated in or with such Content. (For example, in a License.txt file.)
-
-You accept and agree to the following terms and conditions for Your
-present and future Contributions submitted to TianoCore site. Except
-for the license granted to Intel hereunder, You reserve all right,
-title, and interest in and to Your Contributions.
-
-== SECTION 1: Definitions ==
-* "You" or "Contributor" shall mean the copyright owner or legal
- entity authorized by the copyright owner that is making a
- Contribution hereunder. All other entities that control, are
- controlled by, or are under common control with that entity are
- considered to be a single Contributor. For the purposes of this
- definition, "control" means (i) the power, direct or indirect, to
- cause the direction or management of such entity, whether by
- contract or otherwise, or (ii) ownership of fifty percent (50%)
- or more of the outstanding shares, or (iii) beneficial ownership
- of such entity.
-* "Contribution" shall mean any original work of authorship,
- including any modifications or additions to an existing work,
- that is intentionally submitted by You to the TinaoCore site for
- inclusion in, or documentation of, any of the Content. For the
- purposes of this definition, "submitted" means any form of
- electronic, verbal, or written communication sent to the
- TianoCore site or its representatives, including but not limited
- to communication on electronic mailing lists, source code
- control systems, and issue tracking systems that are managed by,
- or on behalf of, the TianoCore site for the purpose of
- discussing and improving the Content, but excluding
- communication that is conspicuously marked or otherwise
- designated in writing by You as "Not a Contribution."
-
-== SECTION 2: License for Contributions ==
-* Contributor hereby agrees that redistribution and use of the
- Contribution in source and binary forms, with or without
- modification, are permitted provided that the following
- conditions are met:
-** Redistributions of source code must retain the Contributor's
- copyright notice, this list of conditions and the following
- disclaimer.
-** Redistributions in binary form must reproduce the Contributor's
- copyright notice, this list of conditions and the following
- disclaimer in the documentation and/or other materials provided
- with the distribution.
-* Disclaimer. None of the names of Contributor, Intel, or the names
- of their respective contributors may be used to endorse or
- promote products derived from this software without specific
- prior written permission.
-* Contributor grants a license (with the right to sublicense) under
- claims of Contributor's patents that Contributor can license that
- are infringed by the Contribution (as delivered by Contributor) to
- make, use, distribute, sell, offer for sale, and import the
- Contribution and derivative works thereof solely to the minimum
- extent necessary for licensee to exercise the granted copyright
- license; this patent license applies solely to those portions of
- the Contribution that are unmodified. No hardware per se is
- licensed.
-* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE
- CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY
- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE
- CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
- DAMAGE.
-
-== SECTION 3: Representations ==
-* You represent that You are legally entitled to grant the above
- license. If your employer(s) has rights to intellectual property
- that You create that includes Your Contributions, You represent
- that You have received permission to make Contributions on behalf
- of that employer, that Your employer has waived such rights for
- Your Contributions.
-* You represent that each of Your Contributions is Your original
- creation (see Section 4 for submissions on behalf of others).
- You represent that Your Contribution submissions include complete
- details of any third-party license or other restriction
- (including, but not limited to, related patents and trademarks)
- of which You are personally aware and which are associated with
- any part of Your Contributions.
-
-== SECTION 4: Third Party Contributions ==
-* Should You wish to submit work that is not Your original creation,
- You may submit it to TianoCore site separately from any
- Contribution, identifying the complete details of its source
- and of any license or other restriction (including, but not
- limited to, related patents, trademarks, and license agreements)
- of which You are personally aware, and conspicuously marking the
- work as "Submitted on behalf of a third-party: [named here]".
-
-== SECTION 5: Miscellaneous ==
-* Applicable Laws. Any claims arising under or relating to this
- Agreement shall be governed by the internal substantive laws of
- the State of Delaware or federal courts located in Delaware,
- without regard to principles of conflict of laws.
-* Language. This Agreement is in the English language only, which
- language shall be controlling in all respects, and all versions
- of this Agreement in any other language shall be for accommodation
- only and shall not be binding. All communications and notices made
- or given pursuant to this Agreement, and all documentation and
- support to be provided, unless otherwise noted, shall be in the
- English language.
-
diff --git a/RiscVVirtPkg/Library/PlatformBootManagerLib/MemoryTest.c b/RiscVVirtPkg/Library/PlatformBootManagerLib/MemoryTest.c
deleted file mode 100644
index 240c177..0000000
--- a/RiscVVirtPkg/Library/PlatformBootManagerLib/MemoryTest.c
+++ /dev/null
@@ -1,1110 +0,0 @@
-/** @file
- Perform the RISC-V platform memory test
-
-Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "PlatformBootManager.h"
-
-EFI_HII_HANDLE gStringPackHandle = NULL;
-EFI_GUID mPlatformBootManagerStringPackGuid = {
- 0x154dd51, 0x9079, 0x4a10, { 0x89, 0x5c, 0x9c, 0x7, 0x72, 0x81, 0x57, 0x88 }
- };
-// extern UINT8 BdsDxeStrings[];
-
-//
-// BDS Platform Functions
-//
-/**
-
- Show progress bar with title above it. It only works in Graphics mode.
-
- @param TitleForeground Foreground color for Title.
- @param TitleBackground Background color for Title.
- @param Title Title above progress bar.
- @param ProgressColor Progress bar color.
- @param Progress Progress (0-100)
- @param PreviousValue The previous value of the progress.
-
- @retval EFI_STATUS Success update the progress bar
-
-**/
-EFI_STATUS
-PlatformBootManagerShowProgress (
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
- IN CHAR16 *Title,
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
- IN UINTN Progress,
- IN UINTN PreviousValue
- )
-{
- EFI_STATUS Status;
- EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;
- EFI_UGA_DRAW_PROTOCOL *UgaDraw;
- UINT32 SizeOfX;
- UINT32 SizeOfY;
- UINT32 ColorDepth;
- UINT32 RefreshRate;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color;
- UINTN BlockHeight;
- UINTN BlockWidth;
- UINTN BlockNum;
- UINTN PosX;
- UINTN PosY;
- UINTN Index;
-
- if (Progress > 100) {
- return EFI_INVALID_PARAMETER;
- }
-
- UgaDraw = NULL;
- Status = gBS->HandleProtocol (
- gST->ConsoleOutHandle,
- &gEfiGraphicsOutputProtocolGuid,
- (VOID **) &GraphicsOutput
- );
- if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) {
- GraphicsOutput = NULL;
-
- Status = gBS->HandleProtocol (
- gST->ConsoleOutHandle,
- &gEfiUgaDrawProtocolGuid,
- (VOID **) &UgaDraw
- );
- }
- if (EFI_ERROR (Status)) {
- return EFI_UNSUPPORTED;
- }
-
- SizeOfX = 0;
- SizeOfY = 0;
- if (GraphicsOutput != NULL) {
- SizeOfX = GraphicsOutput->Mode->Info->HorizontalResolution;
- SizeOfY = GraphicsOutput->Mode->Info->VerticalResolution;
- } else if (UgaDraw != NULL) {
- Status = UgaDraw->GetMode (
- UgaDraw,
- &SizeOfX,
- &SizeOfY,
- &ColorDepth,
- &RefreshRate
- );
- if (EFI_ERROR (Status)) {
- return EFI_UNSUPPORTED;
- }
- } else {
- return EFI_UNSUPPORTED;
- }
-
- BlockWidth = SizeOfX / 100;
- BlockHeight = SizeOfY / 50;
-
- BlockNum = Progress;
-
- PosX = 0;
- PosY = SizeOfY * 48 / 50;
-
- if (BlockNum == 0) {
- //
- // Clear progress area
- //
- SetMem (&Color, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0);
-
- if (GraphicsOutput != NULL) {
- Status = GraphicsOutput->Blt (
- GraphicsOutput,
- &Color,
- EfiBltVideoFill,
- 0,
- 0,
- 0,
- PosY - EFI_GLYPH_HEIGHT - 1,
- SizeOfX,
- SizeOfY - (PosY - EFI_GLYPH_HEIGHT - 1),
- SizeOfX * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
- );
- } else if (FeaturePcdGet (PcdUgaConsumeSupport)) {
- Status = UgaDraw->Blt (
- UgaDraw,
- (EFI_UGA_PIXEL *) &Color,
- EfiUgaVideoFill,
- 0,
- 0,
- 0,
- PosY - EFI_GLYPH_HEIGHT - 1,
- SizeOfX,
- SizeOfY - (PosY - EFI_GLYPH_HEIGHT - 1),
- SizeOfX * sizeof (EFI_UGA_PIXEL)
- );
- } else {
- return EFI_UNSUPPORTED;
- }
- }
- //
- // Show progress by drawing blocks
- //
- for (Index = PreviousValue; Index < BlockNum; Index++) {
- PosX = Index * BlockWidth;
- if (GraphicsOutput != NULL) {
- Status = GraphicsOutput->Blt (
- GraphicsOutput,
- &ProgressColor,
- EfiBltVideoFill,
- 0,
- 0,
- PosX,
- PosY,
- BlockWidth - 1,
- BlockHeight,
- (BlockWidth) * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
- );
- } else if (FeaturePcdGet (PcdUgaConsumeSupport)) {
- Status = UgaDraw->Blt (
- UgaDraw,
- (EFI_UGA_PIXEL *) &ProgressColor,
- EfiUgaVideoFill,
- 0,
- 0,
- PosX,
- PosY,
- BlockWidth - 1,
- BlockHeight,
- (BlockWidth) * sizeof (EFI_UGA_PIXEL)
- );
- } else {
- return EFI_UNSUPPORTED;
- }
- }
-
- PrintXY (
- (SizeOfX - StrLen (Title) * EFI_GLYPH_WIDTH) / 2,
- PosY - EFI_GLYPH_HEIGHT - 1,
- &TitleForeground,
- &TitleBackground,
- Title
- );
-
- return EFI_SUCCESS;
-}
-
-/**
- Perform the memory test base on the memory test intensive level,
- and update the memory resource.
-
- @param Level The memory test intensive level.
-
- @retval EFI_STATUS Success test all the system memory and update
- the memory resource
-
-**/
-EFI_STATUS
-PlatformBootManagerMemoryTest (
- IN EXTENDMEM_COVERAGE_LEVEL Level
- )
-{
- EFI_STATUS Status;
- EFI_STATUS KeyStatus;
- EFI_STATUS InitStatus;
- EFI_STATUS ReturnStatus;
- BOOLEAN RequireSoftECCInit;
- EFI_GENERIC_MEMORY_TEST_PROTOCOL *GenMemoryTest;
- UINT64 TestedMemorySize;
- UINT64 TotalMemorySize;
- UINTN TestPercent;
- UINT64 PreviousValue;
- BOOLEAN ErrorOut;
- BOOLEAN TestAbort;
- EFI_INPUT_KEY Key;
- CHAR16 StrPercent[80];
- CHAR16 *StrTotalMemory;
- CHAR16 *Pos;
- CHAR16 *TmpStr;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL Foreground;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL Background;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color;
- UINT32 TempData;
- UINTN StrTotalMemorySize;
-
- ReturnStatus = EFI_SUCCESS;
- ZeroMem (&Key, sizeof (EFI_INPUT_KEY));
-
- StrTotalMemorySize = 128;
- Pos = AllocateZeroPool (StrTotalMemorySize);
- ASSERT (Pos != NULL);
-
- if (gStringPackHandle == NULL) {
- gStringPackHandle = HiiAddPackages (
- &mPlatformBootManagerStringPackGuid,
- gImageHandle,
- PlatformBootManagerLibStrings,
- NULL
- );
- ASSERT (gStringPackHandle != NULL);
- }
-
- StrTotalMemory = Pos;
-
- TestedMemorySize = 0;
- TotalMemorySize = 0;
- PreviousValue = 0;
- ErrorOut = FALSE;
- TestAbort = FALSE;
-
- SetMem (&Foreground, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);
- SetMem (&Background, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0);
- SetMem (&Color, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);
-
- RequireSoftECCInit = FALSE;
-
- Status = gBS->LocateProtocol (
- &gEfiGenericMemTestProtocolGuid,
- NULL,
- (VOID **) &GenMemoryTest
- );
- if (EFI_ERROR (Status)) {
- FreePool (Pos);
- return EFI_SUCCESS;
- }
-
- InitStatus = GenMemoryTest->MemoryTestInit (
- GenMemoryTest,
- Level,
- &RequireSoftECCInit
- );
- if (InitStatus == EFI_NO_MEDIA) {
- //
- // The PEI codes also have the relevant memory test code to check the memory,
- // it can select to test some range of the memory or all of them. If PEI code
- // checks all the memory, this BDS memory test will has no not-test memory to
- // do the test, and then the status of EFI_NO_MEDIA will be returned by
- // "MemoryTestInit". So it does not need to test memory again, just return.
- //
- FreePool (Pos);
- return EFI_SUCCESS;
- }
-
- if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) {
- TmpStr = HiiGetString (gStringPackHandle, STRING_TOKEN (STR_ESC_TO_SKIP_MEM_TEST), NULL);
-
- if (TmpStr != NULL) {
- PrintXY (10, 10, NULL, NULL, TmpStr);
- FreePool (TmpStr);
- }
- } else {
- DEBUG ((EFI_D_INFO, "Enter memory test.\n"));
- }
- do {
- Status = GenMemoryTest->PerformMemoryTest (
- GenMemoryTest,
- &TestedMemorySize,
- &TotalMemorySize,
- &ErrorOut,
- TestAbort
- );
- if (ErrorOut && (Status == EFI_DEVICE_ERROR)) {
- TmpStr = HiiGetString (gStringPackHandle, STRING_TOKEN (STR_SYSTEM_MEM_ERROR), NULL);
- if (TmpStr != NULL) {
- PrintXY (10, 10, NULL, NULL, TmpStr);
- FreePool (TmpStr);
- }
-
- ASSERT (0);
- }
-
- if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) {
- TempData = (UINT32) DivU64x32 (TotalMemorySize, 16);
- TestPercent = (UINTN) DivU64x32 (
- DivU64x32 (MultU64x32 (TestedMemorySize, 100), 16),
- TempData
- );
- if (TestPercent != PreviousValue) {
- UnicodeValueToString (StrPercent, 0, TestPercent, 0);
- TmpStr = HiiGetString (gStringPackHandle, STRING_TOKEN (STR_MEMORY_TEST_PERCENT), NULL);
- if (TmpStr != NULL) {
- //
- // TmpStr size is 64, StrPercent is reserved to 16.
- //
- StrnCatS (
- StrPercent,
- sizeof (StrPercent) / sizeof (CHAR16),
- TmpStr,
- sizeof (StrPercent) / sizeof (CHAR16) - StrLen (StrPercent) - 1
- );
- PrintXY (10, 10, NULL, NULL, StrPercent);
- FreePool (TmpStr);
- }
-
- TmpStr = HiiGetString (gStringPackHandle, STRING_TOKEN (STR_PERFORM_MEM_TEST), NULL);
- if (TmpStr != NULL) {
- PlatformBootManagerShowProgress (
- Foreground,
- Background,
- TmpStr,
- Color,
- TestPercent,
- (UINTN) PreviousValue
- );
- FreePool (TmpStr);
- }
- }
-
- PreviousValue = TestPercent;
- } else {
- DEBUG ((EFI_D_INFO, "Perform memory test (ESC to skip).\n"));
- }
-
- if (!PcdGetBool (PcdConInConnectOnDemand)) {
- KeyStatus = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
- if (!EFI_ERROR (KeyStatus) && (Key.ScanCode == SCAN_ESC)) {
- if (!RequireSoftECCInit) {
- if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) {
- TmpStr = HiiGetString (gStringPackHandle, STRING_TOKEN (STR_PERFORM_MEM_TEST), NULL);
- if (TmpStr != NULL) {
- PlatformBootManagerShowProgress (
- Foreground,
- Background,
- TmpStr,
- Color,
- 100,
- (UINTN) PreviousValue
- );
- FreePool (TmpStr);
- }
-
- PrintXY (10, 10, NULL, NULL, L"100");
- }
- Status = GenMemoryTest->Finished (GenMemoryTest);
- goto Done;
- }
-
- TestAbort = TRUE;
- }
- }
- } while (Status != EFI_NOT_FOUND);
-
- Status = GenMemoryTest->Finished (GenMemoryTest);
-
-Done:
- if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) {
- UnicodeValueToString (StrTotalMemory, COMMA_TYPE, TotalMemorySize, 0);
- if (StrTotalMemory[0] == L',') {
- StrTotalMemory++;
- StrTotalMemorySize -= sizeof (CHAR16);
- }
-
- TmpStr = HiiGetString (gStringPackHandle, STRING_TOKEN (STR_MEM_TEST_COMPLETED), NULL);
- if (TmpStr != NULL) {
- StrnCatS (
- StrTotalMemory,
- StrTotalMemorySize / sizeof (CHAR16),
- TmpStr,
- StrTotalMemorySize / sizeof (CHAR16) - StrLen (StrTotalMemory) - 1
- );
- FreePool (TmpStr);
- }
-
- PrintXY (10, 10, NULL, NULL, StrTotalMemory);
- PlatformBootManagerShowProgress (
- Foreground,
- Background,
- StrTotalMemory,
- Color,
- 100,
- (UINTN) PreviousValue
- );
-
- } else {
- DEBUG ((EFI_D_INFO, "%d bytes of system memory tested OK\r\n", TotalMemorySize));
- }
-
- FreePool (Pos);
- return ReturnStatus;
-}
-
-/**
- Convert a *.BMP graphics image to a GOP blt buffer. If a NULL Blt buffer
- is passed in a GopBlt buffer will be allocated by this routine. If a GopBlt
- buffer is passed in it will be used if it is big enough.
-
- @param BmpImage Pointer to BMP file
- @param BmpImageSize Number of bytes in BmpImage
- @param GopBlt Buffer containing GOP version of BmpImage.
- @param GopBltSize Size of GopBlt in bytes.
- @param PixelHeight Height of GopBlt/BmpImage in pixels
- @param PixelWidth Width of GopBlt/BmpImage in pixels
-
- @retval EFI_SUCCESS GopBlt and GopBltSize are returned.
- @retval EFI_UNSUPPORTED BmpImage is not a valid *.BMP image
- @retval EFI_BUFFER_TOO_SMALL The passed in GopBlt buffer is not big enough.
- GopBltSize will contain the required size.
- @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate.
-
-**/
-EFI_STATUS
-PlatformBootManagerConvertBmpToGopBlt (
- IN VOID *BmpImage,
- IN UINTN BmpImageSize,
- IN OUT VOID **GopBlt,
- IN OUT UINTN *GopBltSize,
- OUT UINTN *PixelHeight,
- OUT UINTN *PixelWidth
- )
-{
- UINT8 *Image;
- UINT8 *ImageHeader;
- BMP_IMAGE_HEADER *BmpHeader;
- BMP_COLOR_MAP *BmpColorMap;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;
- UINT64 BltBufferSize;
- UINTN Index;
- UINTN Height;
- UINTN Width;
- UINTN ImageIndex;
- UINT32 DataSizePerLine;
- BOOLEAN IsAllocated;
- UINT32 ColorMapNum;
-
- if (sizeof (BMP_IMAGE_HEADER) > BmpImageSize) {
- DEBUG ((DEBUG_INFO, "BMP_IMAGE_HEADER) > BmpImageSize.\n"));
- return EFI_INVALID_PARAMETER;
- }
-
- BmpHeader = (BMP_IMAGE_HEADER *) BmpImage;
-
- if (BmpHeader->CharB != 'B' || BmpHeader->CharM != 'M') {
- DEBUG ((DEBUG_INFO, "(BmpHeader->CharB != 'B' || BmpHeader->CharM != 'M').\n"));
- return EFI_UNSUPPORTED;
- }
-
- //
- // Doesn't support compress.
- //
- if (BmpHeader->CompressionType != 0) {
- DEBUG ((DEBUG_INFO, "It's compressed! We dont support.\n"));
- return EFI_UNSUPPORTED;
- }
-
- //
- // Only support BITMAPINFOHEADER format.
- // BITMAPFILEHEADER + BITMAPINFOHEADER = BMP_IMAGE_HEADER
- //
- if (BmpHeader->HeaderSize != sizeof (BMP_IMAGE_HEADER) - OFFSET_OF(BMP_IMAGE_HEADER, HeaderSize)) {
- DEBUG ((DEBUG_INFO, "Only support BITMAPINFOHEADER.\n"));
- return EFI_UNSUPPORTED;
- }
-
- //
- // The data size in each line must be 4 byte alignment.
- //
- DataSizePerLine = ((BmpHeader->PixelWidth * BmpHeader->BitPerPixel + 31) >> 3) & (~0x3);
- BltBufferSize = MultU64x32 (DataSizePerLine, BmpHeader->PixelHeight);
- if (BltBufferSize > (UINT32) ~0) {
- DEBUG ((DEBUG_INFO, "The data size in each line must be 4 byte alignment.\n"));
- return EFI_INVALID_PARAMETER;
- }
-
- if ((BmpHeader->Size != BmpImageSize) ||
- (BmpHeader->Size < BmpHeader->ImageOffset) ||
- (BmpHeader->Size - BmpHeader->ImageOffset != BmpHeader->PixelHeight * DataSizePerLine)) {
- DEBUG ((DEBUG_INFO, "BmpHeader->Size problem.\n"));
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Calculate Color Map offset in the image.
- //
- Image = BmpImage;
- BmpColorMap = (BMP_COLOR_MAP *) (Image + sizeof (BMP_IMAGE_HEADER));
- if (BmpHeader->ImageOffset < sizeof (BMP_IMAGE_HEADER)) {
- DEBUG ((DEBUG_INFO, "BmpHeader->ImageOffset < sizeof (BMP_IMAGE_HEADER)\n"));
- return EFI_INVALID_PARAMETER;
- }
-
- if (BmpHeader->ImageOffset > sizeof (BMP_IMAGE_HEADER)) {
- switch (BmpHeader->BitPerPixel) {
- case 1:
- ColorMapNum = 2;
- break;
- case 4:
- ColorMapNum = 16;
- break;
- case 8:
- ColorMapNum = 256;
- break;
- default:
- ColorMapNum = 0;
- break;
- }
- //
- // BMP file may has padding data between the bmp header section and the bmp data section.
- //
- if (BmpHeader->ImageOffset - sizeof (BMP_IMAGE_HEADER) < sizeof (BMP_COLOR_MAP) * ColorMapNum) {
- DEBUG ((DEBUG_INFO, "(BmpHeader->ImageOffset - sizeof (BMP_IMAGE_HEADER) < sizeof (BMP_COLOR_MAP) * ColorMapNum)\n"));
- return EFI_INVALID_PARAMETER;
- }
- }
-
- //
- // Calculate graphics image data address in the image
- //
- Image = ((UINT8 *) BmpImage) + BmpHeader->ImageOffset;
- ImageHeader = Image;
-
- //
- // Calculate the BltBuffer needed size.
- //
- BltBufferSize = MultU64x32 ((UINT64) BmpHeader->PixelWidth, BmpHeader->PixelHeight);
- //
- // Ensure the BltBufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL) doesn't overflow
- //
- if (BltBufferSize > DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {
- return EFI_UNSUPPORTED;
- }
- BltBufferSize = MultU64x32 (BltBufferSize, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));
-
- IsAllocated = FALSE;
- if (*GopBlt == NULL) {
- //
- // GopBlt is not allocated by caller.
- //
- *GopBltSize = (UINTN) BltBufferSize;
- *GopBlt = AllocatePool (*GopBltSize);
- IsAllocated = TRUE;
- if (*GopBlt == NULL) {
- DEBUG ((DEBUG_INFO, "EFI_OUT_OF_RESOURCES\n"));
- return EFI_OUT_OF_RESOURCES;
- }
- } else {
- //
- // GopBlt has been allocated by caller.
- //
- if (*GopBltSize < (UINTN) BltBufferSize) {
- *GopBltSize = (UINTN) BltBufferSize;
- DEBUG ((DEBUG_INFO, "EEFI_BUFFER_TOO_SMALL\n"));
- return EFI_BUFFER_TOO_SMALL;
- }
- }
-
- *PixelWidth = BmpHeader->PixelWidth;
- *PixelHeight = BmpHeader->PixelHeight;
-
- //
- // Convert image from BMP to Blt buffer format
- //
- BltBuffer = *GopBlt;
- for (Height = 0; Height < BmpHeader->PixelHeight; Height++) {
- Blt = &BltBuffer[(BmpHeader->PixelHeight - Height - 1) * BmpHeader->PixelWidth];
- for (Width = 0; Width < BmpHeader->PixelWidth; Width++, Image++, Blt++) {
- switch (BmpHeader->BitPerPixel) {
- case 1:
- //
- // Convert 1-bit (2 colors) BMP to 24-bit color
- //
- for (Index = 0; Index < 8 && Width < BmpHeader->PixelWidth; Index++) {
- Blt->Red = BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Red;
- Blt->Green = BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Green;
- Blt->Blue = BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Blue;
- Blt++;
- Width++;
- }
-
- Blt--;
- Width--;
- break;
-
- case 4:
- //
- // Convert 4-bit (16 colors) BMP Palette to 24-bit color
- //
- Index = (*Image) >> 4;
- Blt->Red = BmpColorMap[Index].Red;
- Blt->Green = BmpColorMap[Index].Green;
- Blt->Blue = BmpColorMap[Index].Blue;
- if (Width < (BmpHeader->PixelWidth - 1)) {
- Blt++;
- Width++;
- Index = (*Image) & 0x0f;
- Blt->Red = BmpColorMap[Index].Red;
- Blt->Green = BmpColorMap[Index].Green;
- Blt->Blue = BmpColorMap[Index].Blue;
- }
- break;
-
- case 8:
- //
- // Convert 8-bit (256 colors) BMP Palette to 24-bit color
- //
- Blt->Red = BmpColorMap[*Image].Red;
- Blt->Green = BmpColorMap[*Image].Green;
- Blt->Blue = BmpColorMap[*Image].Blue;
- break;
-
- case 24:
- //
- // It is 24-bit BMP.
- //
- Blt->Blue = *Image++;
- Blt->Green = *Image++;
- Blt->Red = *Image;
- break;
-
- default:
- //
- // Other bit format BMP is not supported.
- //
- if (IsAllocated) {
- FreePool (*GopBlt);
- *GopBlt = NULL;
- }
- DEBUG ((DEBUG_INFO, "Other bit format BMP is not supported.\n"));
- return EFI_UNSUPPORTED;
- break;
- };
-
- }
-
- ImageIndex = (UINTN) (Image - ImageHeader);
- if ((ImageIndex % 4) != 0) {
- //
- // Bmp Image starts each row on a 32-bit boundary!
- //
- Image = Image + (4 - (ImageIndex % 4));
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Use SystemTable Conout to stop video based Simple Text Out consoles from going
- to the video device. Put up LogoFile on every video device that is a console.
-
- @param[in] LogoFile File name of logo to display on the center of the screen.
-
- @retval EFI_SUCCESS ConsoleControl has been flipped to graphics and logo displayed.
- @retval EFI_UNSUPPORTED Logo not found
-
-**/
-EFI_STATUS
-PlatformBootManagerEnableQuietBoot (
- IN EFI_GUID *LogoFile
- )
-{
- EFI_STATUS Status;
- EFI_OEM_BADGING_PROTOCOL *Badging;
- UINT32 SizeOfX;
- UINT32 SizeOfY;
- INTN DestX;
- INTN DestY;
- UINT8 *ImageData;
- UINTN ImageSize;
- UINTN BltSize;
- UINT32 Instance;
- EFI_BADGING_FORMAT Format;
- EFI_BADGING_DISPLAY_ATTRIBUTE Attribute;
- UINTN CoordinateX;
- UINTN CoordinateY;
- UINTN Height;
- UINTN Width;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;
- EFI_UGA_DRAW_PROTOCOL *UgaDraw;
- UINT32 ColorDepth;
- UINT32 RefreshRate;
- EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;
- EFI_BOOT_LOGO_PROTOCOL *BootLogo;
- UINTN NumberOfLogos;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL *LogoBlt;
- UINTN LogoDestX;
- UINTN LogoDestY;
- UINTN LogoHeight;
- UINTN LogoWidth;
- UINTN NewDestX;
- UINTN NewDestY;
- UINTN NewHeight;
- UINTN NewWidth;
- UINT64 BufferSize;
-
- UgaDraw = NULL;
- //
- // Try to open GOP first
- //
- Status = gBS->HandleProtocol (gST->ConsoleOutHandle, &gEfiGraphicsOutputProtocolGuid, (VOID **) &GraphicsOutput);
- if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) {
- DEBUG ((DEBUG_INFO, "No GOP.\n"));
- GraphicsOutput = NULL;
- //
- // Open GOP failed, try to open UGA
- //
- Status = gBS->HandleProtocol (gST->ConsoleOutHandle, &gEfiUgaDrawProtocolGuid, (VOID **) &UgaDraw);
- }
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "No GOP or UGA.\n"));
- return EFI_UNSUPPORTED;
- }
-
- //
- // Try to open Boot Logo Protocol.
- //
- BootLogo = NULL;
- gBS->LocateProtocol (&gEfiBootLogoProtocolGuid, NULL, (VOID **) &BootLogo);
-
- //
- // Erase Cursor from screen
- //
- gST->ConOut->EnableCursor (gST->ConOut, FALSE);
-
- Badging = NULL;
- Status = gBS->LocateProtocol (&gEfiOEMBadgingProtocolGuid, NULL, (VOID **) &Badging);
- if (Badging != NULL) {
- DEBUG ((DEBUG_INFO, "OEM Badging existing!\n"));
- }
- if (GraphicsOutput != NULL) {
- SizeOfX = GraphicsOutput->Mode->Info->HorizontalResolution;
- SizeOfY = GraphicsOutput->Mode->Info->VerticalResolution;
-
- } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {
- Status = UgaDraw->GetMode (UgaDraw, &SizeOfX, &SizeOfY, &ColorDepth, &RefreshRate);
- if (EFI_ERROR (Status)) {
- return EFI_UNSUPPORTED;
- }
- } else {
- return EFI_UNSUPPORTED;
- }
-
- Blt = NULL;
- NumberOfLogos = 0;
- LogoDestX = 0;
- LogoDestY = 0;
- LogoHeight = 0;
- LogoWidth = 0;
- NewDestX = 0;
- NewDestY = 0;
- NewHeight = 0;
- NewWidth = 0;
- Instance = 0;
- while (1) {
- ImageData = NULL;
- ImageSize = 0;
-
- if (Badging != NULL) {
- //
- // Get image from OEMBadging protocol.
- //
- Status = Badging->GetImage (
- Badging,
- &Instance,
- &Format,
- &ImageData,
- &ImageSize,
- &Attribute,
- &CoordinateX,
- &CoordinateY
- );
- if (EFI_ERROR (Status)) {
- goto Done;
- }
- DEBUG ((DEBUG_INFO, "Badging->GetImage: Image size %x Attribute %x\n", ImageSize, Attribute));
-
- //
- // Currently only support BMP format.
- //
- if (Format != EfiBadgingFormatBMP) {
- if (ImageData != NULL) {
- FreePool (ImageData);
- }
- continue;
- }
- } else {
- //
- // Get the specified image from FV.
- //
- DEBUG ((DEBUG_INFO, "Load logo file.\n"));
- Status = GetSectionFromAnyFv (LogoFile, EFI_SECTION_RAW, 0, (VOID **) &ImageData, &ImageSize);
- if (EFI_ERROR (Status)) {
- return EFI_UNSUPPORTED;
- }
-
- CoordinateX = 0;
- CoordinateY = 0;
- if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) {
- DEBUG ((DEBUG_INFO, "Logo enable only = FALSE.\n"));
- Attribute = EfiBadgingDisplayAttributeCenter;
- } else {
- DEBUG ((DEBUG_INFO, "Logo enable only = TRUE.\n"));
- Attribute = EfiBadgingDisplayAttributeCustomized;
- }
- }
-
- if (Blt != NULL) {
- FreePool (Blt);
- }
- Blt = NULL;
- Status = PlatformBootManagerConvertBmpToGopBlt (
- ImageData,
- ImageSize,
- (VOID **) &Blt,
- &BltSize,
- &Height,
- &Width
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "PlatformBootManagerConvertBmpToGopBlt FALSE.\n"));
- FreePool (ImageData);
-
- if (Badging == NULL) {
- return Status;
- } else {
- continue;
- }
- }
- DEBUG ((DEBUG_INFO, "Badging->GetImage: Image H: %d, Width:%d\n", Height, Width));
-
- //
- // Calculate the display position according to Attribute.
- //
- switch (Attribute) {
- case EfiBadgingDisplayAttributeLeftTop:
- DestX = CoordinateX;
- DestY = CoordinateY;
- break;
-
- case EfiBadgingDisplayAttributeCenterTop:
- DestX = (SizeOfX - Width) / 2;
- DestY = CoordinateY;
- break;
-
- case EfiBadgingDisplayAttributeRightTop:
- DestX = (SizeOfX - Width - CoordinateX);
- DestY = CoordinateY;;
- break;
-
- case EfiBadgingDisplayAttributeCenterRight:
- DestX = (SizeOfX - Width - CoordinateX);
- DestY = (SizeOfY - Height) / 2;
- break;
-
- case EfiBadgingDisplayAttributeRightBottom:
- DestX = (SizeOfX - Width - CoordinateX);
- DestY = (SizeOfY - Height - CoordinateY);
- break;
-
- case EfiBadgingDisplayAttributeCenterBottom:
- DestX = (SizeOfX - Width) / 2;
- DestY = (SizeOfY - Height - CoordinateY);
- break;
-
- case EfiBadgingDisplayAttributeLeftBottom:
- DestX = CoordinateX;
- DestY = (SizeOfY - Height - CoordinateY);
- break;
-
- case EfiBadgingDisplayAttributeCenterLeft:
- DestX = CoordinateX;
- DestY = (SizeOfY - Height) / 2;
- break;
-
- case EfiBadgingDisplayAttributeCenter:
- DestX = (SizeOfX - Width) / 2;
- DestY = (SizeOfY - Height) / 2;
- break;
-
- case EfiBadgingDisplayAttributeCustomized:
- DestX = CoordinateX;
- DestY = CoordinateY;
- break;
-
- default:
- DestX = CoordinateX;
- DestY = CoordinateY;
- break;
- }
-
- if ((DestX >= 0) && (DestY >= 0)) {
- if (GraphicsOutput != NULL) {
- Status = GraphicsOutput->Blt (
- GraphicsOutput,
- Blt,
- EfiBltBufferToVideo,
- 0,
- 0,
- (UINTN) DestX,
- (UINTN) DestY,
- Width,
- Height,
- Width * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
- );
- } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {
- Status = UgaDraw->Blt (
- UgaDraw,
- (EFI_UGA_PIXEL *) Blt,
- EfiUgaBltBufferToVideo,
- 0,
- 0,
- (UINTN) DestX,
- (UINTN) DestY,
- Width,
- Height,
- Width * sizeof (EFI_UGA_PIXEL)
- );
- } else {
- Status = EFI_UNSUPPORTED;
- }
-
- //
- // Report displayed Logo information.
- //
- if (!EFI_ERROR (Status)) {
- NumberOfLogos++;
-
- if (LogoWidth == 0) {
- //
- // The first Logo.
- //
- LogoDestX = (UINTN) DestX;
- LogoDestY = (UINTN) DestY;
- LogoWidth = Width;
- LogoHeight = Height;
- } else {
- //
- // Merge new logo with old one.
- //
- NewDestX = MIN ((UINTN) DestX, LogoDestX);
- NewDestY = MIN ((UINTN) DestY, LogoDestY);
- NewWidth = MAX ((UINTN) DestX + Width, LogoDestX + LogoWidth) - NewDestX;
- NewHeight = MAX ((UINTN) DestY + Height, LogoDestY + LogoHeight) - NewDestY;
-
- LogoDestX = NewDestX;
- LogoDestY = NewDestY;
- LogoWidth = NewWidth;
- LogoHeight = NewHeight;
- }
- }
- }
-
- FreePool (ImageData);
-
- if (Badging == NULL) {
- break;
- }
- }
-
-Done:
- if (BootLogo == NULL || NumberOfLogos == 0) {
- //
- // No logo displayed.
- //
- if (Blt != NULL) {
- FreePool (Blt);
- }
-
- return Status;
- }
-
- //
- // Advertise displayed Logo information.
- //
- if (NumberOfLogos == 1) {
- //
- // Only one logo displayed, use its Blt buffer directly for BootLogo protocol.
- //
- LogoBlt = Blt;
- Status = EFI_SUCCESS;
- } else {
- //
- // More than one Logo displayed, get merged BltBuffer using VideoToBuffer operation.
- //
- if (Blt != NULL) {
- FreePool (Blt);
- }
-
- //
- // Ensure the LogoHeight * LogoWidth doesn't overflow
- //
- if (LogoHeight > DivU64x64Remainder ((UINTN) ~0, LogoWidth, NULL)) {
- return EFI_UNSUPPORTED;
- }
- BufferSize = MultU64x64 (LogoWidth, LogoHeight);
-
- //
- // Ensure the BufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL) doesn't overflow
- //
- if (BufferSize > DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {
- return EFI_UNSUPPORTED;
- }
-
- LogoBlt = AllocateZeroPool ((UINTN)BufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));
- if (LogoBlt == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- if (GraphicsOutput != NULL) {
- DEBUG ((DEBUG_INFO, "GraphicsOutput->Blt.\n"));
- Status = GraphicsOutput->Blt (
- GraphicsOutput,
- LogoBlt,
- EfiBltVideoToBltBuffer,
- LogoDestX,
- LogoDestY,
- 0,
- 0,
- LogoWidth,
- LogoHeight,
- LogoWidth * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
- );
- } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {
- DEBUG ((DEBUG_INFO, " UgaDraw->Blt.\n"));
- Status = UgaDraw->Blt (
- UgaDraw,
- (EFI_UGA_PIXEL *) LogoBlt,
- EfiUgaVideoToBltBuffer,
- LogoDestX,
- LogoDestY,
- 0,
- 0,
- LogoWidth,
- LogoHeight,
- LogoWidth * sizeof (EFI_UGA_PIXEL)
- );
- } else {
- Status = EFI_UNSUPPORTED;
- }
- }
-
- if (!EFI_ERROR (Status)) {
- BootLogo->SetBootLogo (BootLogo, LogoBlt, LogoDestX, LogoDestY, LogoWidth, LogoHeight);
- }
- FreePool (LogoBlt);
-
- return Status;
-}
-
-/**
- Use SystemTable Conout to turn on video based Simple Text Out consoles. The
- Simple Text Out screens will now be synced up with all non video output devices
-
- @retval EFI_SUCCESS UGA devices are back in text mode and synced up.
-
-**/
-EFI_STATUS
-PlatformBootManagerDisableQuietBoot (
- VOID
- )
-{
- //
- // Enable Cursor on Screen
- //
- gST->ConOut->EnableCursor (gST->ConOut, TRUE);
- return EFI_SUCCESS;
-}
diff --git a/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
deleted file mode 100644
index 2628f4f..0000000
--- a/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/** @file
- This file include all platform action which can be customized
- by IBV/OEM.
-
-Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "PlatformBootManager.h"
-
-
-EFI_GUID mUefiShellFileGuid = { 0x7C04A583, 0x9E3E, 0x4f1c, {0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1}};
-
-/**
- Perform the platform diagnostic, such like test memory. OEM/IBV also
- can customize this function to support specific platform diagnostic.
-
- @param MemoryTestLevel The memory test intensive level
- @param QuietBoot Indicate if need to enable the quiet boot
-
-**/
-VOID
-PlatformBootManagerDiagnostics (
- IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel,
- IN BOOLEAN QuietBoot
- )
-{
- EFI_STATUS Status;
-
- //
- // Here we can decide if we need to show
- // the diagnostics screen
- // Notes: this quiet boot code should be remove
- // from the graphic lib
- //
- if (QuietBoot) {
- PlatformBootManagerEnableQuietBoot (PcdGetPtr(PcdLogoFile));
-
- //
- // Perform system diagnostic
- //
- Status = PlatformBootManagerMemoryTest (MemoryTestLevel);
- if (EFI_ERROR (Status)) {
- PlatformBootManagerDisableQuietBoot ();
- }
-
- return;
- }
-
- //
- // Perform system diagnostic
- //
- Status = PlatformBootManagerMemoryTest (MemoryTestLevel);
-}
-
-/**
- Return the index of the load option in the load option array.
-
- The function consider two load options are equal when the
- OptionType, Attributes, Description, FilePath and OptionalData are equal.
-
- @param Key Pointer to the load option to be found.
- @param Array Pointer to the array of load options to be found.
- @param Count Number of entries in the Array.
-
- @retval -1 Key wasn't found in the Array.
- @retval 0 ~ Count-1 The index of the Key in the Array.
-**/
-INTN
-PlatformFindLoadOption (
- IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
- IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
- IN UINTN Count
- )
-{
- UINTN Index;
-
- for (Index = 0; Index < Count; Index++) {
- if ((Key->OptionType == Array[Index].OptionType) &&
- (Key->Attributes == Array[Index].Attributes) &&
- (StrCmp (Key->Description, Array[Index].Description) == 0) &&
- (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&
- (Key->OptionalDataSize == Array[Index].OptionalDataSize) &&
- (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {
- return (INTN) Index;
- }
- }
-
- return -1;
-}
-
-VOID
-PlatformRegisterFvBootOption (
- EFI_GUID *FileGuid,
- CHAR16 *Description,
- UINT32 Attributes
- )
-{
- EFI_STATUS Status;
- UINTN OptionIndex;
- EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
- UINTN BootOptionCount;
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
-
- Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **) &LoadedImage);
- ASSERT_EFI_ERROR (Status);
-
- EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
- DevicePath = AppendDevicePathNode (
- DevicePathFromHandle (LoadedImage->DeviceHandle),
- (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
- );
-
- Status = EfiBootManagerInitializeLoadOption (
- &NewOption,
- LoadOptionNumberUnassigned,
- LoadOptionTypeBoot,
- Attributes,
- Description,
- DevicePath,
- NULL,
- 0
- );
- if (!EFI_ERROR (Status)) {
- BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);
-
- OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);
-
- if (OptionIndex == -1) {
- Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) -1);
- ASSERT_EFI_ERROR (Status);
- }
- EfiBootManagerFreeLoadOption (&NewOption);
- EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
- }
-}
-
-/**
- Do the platform specific action before the console is connected.
-
- Such as:
- Update console variable;
- Register new Driver#### or Boot####;
- Signal ReadyToLock event.
-**/
-VOID
-EFIAPI
-PlatformBootManagerBeforeConsole (
- VOID
- )
-{
- UINTN Index;
- EFI_STATUS Status;
- EFI_INPUT_KEY Enter;
- EFI_INPUT_KEY F2;
- EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
-
- //
- // Update the console variables.
- //
- for (Index = 0; gPlatformConsole[Index].DevicePath != NULL; Index++) {
- DEBUG ((DEBUG_INFO, "Check gPlatformConsole %d\n", Index));
- if ((gPlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) {
- Status = EfiBootManagerUpdateConsoleVariable (ConIn, gPlatformConsole[Index].DevicePath, NULL);
- DEBUG ((DEBUG_INFO, "CONSOLE_IN variable set %s : %r\n", ConvertDevicePathToText (gPlatformConsole[Index].DevicePath, FALSE, FALSE), Status));
- }
-
- if ((gPlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) {
- Status = EfiBootManagerUpdateConsoleVariable (ConOut, gPlatformConsole[Index].DevicePath, NULL);
- DEBUG ((DEBUG_INFO, "CONSOLE_OUT variable set %s : %r\n", ConvertDevicePathToText (gPlatformConsole[Index].DevicePath, FALSE, FALSE), Status));
- }
-
- if ((gPlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) {
- Status = EfiBootManagerUpdateConsoleVariable (ErrOut, gPlatformConsole[Index].DevicePath, NULL);
- DEBUG ((DEBUG_INFO, "STD_ERROR variable set %r", Status));
- }
- }
-
- //
- // Register ENTER as CONTINUE key
- //
- Enter.ScanCode = SCAN_NULL;
- Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;
- EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
- //
- // Map F2 to Boot Manager Menu
- //
- F2.ScanCode = SCAN_F2;
- F2.UnicodeChar = CHAR_NULL;
- EfiBootManagerGetBootManagerMenu (&BootOption);
- EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL);
- //
- // Register UEFI Shell
- //
- PlatformRegisterFvBootOption (&mUefiShellFileGuid, L"UEFI Shell", LOAD_OPTION_ACTIVE);
-}
-
-/**
- Do the platform specific action after the console is connected.
-
- Such as:
- Dynamically switch output mode;
- Signal console ready platform customized event;
- Run diagnostics like memory testing;
- Connect certain devices;
- Dispatch aditional option roms.
-**/
-VOID
-EFIAPI
-PlatformBootManagerAfterConsole (
- VOID
- )
-{
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL White;
-
- Black.Blue = Black.Green = Black.Red = Black.Reserved = 0;
- White.Blue = White.Green = White.Red = White.Reserved = 0xFF;
-
- EfiBootManagerConnectAll ();
- EfiBootManagerRefreshAllBootOption ();
-
- PlatformBootManagerDiagnostics (QUICK, TRUE);
-
- PrintXY (10, 10, &White, &Black, L"F2 to enter Boot Manager Menu. ");
- PrintXY (10, 30, &White, &Black, L"Enter to boot directly.");
-}
-
-/**
- This function is called each second during the boot manager waits the timeout.
-
- @param TimeoutRemain The remaining timeout.
-**/
-VOID
-EFIAPI
-PlatformBootManagerWaitCallback (
- UINT16 TimeoutRemain
- )
-{
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL White;
- UINT16 Timeout;
-
- Timeout = PcdGet16 (PcdPlatformBootTimeOut);
-
- Black.Blue = Black.Green = Black.Red = Black.Reserved = 0;
- White.Blue = White.Green = White.Red = White.Reserved = 0xFF;
-
- PlatformBootManagerShowProgress (
- White,
- Black,
- L"Start boot option",
- White,
- (Timeout - TimeoutRemain) * 100 / Timeout,
- 0
- );
-}
diff --git a/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManager.h b/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
deleted file mode 100644
index e69bd4e..0000000
--- a/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/**@file
- Head file for BDS Platform specific code
-
-Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#ifndef _PLATFORM_BOOT_MANAGER_H
-#define _PLATFORM_BOOT_MANAGER_H
-
-#include <PiDxe.h>
-#include <IndustryStandard/Bmp.h>
-#include <Protocol/GenericMemoryTest.h>
-#include <Protocol/LoadedImage.h>
-#include <Protocol/UgaDraw.h>
-#include <Protocol/GraphicsOutput.h>
-#include <Protocol/OEMBadging.h>
-#include <Protocol/BootLogo.h>
-#include <Protocol/DevicePath.h>
-
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/BaseLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/UefiLib.h>
-#include <Library/UefiBootManagerLib.h>
-#include <Library/PcdLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/HiiLib.h>
-#include <Library/PrintLib.h>
-#include <Library/DxeServicesLib.h>
-
-typedef struct {
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- UINTN ConnectType;
-} PLATFORM_CONSOLE_CONNECT_ENTRY;
-
-extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];
-
-#define gEndEntire \
- { \
- END_DEVICE_PATH_TYPE,\
- END_ENTIRE_DEVICE_PATH_SUBTYPE,\
- END_DEVICE_PATH_LENGTH,\
- 0\
- }
-
-#define CONSOLE_OUT BIT0
-#define CONSOLE_IN BIT1
-#define STD_ERROR BIT2
-
-//
-// Below is the platform PCI device path for
-//
-typedef struct {
- ACPI_HID_DEVICE_PATH PciRootBridge;
- PCI_DEVICE_PATH PciDevice;
- ACPI_ADR_DEVICE_PATH AcpiAddr;
- EFI_DEVICE_PATH_PROTOCOL End;
-} PLATFORM_PCI_DEVICE_PATH;
-
-/**
- Use SystemTable Conout to stop video based Simple Text Out consoles from going
- to the video device. Put up LogoFile on every video device that is a console.
-
- @param[in] LogoFile File name of logo to display on the center of the screen.
-
- @retval EFI_SUCCESS ConsoleControl has been flipped to graphics and logo displayed.
- @retval EFI_UNSUPPORTED Logo not found
-
-**/
-EFI_STATUS
-PlatformBootManagerEnableQuietBoot (
- IN EFI_GUID *LogoFile
- );
-
-/**
- Use SystemTable Conout to turn on video based Simple Text Out consoles. The
- Simple Text Out screens will now be synced up with all non video output devices
-
- @retval EFI_SUCCESS UGA devices are back in text mode and synced up.
-
-**/
-EFI_STATUS
-PlatformBootManagerDisableQuietBoot (
- VOID
- );
-
-/**
- Perform the memory test base on the memory test intensive level,
- and update the memory resource.
-
- @param Level The memory test intensive level.
-
- @retval EFI_STATUS Success test all the system memory and update
- the memory resource
-
-**/
-EFI_STATUS
-PlatformBootManagerMemoryTest (
- IN EXTENDMEM_COVERAGE_LEVEL Level
- );
-
-/**
-
- Show progress bar with title above it. It only works in Graphics mode.
-
-
- @param TitleForeground Foreground color for Title.
- @param TitleBackground Background color for Title.
- @param Title Title above progress bar.
- @param ProgressColor Progress bar color.
- @param Progress Progress (0-100)
- @param PreviousValue The previous value of the progress.
-
- @retval EFI_STATUS Success update the progress bar
-
-**/
-EFI_STATUS
-PlatformBootManagerShowProgress (
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
- IN CHAR16 *Title,
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
- IN UINTN Progress,
- IN UINTN PreviousValue
- );
-
-#endif // _PLATFORM_BOOT_MANAGER_H
diff --git a/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
deleted file mode 100644
index 7a8d7d8..0000000
--- a/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ /dev/null
@@ -1,72 +0,0 @@
-## @file
-# Include all platform action which can be customized by IBV/OEM.
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-# Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PlatformBootManagerLib
- FILE_GUID = 7DDA7916-6139-4D46-A415-30E854AF3BC7
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV
-#
-
-[Sources]
- PlatformData.c
- PlatformBootManager.c
- PlatformBootManager.h
- MemoryTest.c
- Strings.uni
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
-
-[LibraryClasses]
- BaseLib
- UefiBootServicesTableLib
- UefiRuntimeServicesTableLib
- UefiLib
- UefiBootManagerLib
- PcdLib
- DxeServicesLib
- MemoryAllocationLib
- DevicePathLib
- HiiLib
- PrintLib
-
-[Guids]
-
-[Protocols]
- gEfiGenericMemTestProtocolGuid ## CONSUMES
- gEfiGraphicsOutputProtocolGuid ## CONSUMES
- gEfiUgaDrawProtocolGuid ## CONSUMES
- gEfiOEMBadgingProtocolGuid ## CONSUMES
- gEfiBootLogoProtocolGuid ## CONSUMES
-
-[Pcd]
- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn
- gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootlogoOnlyEnable
- gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand
diff --git a/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformData.c b/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformData.c
deleted file mode 100644
index 18209d3..0000000
--- a/RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformData.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/**@file
- Defined the platform specific device path which will be filled to
- ConIn/ConOut variables.
-
-Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#include "PlatformBootManager.h"
-
-//
-// Platform specific keyboard device path
-//
-PLATFORM_PCI_DEVICE_PATH gGopDevicePath0 = {
- {
- {
- ACPI_DEVICE_PATH, ACPI_DP,
- {
- (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),
- (UINT8)((sizeof (ACPI_HID_DEVICE_PATH)) >> 8)
- }
- },
- EISA_PNP_ID (0x0A03),
- 0
- },
- {
- {
- HARDWARE_DEVICE_PATH,
- HW_PCI_DP,
- {
- (UINT8) (sizeof (PCI_DEVICE_PATH)),
- (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8)
- }
- },
- 0, // Function 0.
- 2 // Device 2.
- },
- {
- {
- ACPI_DEVICE_PATH,
- ACPI_ADR_DP,
- {
- (UINT8) (sizeof (ACPI_ADR_DEVICE_PATH)),
- (UINT8)((sizeof (ACPI_ADR_DEVICE_PATH)) >> 8)
- }
- },
- ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_VGA, 0, 0)
- },
- {
- END_DEVICE_PATH_TYPE,
- END_ENTIRE_DEVICE_PATH_SUBTYPE,
- {
- END_DEVICE_PATH_LENGTH,
- 0
- } \
- }
-};
-
-//
-// Predefined platform default console device path
-//
-PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {
- {
- (EFI_DEVICE_PATH_PROTOCOL *) &gGopDevicePath0,
- CONSOLE_OUT
- },
- {
- NULL,
- 0
- }
-};
diff --git a/RiscVVirtPkg/Library/PlatformBootManagerLib/Strings.uni b/RiscVVirtPkg/Library/PlatformBootManagerLib/Strings.uni
deleted file mode 100644
index 03dc40bf7d7a53183c9bc508bdcabde3808e996b..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/RiscVVirtPkg/Library/PlatformDebugLibIoPort/DebugLib.c b/RiscVVirtPkg/Library/PlatformDebugLibIoPort/DebugLib.c
deleted file mode 100644
index abec32a..0000000
--- a/RiscVVirtPkg/Library/PlatformDebugLibIoPort/DebugLib.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/** @file
- Base Debug library instance for QEMU debug port.
- It uses PrintLib to send debug messages to a fixed I/O port.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2012, Red Hat, Inc.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Base.h>
-#include <Uefi.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include <Library/PrintLib.h>
-#include <Library/PcdLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugPrintErrorLevelLib.h>
-
-//
-// Define the maximum debug and assert message length that this library supports
-//
-#define MAX_DEBUG_MESSAGE_LENGTH 0x100
-
-/**
- This constructor function does not have to do anything.
-
- @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
-
-**/
-RETURN_STATUS
-EFIAPI
-PlatformDebugLibIoPortConstructor (
- VOID
- )
-{
- return EFI_SUCCESS;
-}
-
-/**
- Prints a debug message to the debug output device if the specified error level is enabled.
-
- If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
- GetDebugPrintErrorLevel (), then print the message specified by Format and the
- associated variable argument list to the debug output device.
-
- If Format is NULL, then ASSERT().
-
- @param ErrorLevel The error level of the debug message.
- @param Format Format string for the debug message to print.
- @param ... Variable argument list whose contents are accessed
- based on the format string specified by Format.
-
-**/
-VOID
-EFIAPI
-DebugPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- ...
- )
-{
- CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
- VA_LIST Marker;
- UINT8 *Ptr;
-
- //
- // If Format is NULL, then ASSERT().
- //
- ASSERT (Format != NULL);
-
- //
- // Check driver debug mask value and global mask
- //
- if ((ErrorLevel & GetDebugPrintErrorLevel ()) == 0) {
- return;
- }
-
- //
- // Convert the DEBUG() message to an ASCII String
- //
- VA_START (Marker, Format);
- AsciiVSPrint (Buffer, sizeof (Buffer), Format, Marker);
- VA_END (Marker);
-
- //
- // Send the print string to the debug I/O port
- //
- for (Ptr = (UINT8 *) Buffer; *Ptr; Ptr++) {
- IoWrite8 (PcdGet16(PcdDebugIoPort), *Ptr);
- }
-}
-
-/**
- Prints an assert message containing a filename, line number, and description.
- This may be followed by a breakpoint or a dead loop.
-
- Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"
- to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
- PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
- DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
- CpuDeadLoop() is called. If neither of these bits are set, then this function
- returns immediately after the message is printed to the debug output device.
- DebugAssert() must actively prevent recursion. If DebugAssert() is called while
- processing another DebugAssert(), then DebugAssert() must return immediately.
-
- If FileName is NULL, then a <FileName> string of "(NULL) Filename" is printed.
- If Description is NULL, then a <Description> string of "(NULL) Description" is printed.
-
- @param FileName The pointer to the name of the source file that generated the assert condition.
- @param LineNumber The line number in the source file that generated the assert condition
- @param Description The pointer to the description of the assert condition.
-
-**/
-VOID
-EFIAPI
-DebugAssert (
- IN CONST CHAR8 *FileName,
- IN UINTN LineNumber,
- IN CONST CHAR8 *Description
- )
-{
- CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
- UINT8 *Ptr;
-
- //
- // Generate the ASSERT() message in Ascii format
- //
- AsciiSPrint (Buffer, sizeof Buffer, "ASSERT %a(%Lu): %a\n", FileName,
- (UINT64)LineNumber, Description);
-
- //
- // Send the print string to the Console Output device
- //
- for (Ptr = (UINT8 *) Buffer; *Ptr; Ptr++) {
- IoWrite8 (PcdGet16(PcdDebugIoPort), *Ptr);
- }
-
- //
- // Generate a Breakpoint, DeadLoop, or NOP based on PCD settings
- //
- if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {
- CpuBreakpoint ();
- } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {
- CpuDeadLoop ();
- }
-}
-
-/**
- Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
-
- This function fills Length bytes of Buffer with the value specified by
- PcdDebugClearMemoryValue, and returns Buffer.
-
- If Buffer is NULL, then ASSERT().
- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
-
- @param Buffer The pointer to the target buffer to be filled with PcdDebugClearMemoryValue.
- @param Length The number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue.
-
- @return Buffer The pointer to the target buffer filled with PcdDebugClearMemoryValue.
-
-**/
-VOID *
-EFIAPI
-DebugClearMemory (
- OUT VOID *Buffer,
- IN UINTN Length
- )
-{
- //
- // If Buffer is NULL, then ASSERT().
- //
- ASSERT (Buffer != NULL);
-
- //
- // SetMem() checks for the the ASSERT() condition on Length and returns Buffer
- //
- return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));
-}
-
-/**
- Returns TRUE if ASSERT() macros are enabled.
-
- This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
-
- @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.
-
-**/
-BOOLEAN
-EFIAPI
-DebugAssertEnabled (
- VOID
- )
-{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
-}
-
-/**
- Returns TRUE if DEBUG() macros are enabled.
-
- This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
-
- @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.
-
-**/
-BOOLEAN
-EFIAPI
-DebugPrintEnabled (
- VOID
- )
-{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
-}
-
-/**
- Returns TRUE if DEBUG_CODE() macros are enabled.
-
- This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
-
- @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.
-
-**/
-BOOLEAN
-EFIAPI
-DebugCodeEnabled (
- VOID
- )
-{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
-}
-
-/**
- Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
-
- This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
- PcdDebugProperyMask is set. Otherwise FALSE is returned.
-
- @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
- @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.
-
-**/
-BOOLEAN
-EFIAPI
-DebugClearMemoryEnabled (
- VOID
- )
-{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
-}
-
-/**
- Returns TRUE if any one of the bit is set both in ErrorLevel and PcdFixedDebugPrintErrorLevel.
-
- This function compares the bit mask of ErrorLevel and PcdFixedDebugPrintErrorLevel.
-
- @retval TRUE Current ErrorLevel is supported.
- @retval FALSE Current ErrorLevel is not supported.
-
-**/
-BOOLEAN
-EFIAPI
-DebugPrintLevelEnabled (
- IN CONST UINTN ErrorLevel
- )
-{
- return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);
-}
diff --git a/RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf b/RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
deleted file mode 100644
index e70bf44..0000000
--- a/RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
+++ /dev/null
@@ -1,51 +0,0 @@
-## @file
-# Instance of Debug Library for the QEMU debug console port.
-# It uses Print Library to produce formatted output strings.
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-# Copyright (c) 2012, Red Hat, Inc.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PlatformDebugLibIoPort
- FILE_GUID = DF934DA3-CD31-49FE-AF50-B3C87C79325F
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = DebugLib
- CONSTRUCTOR = PlatformDebugLibIoPortConstructor
-
-#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
-#
-
-[Sources]
- DebugLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- BaseMemoryLib
- IoLib
- PcdLib
- PrintLib
- BaseLib
- DebugPrintErrorLevelLib
-
-[Pcd]
- gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort ## CONSUMES
- gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue ## CONSUMES
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask ## CONSUMES
- gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel ## CONSUMES
-
diff --git a/RiscVVirtPkg/Library/QemuFwCfgLib/Ia32/IoLibExAsm.nasm b/RiscVVirtPkg/Library/QemuFwCfgLib/Ia32/IoLibExAsm.nasm
deleted file mode 100644
index faa22e9..0000000
--- a/RiscVVirtPkg/Library/QemuFwCfgLib/Ia32/IoLibExAsm.nasm
+++ /dev/null
@@ -1,55 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-; This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php.
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- SECTION .text
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoReadFifo8 (
-; IN UINTN Port,
-; IN UINTN Size,
-; IN VOID *Buffer
-; );
-;------------------------------------------------------------------------------
-global ASM_PFX(IoReadFifo8)
-ASM_PFX(IoReadFifo8):
-
- mov dx, [esp + 4]
- mov ecx, [esp + 8]
- push edi
- mov edi, [esp + 16]
-rep insb
- pop edi
- ret
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoWriteFifo8 (
-; IN UINTN Port,
-; IN UINTN Size,
-; IN VOID *Buffer
-; );
-;------------------------------------------------------------------------------
-global ASM_PFX(IoWriteFifo8)
-ASM_PFX(IoWriteFifo8):
-
- mov dx, [esp + 4]
- mov ecx, [esp + 8]
- push esi
- mov esi, [esp + 16]
-rep outsb
- pop esi
- ret
-
diff --git a/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c b/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c
deleted file mode 100644
index 3b283a8..0000000
--- a/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c
+++ /dev/null
@@ -1,332 +0,0 @@
-/** @file
-
- Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
- Copyright (C) 2013, Red Hat, Inc.
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "Uefi.h"
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/IoLib.h>
-#include <Library/QemuFwCfgLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-
-/**
- Reads an 8-bit MMIO fifo into a block of memory.
-
- Reads the 8-bit MMIO fifo specified by Port.
-
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all MMIO read and write operations are
- serialized.
-
- If 8-bit MMIO port operations are not supported, then ASSERT().
-
- @param Port The MMIO to read.
- @param Count The number of times to read MMIO.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-MemReadFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- while (Count != 0) {
- *((UINT8 *)Buffer) = *((UINT8 *)Port);
- (UINT8 *)Buffer ++;
- Count --;
- };
-}
-
-/**
- Writes an 8-bit MMIO fifo from a block of memory.
-
- Writes the 8-bit MMIO fifo port specified by Port.
-
- The port is written Count times, and the data are obtained
- from the provided Buffer.
-
- This function must guarantee that all MMIO read and write operations are
- serialized.
-
- If 8-bit MMIO port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read MMIO.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-MemWriteFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- while (Count != 0) {
- *((UINT8 *)Port) = *((UINT8 *)Buffer);
- (UINT8 *)Buffer ++;
- Count --;
- };
-}
-
-/**
- Selects a firmware configuration item for reading.
-
- Following this call, any data read from this item will start from
- the beginning of the configuration item's data.
-
- @param[in] QemuFwCfgItem - Firmware Configuration item to read
-
-**/
-VOID
-EFIAPI
-QemuFwCfgSelectItem (
- IN FIRMWARE_CONFIG_ITEM QemuFwCfgItem
- )
-{
- DEBUG ((EFI_D_INFO, "Select Item: 0x%x\n", (UINT16)(UINTN) QemuFwCfgItem));
- IoWrite16 (0x510, (UINT16)(UINTN) QemuFwCfgItem);
-}
-
-
-/**
- Reads firmware configuration bytes into a buffer
-
- @param[in] Size - Size in bytes to read
- @param[in] Buffer - Buffer to store data into (OPTIONAL if Size is 0)
-
-**/
-VOID
-EFIAPI
-InternalQemuFwCfgReadBytes (
- IN UINTN Size,
- IN VOID *Buffer OPTIONAL
- )
-{
- MemReadFifo8 (0x511, Size, Buffer);
-}
-
-/**
- Reads firmware configuration bytes into a buffer
-
- If called multiple times, then the data read will
- continue at the offset of the firmware configuration
- item where the previous read ended.
-
- @param[in] Size - Size in bytes to read
- @param[in] Buffer - Buffer to store data into
-
-**/
-VOID
-EFIAPI
-QemuFwCfgReadBytes (
- IN UINTN Size,
- IN VOID *Buffer
- )
-{
- if (InternalQemuFwCfgIsAvailable ()) {
- InternalQemuFwCfgReadBytes (Size, Buffer);
- } else {
- ZeroMem (Buffer, Size);
- }
-}
-
-/**
- Write firmware configuration bytes from a buffer
-
- If called multiple times, then the data written will
- continue at the offset of the firmware configuration
- item where the previous write ended.
-
- @param[in] Size - Size in bytes to write
- @param[in] Buffer - Buffer to read data from
-
-**/
-VOID
-EFIAPI
-QemuFwCfgWriteBytes (
- IN UINTN Size,
- IN VOID *Buffer
- )
-{
- if (InternalQemuFwCfgIsAvailable ()) {
- MemWriteFifo8 (0x511, Size, Buffer);
- }
-}
-
-/**
- Reads a UINT8 firmware configuration value
-
- @return Value of Firmware Configuration item read
-
-**/
-UINT8
-EFIAPI
-QemuFwCfgRead8 (
- VOID
- )
-{
- UINT8 Result;
-
- QemuFwCfgReadBytes (sizeof (Result), &Result);
-
- return Result;
-}
-
-/**
- Reads a UINT16 firmware configuration value
-
- @return Value of Firmware Configuration item read
-
-**/
-UINT16
-EFIAPI
-QemuFwCfgRead16 (
- VOID
- )
-{
- UINT16 Result;
-
- QemuFwCfgReadBytes (sizeof (Result), &Result);
-
- return Result;
-}
-
-/**
- Reads a UINT32 firmware configuration value
-
- @return Value of Firmware Configuration item read
-
-**/
-UINT32
-EFIAPI
-QemuFwCfgRead32 (
- VOID
- )
-{
- UINT32 Result;
-
- QemuFwCfgReadBytes (sizeof (Result), &Result);
-
- return Result;
-}
-
-
-/**
- Reads a UINT64 firmware configuration value
-
- @return Value of Firmware Configuration item read
-
-**/
-UINT64
-EFIAPI
-QemuFwCfgRead64 (
- VOID
- )
-{
- UINT64 Result;
-
- QemuFwCfgReadBytes (sizeof (Result), &Result);
-
- return Result;
-}
-
-/**
- Find the configuration item corresponding to the firmware configuration file.
-
- @param[in] Name - Name of file to look up.
- @param[out] Item - Configuration item corresponding to the file, to be passed
- to QemuFwCfgSelectItem ().
- @param[out] Size - Number of bytes in the file.
-
- @return RETURN_SUCCESS If file is found.
- RETURN_NOT_FOUND If file is not found.
- RETURN_UNSUPPORTED If firmware configuration is unavailable.
-
-**/
-RETURN_STATUS
-EFIAPI
-QemuFwCfgFindFile (
- IN CONST CHAR8 *Name,
- OUT FIRMWARE_CONFIG_ITEM *Item,
- OUT UINTN *Size
- )
-{
- UINT32 Count;
- UINT32 Idx;
-
- if (!InternalQemuFwCfgIsAvailable ()) {
- return RETURN_UNSUPPORTED;
- }
-
- QemuFwCfgSelectItem (QemuFwCfgItemFileDir);
- Count = SwapBytes32 (QemuFwCfgRead32 ());
-
- for (Idx = 0; Idx < Count; ++Idx) {
- UINT32 FileSize;
- UINT16 FileSelect;
- UINT16 FileReserved;
- CHAR8 FName[QEMU_FW_CFG_FNAME_SIZE];
-
- FileSize = QemuFwCfgRead32 ();
- FileSelect = QemuFwCfgRead16 ();
- FileReserved = QemuFwCfgRead16 ();
- (VOID) FileReserved; /* Force a do-nothing reference. */
- InternalQemuFwCfgReadBytes (sizeof (FName), FName);
-
- if (AsciiStrCmp (Name, FName) == 0) {
- *Item = SwapBytes16 (FileSelect);
- *Size = SwapBytes32 (FileSize);
- return RETURN_SUCCESS;
- }
- }
-
- return RETURN_NOT_FOUND;
-}
-
-/**
- Determine if S3 support is explicitly enabled.
-
- @retval TRUE if S3 support is explicitly enabled.
- FALSE otherwise. This includes unavailability of the firmware
- configuration interface.
-**/
-BOOLEAN
-EFIAPI
-QemuFwCfgS3Enabled (
- VOID
- )
-{
- RETURN_STATUS Status;
- FIRMWARE_CONFIG_ITEM FwCfgItem;
- UINTN FwCfgSize;
- UINT8 SystemStates[6];
-
- Status = QemuFwCfgFindFile ("etc/system-states", &FwCfgItem, &FwCfgSize);
- if (Status != RETURN_SUCCESS || FwCfgSize != sizeof SystemStates) {
- return FALSE;
- }
- QemuFwCfgSelectItem (FwCfgItem);
- QemuFwCfgReadBytes (sizeof SystemStates, SystemStates);
- return (BOOLEAN) (SystemStates[3] & BIT7);
-}
diff --git a/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf b/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
deleted file mode 100644
index 40aa781..0000000
--- a/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
+++ /dev/null
@@ -1,50 +0,0 @@
-## @file
-#
-# Stateful, implicitly initialized fw_cfg library.
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-# Copyright (C) 2013, Red Hat, Inc.
-# Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = QemuFwCfgLib
- FILE_GUID = b24657f7-4890-4778-bb6C-4ad5146cfafe
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = QemuFwCfgLib|PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER
-
- CONSTRUCTOR = QemuFwCfgInitialize
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Sources]
- QemuFwCfgLib.c
- QemuFwCfgPeiDxe.c
-
-[Packages]
- MdePkg/MdePkg.dec
- OvmfPkg/OvmfPkg.dec
- RiscVVirtPkg/RiscVVirtPkg.dec
-
-[LibraryClasses]
- BaseLib
- BaseMemoryLib
- DebugLib
- IoLib
- MemoryAllocationLib
-
diff --git a/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgPeiDxe.c b/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgPeiDxe.c
deleted file mode 100644
index f693cff..0000000
--- a/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgPeiDxe.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/** @file
-
- Stateful and implicitly initialized fw_cfg library implementation.
-
- Copyright (C) 2013, Red Hat, Inc.
- Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available
- under the terms and conditions of the BSD License which accompanies this
- distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#include <Library/DebugLib.h>
-#include <Library/QemuFwCfgLib.h>
-
-STATIC BOOLEAN mQemuFwCfgSupported = FALSE;
-
-
-/**
- Returns a boolean indicating if the firmware configuration interface
- is available or not.
-
- This function may change fw_cfg state.
-
- @retval TRUE The interface is available
- @retval FALSE The interface is not available
-
-**/
-BOOLEAN
-EFIAPI
-QemuFwCfgIsAvailable (
- VOID
- )
-{
- return InternalQemuFwCfgIsAvailable ();
-}
-
-
-RETURN_STATUS
-EFIAPI
-QemuFwCfgInitialize (
- VOID
- )
-{
- UINT32 Signature;
- UINT32 Revision;
-
- //
- // Enable the access routines while probing to see if it is supported.
- //
- mQemuFwCfgSupported = TRUE;
-
- QemuFwCfgSelectItem (QemuFwCfgItemSignature);
- Signature = QemuFwCfgRead32 ();
- DEBUG ((EFI_D_INFO, "FW CFG Signature: 0x%x\n", Signature));
- QemuFwCfgSelectItem (QemuFwCfgItemInterfaceVersion);
- Revision = QemuFwCfgRead32 ();
- DEBUG ((EFI_D_INFO, "FW CFG Revision: 0x%x\n", Revision));
- if ((Signature != SIGNATURE_32 ('Q', 'E', 'M', 'U')) ||
- (Revision < 1)
- ) {
- DEBUG ((EFI_D_INFO, "QemuFwCfg interface not supported.\n"));
- mQemuFwCfgSupported = FALSE;
- return RETURN_SUCCESS;
- }
-
- DEBUG ((EFI_D_INFO, "QemuFwCfg interface is supported.\n"));
- return RETURN_SUCCESS;
-}
-
-
-/**
- Returns a boolean indicating if the firmware configuration interface is
- available for library-internal purposes.
-
- This function never changes fw_cfg state.
-
- @retval TRUE The interface is available internally.
- @retval FALSE The interface is not available internally.
-**/
-BOOLEAN
-EFIAPI
-InternalQemuFwCfgIsAvailable (
- VOID
- )
-{
- return mQemuFwCfgSupported;
-}
diff --git a/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c b/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c
deleted file mode 100644
index 88c32ce..0000000
--- a/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgSec.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/** @file
-
- Stateless fw_cfg library implementation.
-
- Clients must call QemuFwCfgIsAvailable() first.
-
- Copyright (C) 2013, Red Hat, Inc.
- Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available
- under the terms and conditions of the BSD License which accompanies this
- distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#include <Library/DebugLib.h>
-#include <Library/QemuFwCfgLib.h>
-
-
-/**
- Returns a boolean indicating if the firmware configuration interface
- is available or not.
-
- This function may change fw_cfg state.
-
- @retval TRUE The interface is available
- @retval FALSE The interface is not available
-
-**/
-BOOLEAN
-EFIAPI
-QemuFwCfgIsAvailable (
- VOID
- )
-{
- UINT32 Signature;
- UINT32 Revision;
-
- QemuFwCfgSelectItem (QemuFwCfgItemSignature);
- Signature = QemuFwCfgRead32 ();
- DEBUG ((EFI_D_INFO, "FW CFG Signature: 0x%x\n", Signature));
- QemuFwCfgSelectItem (QemuFwCfgItemInterfaceVersion);
- Revision = QemuFwCfgRead32 ();
- DEBUG ((EFI_D_INFO, "FW CFG Revision: 0x%x\n", Revision));
- if ((Signature != SIGNATURE_32 ('Q', 'E', 'M', 'U')) ||
- (Revision < 1)
- ) {
- DEBUG ((EFI_D_INFO, "QemuFwCfg interface not supported.\n"));
- return FALSE;
- }
-
- DEBUG ((EFI_D_INFO, "QemuFwCfg interface is supported.\n"));
- return TRUE;
-}
-
-
-/**
- Returns a boolean indicating if the firmware configuration interface is
- available for library-internal purposes.
-
- This function never changes fw_cfg state.
-
- @retval TRUE The interface is available internally.
- @retval FALSE The interface is not available internally.
-**/
-BOOLEAN
-EFIAPI
-InternalQemuFwCfgIsAvailable (
- VOID
- )
-{
- //
- // We always return TRUE, because the consumer of this library ought to have
- // called QemuFwCfgIsAvailable before making other calls which would hit this
- // path.
- //
- return TRUE;
-}
diff --git a/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf b/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf
deleted file mode 100644
index bcee981..0000000
--- a/RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf
+++ /dev/null
@@ -1,48 +0,0 @@
-## @file
-#
-# Stateless fw_cfg library that must be queried before use.
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-# Copyright (C) 2013, Red Hat, Inc.
-# Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = QemuFwCfgSecLib
- FILE_GUID = 12b3a8f7-a587-47b8-b7cd-55e56e734913
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = QemuFwCfgLib|SEC
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64 RISCV64
-#
-
-[Sources]
- QemuFwCfgLib.c
- QemuFwCfgSec.c
-
-[Packages]
- MdePkg/MdePkg.dec
- OvmfPkg/OvmfPkg.dec
- RiscVVirtPkg/RiscVVirtPkg.dec
-
-[LibraryClasses]
- BaseLib
- BaseMemoryLib
- DebugLib
- IoLib
- MemoryAllocationLib
-
diff --git a/RiscVVirtPkg/Library/QemuFwCfgLib/X64/IoLibExAsm.nasm b/RiscVVirtPkg/Library/QemuFwCfgLib/X64/IoLibExAsm.nasm
deleted file mode 100644
index f1078f2..0000000
--- a/RiscVVirtPkg/Library/QemuFwCfgLib/X64/IoLibExAsm.nasm
+++ /dev/null
@@ -1,52 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-; This program and the accompanying materials
-; are licensed and made available under the terms and conditions of the BSD License
-; which accompanies this distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php.
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- DEFAULT REL
- SECTION .text
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoReadFifo8 (
-; IN UINTN Port, // rcx
-; IN UINTN Size, // rdx
-; IN VOID *Buffer // r8
-; );
-;------------------------------------------------------------------------------
-global ASM_PFX(IoReadFifo8)
-ASM_PFX(IoReadFifo8):
-
- xchg rcx, rdx
- xchg rdi, r8 ; rdi: buffer address; r8: save rdi
-rep insb
- mov rdi, r8 ; restore rdi
- ret
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoWriteFifo8 (
-; IN UINTN Port, // rcx
-; IN UINTN Size, // rdx
-; IN VOID *Buffer // r8
-; );
-;------------------------------------------------------------------------------
-global ASM_PFX(IoWriteFifo8)
-ASM_PFX(IoWriteFifo8):
-
- xchg rcx, rdx
- xchg rsi, r8 ; rdi: buffer address; r8: save rdi
-rep outsb
- mov rsi, r8 ; restore rdi
- ret
-
diff --git a/RiscVVirtPkg/Library/ResetSystemLib/ResetSystemLib.c b/RiscVVirtPkg/Library/ResetSystemLib/ResetSystemLib.c
deleted file mode 100644
index a38eec6..0000000
--- a/RiscVVirtPkg/Library/ResetSystemLib/ResetSystemLib.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/** @file
- RISC-V reset functionality.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#include <Base.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-
-/**
- Calling this function causes a system-wide reset. This sets
- all circuitry within the system to its initial state. This type of reset
- is asynchronous to system operation and operates without regard to
- cycle boundaries.
-
- System reset should not return, if it returns, it means the system does
- not support cold reset.
-**/
-VOID
-EFIAPI
-ResetCold (
- VOID
- )
-{
- DEBUG ((DEBUG_ERROR, "Not available on RISV-V yet\n"));
- ASSERT (FALSE);
-}
-
-/**
- Calling this function causes a system-wide initialization. The processors
- are set to their initial state, and pending cycles are not corrupted.
-
- System reset should not return, if it returns, it means the system does
- not support warm reset.
-**/
-VOID
-EFIAPI
-ResetWarm (
- VOID
- )
-{
- DEBUG ((DEBUG_ERROR, "Not available on RISV-V yet\n"));
- ASSERT (FALSE);
-}
-
-/**
- Calling this function causes the system to enter a power state equivalent
- to the ACPI G2/S5 or G3 states.
-
- System shutdown should not return, if it returns, it means the system does
- not support shut down reset.
-**/
-VOID
-EFIAPI
-ResetShutdown (
- VOID
- )
-{
- DEBUG ((DEBUG_ERROR, "Not available on RISV-V yet\n"));
- ASSERT (FALSE);
-}
-
-
-/**
- Calling this function causes the system to enter a power state for capsule
- update.
-
- Reset update should not return, if it returns, it means the system does
- not support capsule update.
-
-**/
-VOID
-EFIAPI
-EnterS3WithImmediateWake (
- VOID
- )
-{
- DEBUG ((DEBUG_ERROR, "Not available on RISV-V yet\n"));
- ASSERT (FALSE);
-}
diff --git a/RiscVVirtPkg/Library/ResetSystemLib/ResetSystemLib.inf b/RiscVVirtPkg/Library/ResetSystemLib/ResetSystemLib.inf
deleted file mode 100644
index 7702fc1..0000000
--- a/RiscVVirtPkg/Library/ResetSystemLib/ResetSystemLib.inf
+++ /dev/null
@@ -1,39 +0,0 @@
-## @file
-# RISC-V Library instance for ResetSystem library class
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ResetSystemLib
- FILE_GUID = 6914B03F6-BD8C-4137-A2CA-755E254E1A3A
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = ResetSystemLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV32 RISCV64
-#
-
-[Sources]
- ResetSystemLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- DebugLib
-
-[Pcd]
diff --git a/RiscVVirtPkg/License.txt b/RiscVVirtPkg/License.txt
deleted file mode 100644
index 07a4753..0000000
--- a/RiscVVirtPkg/License.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-Copyright (c) 2014 - 2015, Linaro Limited. All rights reserved.
-Copyright (c) 2013 - 2015, Red Hat, Inc.
-Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.
-Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.
-Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-
-* Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in
- the documentation and/or other materials provided with the
- distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-
-
-Some files are subject to the following license, the MIT license. Those files
-are located in:
-- OvmfPkg/Include/IndustryStandard/Xen/
-- OvmfPkg/XenBusDxe/
-- OvmfPkg/XenPvBlkDxe/
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
diff --git a/RiscVVirtPkg/README b/RiscVVirtPkg/README
deleted file mode 100644
index ff48f62..0000000
--- a/RiscVVirtPkg/README
+++ /dev/null
@@ -1,101 +0,0 @@
-## @file
-# Readme of how to build and launch RiscVVirtPkg on QEMU.
-#
-# Copyright (c) 2016-2017, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-=== EDKII RISC-V Virtual Package OVERVIEW ===
-
-The RISC-V virtual package project is RISC-V UEFI port on QEMU.
-The binary built from RiscVVirtPkg can be lanuched on RISC_V QEMU port for emulating RISC-V ISA.
-
-More information about UEFI can be found at http://www.tianocore.org
-More information about OVMF can be found at http://www.tianocore.org/ovmf/
-More information about RISC-V can be found at http://riscv.org
-
-=== STATUS ===
-
-Current capabilities:
- Current implementation can boot UEFI to internal shell with USB keybaord support.
-
-* Currently we only have the implementation of RISC-V 64 arch.
-* We preserved the capability of supporting RISC-V 32/128 arch.
-* ACPI, SMBIOS, SMM and MP are not yet supported.
-* QEMU RISC-V port
- - Video, USB keyboard
-* Only GCC can build RISC-V arch
-
-=== FUTURE PLANS ===
-
-* Implement ACPI, MP, SMBIO and SMM for RISC-V.
-
-=== Get source code ===
-* QEMU RISC-V PC/AT port.
- git clone https://github.com/AbnerChang/RiscVQemuPcat.git (Latest commit SHA 9992f910 07/03/2017)
-
-* RISC-V tools (RISC-V GCC 7.1.1)
- $git clone https://github.com/riscv/riscv-tools.git (Lastest commit SHA 7cd1d105 06/22/2017)
-
-* EDK2 open source
-
-=== Build RISC-V tool chain ===
-Before you build RISC-V tool chain, you need below packages.
-*sudo apt-get install autoconf automake autotools-dev curl device-tree-compiler libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev
-*Change directory to riscv-tools
- git submodule update --init --recursive
- export RISCV=~/riscv
-*In build.sh, add build option "--with-arch=rv64g" to "build_project" as below,
-build_project riscv-gnu-toolchain --prefix=$RISCV --with-arch=rv64g
-This builds RISC-V tool chain to use RISC-V "G" varient.
-*Build RISC-V tool chain
- ./build.sh
-
-The binaries needed for building EDK2 open source to RISC-V ISA are built in to ~/riscv
-
-More information on below link,
-http://riscv.org/software-tools/
-
-**** Build QEMU RISC-V PC/AT
-Before you build QEMU RISC-V, you need belwo packages.
-*sudo apt-get install libpixman-1-dev
-*sudo apt-get install gcc libc6-dev pkg-config bridge-utils uml-utilities zlib1g-dev libglib2.0-dev autoconf automake libtool libsdl1.2-dev
-*Change directory to RiscVQemuPcat
-*./configure --target-list=riscvpcat-softmmu
-*make
-
-More information on below link,
-http://riscv.org/software-tools/riscv-qemu/
-https://github.com/AbnerChang/RiscVQemuPcat.git
-
-**** Build RISC-V EDK2
-Before you build QEMU RISC-V EDK2, you need belwo package.
-*$sudo apt-get install uuid-dev
-*Change to your EDK2 open source directory.
-*$. edksetup.sh
-*Conf/target.txt
-ACTIVE_PLATFORM = RiscVVirtPkg/RiscVVirt64.dsc
-TARGET_ARCH = RISCV64
-TOOL_CHAIN_TAG = GCC711RISCV
-
-*$export PATH=$PATH:~/riscv/bin
-*$make -C BaseTools
-*$build
- - Without searil port debug log output.
-*$build -D DEBUG_ON_SERIAL_PORT
- - With searil port debug log output.
-
-**** Launch QEMU RISC-V PC/AT
-* Change directory to ~/RiscVQemuPcat/riscvpcat-softmmu
-* $./qemu-system-riscvpcat -bios RISCVVIRT.fd -usb -usbdevice keyboard
- - Launch RISC-V image *without* serial output.
-* $./qemu-system-riscvpcat -serial /dev/pts/8 -bios RISCVVIRT.fd -usb -usbdevice keyboard
- - Launch RISC-V image *with* serial output. The serial port in this case is /dev/pts/8.
diff --git a/RiscVVirtPkg/RiscVVirt.fdf.inc b/RiscVVirtPkg/RiscVVirt.fdf.inc
deleted file mode 100644
index 3dd7b30..0000000
--- a/RiscVVirtPkg/RiscVVirt.fdf.inc
+++ /dev/null
@@ -1,38 +0,0 @@
-## @file
-# RISC-V flash definition file on EFI/Framework Open Virtual Machine Firmware (OVMF) platform
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-DEFINE BLOCK_SIZE = 0x1000
-DEFINE VARS_SIZE = 0x20000
-DEFINE VARS_BLOCKS = 0x20
-
-DEFINE FW_BASE_ADDRESS = 0xFF800000
-DEFINE FW_SIZE = 0x00800000
-DEFINE FW_BLOCKS = 0x800
-#
-# FF800000-FF820000 is used by variable.
-#
-DEFINE CODE_BASE_ADDRESS = 0xFF820000
-DEFINE CODE_SIZE = 0x007E0000
-DEFINE CODE_BLOCKS = 0x7E0
-DEFINE FVMAIN_BASE = 0x0560000
-DEFINE FVMAIN_SIZE = 0x0018C000
-DEFINE PEIFV_OFFSET = 0x06EC000
-DEFINE PEIFV_SIZE = 0xE0000
-DEFINE SECFV_OFFSET = 0x007CC000
-DEFINE SECFV_SIZE = 0x34000
-
-SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress = $(FW_BASE_ADDRESS)
-SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize = $(FW_SIZE)
-SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize = $(BLOCK_SIZE)
-
diff --git a/RiscVVirtPkg/RiscVVirt64.dsc b/RiscVVirtPkg/RiscVVirt64.dsc
deleted file mode 100644
index f49df5a..0000000
--- a/RiscVVirtPkg/RiscVVirt64.dsc
+++ /dev/null
@@ -1,598 +0,0 @@
-## @file
-# RISC-V on EFI/Framework Open Virtual Machine Firmware (OVMF) platform
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
- PLATFORM_NAME = RiscvVirt
- PLATFORM_GUID = C0F221A1-6C0B-4370-A3AE-FD95D7BA6FF2
- PLATFORM_VERSION = 0.1
- DSC_SPECIFICATION = 0x00010005
- OUTPUT_DIRECTORY = Build/RiscVVirt64
- SUPPORTED_ARCHITECTURES = RISCV64
- BUILD_TARGETS = DEBUG|RELEASE
- SKUID_IDENTIFIER = DEFAULT
- FLASH_DEFINITION = RiscVVirtPkg/RiscVVirt64.fdf
-
- #
- # Enable below options may cause build error or may not work on
- # the initial version of RISC-V package
- # Defines for default states. These can be changed on the command line.
- # -D FLAG=VALUE
- #
- DEFINE SECURE_BOOT_ENABLE = FALSE
- DEFINE NETWORK_IP6_ENABLE = FALSE
- DEFINE HTTP_BOOT_ENABLE = FALSE
-
-[BuildOptions]
- GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
-!ifdef $(SOURCE_DEBUG_ENABLE)
- GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable
-!endif
-
-################################################################################
-#
-# SKU Identification section - list of all SKU IDs supported by this Platform.
-#
-################################################################################
-[SkuIds]
- 0|DEFAULT
-
-################################################################################
-#
-# Library Class section - list of all Library Classes needed by this Platform.
-#
-################################################################################
-[LibraryClasses]
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
- BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
- BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
- SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
- CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
- PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
- CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
- UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
- CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
- PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
- PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
- IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf
- UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
- UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
- UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
- UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
- UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
- DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
- FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
- SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
- UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
- CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
- SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf
- UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
-
-!ifdef $(SOURCE_DEBUG_ENABLE)
- PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
- DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
-!else
- PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
- DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
-!endif
-
- QemuFwCfgLib|RiscVVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
- ResetSystemLib|RiscVVirtPkg/Library/ResetSystemLib/ResetSystemLib.inf
-
- DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
-
-!if $(SECURE_BOOT_ENABLE) == TRUE
- IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
- OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
- TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
- AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
-!if $(NETWORK_IP6_ENABLE) == TRUE
- TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
-!endif
-!else
- TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
- AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
-!endif
- VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
-
-!if $(HTTP_BOOT_ENABLE) == TRUE
- HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
-!endif
-
- #S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
- SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
- OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
-
-[LibraryClasses.common]
-!if $(SECURE_BOOT_ENABLE) == TRUE
- BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
-!endif
- RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
- CpuExceptionHandlerLib|RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
-
-[LibraryClasses.common.SEC]
-!ifdef $(DEBUG_ON_SERIAL_PORT)
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-!else
- DebugLib|RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
-!endif
-
- ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
-
-!ifdef $(SOURCE_DEBUG_ENABLE)
- DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
-!endif
-
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
- RiscVPlatformTempMemoryInitLib|RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
-
-[LibraryClasses.common.PEI_CORE]
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
- PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.inf
- PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
- PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
- ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
-!ifdef $(DEBUG_ON_SERIAL_PORT)
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-!else
- DebugLib|RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
-!endif
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
-
-[LibraryClasses.common.PEIM]
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
- PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.inf
- PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
- PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
- ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
-!ifdef $(DEBUG_ON_SERIAL_PORT)
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-!else
- DebugLib|RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
-!endif
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
- PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
-!ifdef $(SOURCE_DEBUG_ENABLE)
- DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
-!endif
-
-[LibraryClasses.common.DXE_CORE]
- TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
- HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
- DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
- MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
-!ifdef $(DEBUG_ON_SERIAL_PORT)
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-!else
- DebugLib|RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
-!endif
- ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
-!ifdef $(SOURCE_DEBUG_ENABLE)
- DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
-!endif
- #CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
-
-[LibraryClasses.common.DXE_RUNTIME_DRIVER]
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
- DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
-!ifdef $(DEBUG_ON_SERIAL_PORT)
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-!else
- DebugLib|RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
-!endif
- UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
-!if $(SECURE_BOOT_ENABLE) == TRUE
- BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
-!endif
- UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
-
-[LibraryClasses.common.UEFI_DRIVER]
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
- DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
-!ifdef $(DEBUG_ON_SERIAL_PORT)
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-!else
- DebugLib|RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
-!endif
- UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
-
-[LibraryClasses.common.DXE_DRIVER]
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
- UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
-!ifdef $(DEBUG_ON_SERIAL_PORT)
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-!else
- DebugLib|RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
-!endif
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
-!ifdef $(SOURCE_DEBUG_ENABLE)
- DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
-!endif
- UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
- PlatformBootManagerLib|RiscVVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
- #CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
-
-[LibraryClasses.common.UEFI_APPLICATION]
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
-!ifdef $(DEBUG_ON_SERIAL_PORT)
- DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
-!else
- DebugLib|RiscVVirtPkg/Library/PlatformDebugLibIoPort/PlatformDebugLibIoPort.inf
-!endif
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
-
-[LibraryClasses.common.DXE_SMM_DRIVER]
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
-
-[LibraryClasses.common.SMM_CORE]
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
-
-################################################################################
-#
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
-#
-################################################################################
-[PcdsFeatureFlag]
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
-!if $(SECURE_BOOT_ENABLE) == TRUE
- gUefiOvmfPkgTokenSpaceGuid.PcdSecureBootEnable|TRUE
-!endif
-
-[PcdsFixedAtBuild]
- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1
- gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
- gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10
- gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxFvSupported|6
- gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|32
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
- gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
-
- gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
- gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
-!ifdef $(SOURCE_DEBUG_ENABLE)
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
-!else
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
-!endif
-
-!ifdef $(SOURCE_DEBUG_ENABLE)
- gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
-!endif
-
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
-
-!if $(SECURE_BOOT_ENABLE) == TRUE
- # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot
- gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
- gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
- gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
-!endif
-
- #
- # F2 for UI APP
- #
- gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
-
- # IRQs 5, 9, 10, 11 are level-triggered
- gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0E20
-
-################################################################################
-#
-# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
-#
-################################################################################
-
-[PcdsDynamicDefault]
- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0
-
- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0
-
- # Set video resolution for text setup.
- gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
- gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
-
- gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
- gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0
- gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE
-
-################################################################################
-#
-# Components Section - list of all EDK II Modules needed by this Platform.
-#
-################################################################################
-[Components]
- RiscVPkg/Universal/ResetVector/ResetVector.inf
-
- #
- # SEC Phase modules
- #
- RiscVPkg/Universal/Sec/SecMain.inf
-
- #
- # PEI Phase modules
- #
- MdeModulePkg/Core/Pei/PeiMain.inf
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
- <LibraryClasses>
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- }
- IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
- <LibraryClasses>
- NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- }
-
- RiscVVirtPkg/Universal/PlatformPei/PlatformPei.inf {
- <LibraryClasses>
- PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
- }
-
- #
- # DXE Phase modules
- #
- MdeModulePkg/Core/Dxe/DxeMain.inf {
- <LibraryClasses>
- NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
- }
-
- IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
- <LibraryClasses>
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- }
-
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
-
-!if $(SECURE_BOOT_ENABLE) == TRUE
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
- <LibraryClasses>
- NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
- }
-!else
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-!endif
-
- #
- # EBC not supported on RISC-V yet
- #
- #MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-
- PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
- <LibraryClasses>
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- }
- PcAtChipsetPkg/KbcResetDxe/Reset.inf
- MdeModulePkg/Universal/Metronome/Metronome.inf
- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
- MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
-
- #
- # RISC-V Packakge
- #
- RiscVPkg/Universal/TimerDxe/TimerDxe.inf
- RiscVPkg/Universal/CpuDxe/CpuDxe.inf
-
- #
- # RISC-V QEMU package
- #
- RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridgeDxe.inf
- OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
- OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf {
- <LibraryClasses>
- BltLib|OptionRomPkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
- }
-
- #
- # Power on screen badges
- #
- RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadgingDxe.inf
-
- #
- # XEN related drivers
- #
- OvmfPkg/XenIoPciDxe/XenIoPciDxe.inf
-
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
- <LibraryClasses>
- NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
- }
- MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf {
- <LibraryClasses>
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- }
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf {
- <LibraryClasses>
- DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- }
- MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
- MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
- IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf
- PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
-
- #
- # ISA Support
- #
- PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf
- IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
- IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
- IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
- IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/IsaFloppyDxe.inf
-
- #
- # SMBIOS Support
- #
- MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
-
- #
- # ACPI Support
- # Not support on RISC-V yet
- #
- #MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
- #MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
-
- #
- # Network Support
- #
- MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
- MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
- MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
-!if $(NETWORK_IP6_ENABLE) == TRUE
- NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- NetworkPkg/TcpDxe/TcpDxe.inf
- NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
-!if $(SECURE_BOOT_ENABLE) == TRUE
- NetworkPkg/IScsiDxe/IScsiDxe.inf
-!else
- MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
-!endif
-!else
- MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
- MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
-!endif
-!if $(HTTP_BOOT_ENABLE) == TRUE
- NetworkPkg/DnsDxe/DnsDxe.inf
- NetworkPkg/HttpDxe/HttpDxe.inf
- NetworkPkg/HttpBootDxe/HttpBootDxe.inf
-!endif
-
- #
- # Usb Support
- #
- MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
- MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
- MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
-
-
- ShellPkg/Application/Shell/Shell.inf {
- <LibraryClasses>
- ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
- NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
- NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
- HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
- ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
- FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
- SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
- PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
- BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
-
- <PcdsFixedAtBuild>
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
- gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
- gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
- }
-
-!if $(SECURE_BOOT_ENABLE) == TRUE
- SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
-!endif
-
- MdeModulePkg/Application/UiApp/UiApp.inf
diff --git a/RiscVVirtPkg/RiscVVirt64.fdf b/RiscVVirtPkg/RiscVVirt64.fdf
deleted file mode 100644
index ca38dd2..0000000
--- a/RiscVVirtPkg/RiscVVirt64.fdf
+++ /dev/null
@@ -1,418 +0,0 @@
-## @file
-# RISC-V flash definition file on EFI/Framework Open Virtual Machine Firmware (OVMF) platform
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-[Defines]
-
-!include RiscVVirt.fdf.inc
-
-#
-# Build the variable store and the firmware code as one unified flash device
-# image.
-#
-[FD.RISCVVIRT]
-BaseAddress = $(FW_BASE_ADDRESS)
-Size = $(FW_SIZE)
-ErasePolarity = 1
-BlockSize = $(BLOCK_SIZE)
-NumBlocks = $(FW_BLOCKS)
-
-!include VarStore.fdf.inc
-
-$(FVMAIN_BASE)|$(FVMAIN_SIZE)
-gUefiRiscVPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPkgTokenSpaceGuid.PcdRiscVDxeFvSize
-FV = FVMAIN_COMPACT
-
-$(PEIFV_OFFSET)|$(PEIFV_SIZE)
-gUefiRiscVPkgTokenSpaceGuid.PcdRiscVPeiFvBase|gUefiRiscVPkgTokenSpaceGuid.PcdRiscVPeiFvSize
-FV = PEIFV
-
-$(SECFV_OFFSET)|$(SECFV_SIZE)
-FV = SECFV
-
-################################################################################
-
-[FD.MEMFD]
-BaseAddress = 0x800000
-Size = 0x900000
-ErasePolarity = 1
-BlockSize = 0x10000
-NumBlocks = 0x90
-
-0x0000000|0x00001000
-gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize
-
-0x0001000|0x00001000
-gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
-
-0x00002000|0x00008000
-gUefiRiscVPkgTokenSpaceGuid.PcdRiscVSecPeiTempRamBase|gUefiRiscVPkgTokenSpaceGuid.PcdRiscVSecPeiTempRamSize
-
-0x0000A000|0x00008000
-gUefiOvmfPkgTokenSpaceGuid.PcdS3AcpiReservedMemoryBase|gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize
-
-0x00012000|0x000E0000
-gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize
-
-0x000F2000|0x00800000
-gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize
-
-################################################################################
-
-[FV.SECFV]
-BlockSize = 0x1000
-FvAlignment = 16
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-
-#
-# SEC Phase modules
-#
-# The code in this FV handles the initial firmware startup, and
-# decompresses the PEI and DXE FVs which handles the rest of the boot sequence.
-#
-INF RiscVPkg/Universal/Sec/SecMain.inf
-INF RuleOverride=RESET_VECTOR RiscVPkg/Universal/ResetVector/ResetVector.inf
-
-################################################################################
-[FV.PEIFV]
-BlockSize = 0x10000
-FvAlignment = 16
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-
-APRIORI PEI {
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
-}
-
-#
-# PEI Phase modules
-#
-INF MdeModulePkg/Core/Pei/PeiMain.inf
-INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
-INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
-INF RiscVVirtPkg/Universal/PlatformPei/PlatformPei.inf
-INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
-
-################################################################################
-
-[FV.DXEFV]
-BlockSize = 0x10000
-FvAlignment = 16
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-
-APRIORI DXE {
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
- INF OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
-}
-
-#
-# DXE Phase modules
-#
-INF MdeModulePkg/Core/Dxe/DxeMain.inf
-
-INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
-INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
-
-INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
-INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
-#INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
-INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
-INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
-INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
-INF OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
-INF RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridgeDxe.inf
-INF PcAtChipsetPkg/KbcResetDxe/Reset.inf
-INF MdeModulePkg/Universal/Metronome/Metronome.inf
-INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
-
-INF RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadgingDxe.inf
-INF RiscVPkg/Universal/TimerDxe/TimerDxe.inf
-INF RiscVPkg/Universal/CpuDxe/CpuDxe.inf
-INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
-
-#
-# XEN drivers
-#
-INF OvmfPkg/XenIoPciDxe/XenIoPciDxe.inf
-INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
-!if $(SECURE_BOOT_ENABLE) == TRUE
- INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
-!endif
-
-INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
-INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
-INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
-INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
-INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
-INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
-INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
-INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
-INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
-INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
-INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
-INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
-INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
-INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
-INF IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf
-INF PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf
-INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
-INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
-INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
-
-INF PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf
-INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
-
-!ifndef $(SOURCE_DEBUG_ENABLE)
-INF IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
-!endif
-
-INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
-INF IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/IsaFloppyDxe.inf
-
-INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
-
-#
-# ACPI is not supported yet on RISC-V package.
-#
-#INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
-#INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
-
-#INF RuleOverride = BINARY FatBinPkg/EnhancedFatDxe/Fat.inf
-
-INF ShellPkg/Application/Shell/Shell.inf
-
-FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {
- SECTION RAW = MdeModulePkg/Logo/Logo.bmp
-}
-
-FILE FREEFORM = PCD(gUefiRiscVVirtPkgTokenSpaceGuid.PcdRiscVLogoFile) {
- SECTION RAW = RiscVVirtPkg/Universal/Logo/RiscVLogo.bmp
-}
-
-#
-# Network modules
-#
-!if $(E1000_ENABLE)
- FILE DRIVER = 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 {
- SECTION PE32 = Intel3.5/EFIX64/E3507X2.EFI
- }
-!endif
- INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
- INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
-!if $(NETWORK_IP6_ENABLE) == TRUE
- INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
- INF NetworkPkg/TcpDxe/TcpDxe.inf
- INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
- INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
- INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
- INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
-!if $(SECURE_BOOT_ENABLE) == TRUE
- INF NetworkPkg/IScsiDxe/IScsiDxe.inf
-!else
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
-!endif
-!else
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
-!endif
-!if $(HTTP_BOOT_ENABLE) == TRUE
- INF NetworkPkg/DnsDxe/DnsDxe.inf
- INF NetworkPkg/HttpDxe/HttpDxe.inf
- INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
-!endif
-
-#
-# Usb Support
-#
-INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
-INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
-INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
-INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
-INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
-INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
-
-INF OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
-
-INF MdeModulePkg/Application/UiApp/UiApp.inf
-
-################################################################################
-
-[FV.FVMAIN_COMPACT]
-FvAlignment = 16
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-FvNameGuid = 27A72E80-3118-4c0c-8673-AA5B4EFA9613
-
-FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
- #
- # These firmware volumes will have files placed in them uncompressed,
- # and then both firmware volumes will be compressed in a single
- # compression operation in order to achieve better overall compression.
- #
- SECTION FV_IMAGE = DXEFV
- }
- }
-
-################################################################################
-
-[Rule.Common.SEC]
- FILE SEC = $(NAMED_GUID) {
- PE32 PE32 Align=64 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING ="$(MODULE_NAME)" Optional
- VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.PEI_CORE]
- FILE PEI_CORE = $(NAMED_GUID) {
- PE32 PE32 Align=64 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING ="$(MODULE_NAME)" Optional
- VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.PEIM]
- FILE PEIM = $(NAMED_GUID) {
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 Align=64 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.DXE_CORE]
- FILE DXE_CORE = $(NAMED_GUID) {
- PE32 PE32 Align=64 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.DXE_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 Align=64 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.DXE_RUNTIME_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 Align=64 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.UEFI_DRIVER]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 Align=64 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.UEFI_DRIVER.BINARY]
- FILE DRIVER = $(NAMED_GUID) {
- DXE_DEPEX DXE_DEPEX Optional |.depex
- PE32 PE32 Align=64 |.efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.UEFI_APPLICATION]
- FILE APPLICATION = $(NAMED_GUID) {
- PE32 PE32 Align=64 $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.UEFI_APPLICATION.BINARY]
- FILE APPLICATION = $(NAMED_GUID) {
- PE32 PE32 Align=64 |.efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.USER_DEFINED.ACPITABLE]
- FILE FREEFORM = $(NAMED_GUID) {
- RAW ACPI |.acpi
- RAW ASL |.aml
- }
-
-[Rule.Common.SEC.RESET_VECTOR]
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- PE32 PE32 Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
- }
diff --git a/RiscVVirtPkg/RiscVVirtPkg.dec b/RiscVVirtPkg/RiscVVirtPkg.dec
deleted file mode 100644
index 9cf22af..0000000
--- a/RiscVVirtPkg/RiscVVirtPkg.dec
+++ /dev/null
@@ -1,41 +0,0 @@
-## @file
-# RISC-V EFI/Framework Open Virtual Machine Firmware (OVMF) platform
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- DEC_SPECIFICATION = 0x00010005
- PACKAGE_NAME = RiscVVirtPkg
- PACKAGE_GUID = 9F2A0F50-4421-465C-A064-CDAD6DCABE75
- PACKAGE_VERSION = 0.1
-
-[Includes]
-
-[LibraryClasses]
-
-[Guids]
- gUefiRiscVVirtPkgTokenSpaceGuid = { 0xbdaf02c7, 0xbe60, 0x421d, { 0xad, 0x3e, 0xf0, 0x55, 0xf7, 0x92, 0x4c, 0x03 }}
-
-[Protocols]
-
-[PcdsFixedAtBuild]
- #
- # POST screen logo
- #
- gUefiRiscVVirtPkgTokenSpaceGuid.PcdRiscVLogoFile |{ 0x16, 0x9e, 0x32, 0x67, 0xd3, 0x19, 0xca, 0x46, 0x9f, 0x2e, 0xa3, 0x73, 0x1a, 0x5f, 0xb3, 0x39 }|VOID*|0x00001000
- gUefiRiscVVirtPkgTokenSpaceGuid.PcdAcpiPmBaseAddress|0xB000|UINT16|1
-
-[PcdsDynamic, PcdsDynamicEx]
-
-[PcdsFeatureFlag]
-
diff --git a/RiscVVirtPkg/Universal/Logo/Logo.uni b/RiscVVirtPkg/Universal/Logo/Logo.uni
deleted file mode 100644
index db917c3f800a4e05e29d1fc3f55b978a2fda5a8c..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001
literal 1948
zcmd6oTW`}q5QXO%iT_}wFM!$xc;EpcMAI0EC{2_m6rQTwW09L2Cn0|x_|9w-*C<?`
z09m{1-I<*^b7sc=_O)zfix`i1B70>+OKf5TyKnb6m8@lB_L23Oht{zb@{Ik&<~CwP
z*5yuSQ)CNv3wAyBD@*;}lKXSp*bLd+=OyQoOM8i~^ad^&qLFgiw3=Pnxt-VtJKbX`
zVoJCh;dKr&VG_m#x97G7fzV2x{WbK5aGrx^VOvloa5V-^WDkh=A?s6nY)|Z&9rOMc
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diff --git a/RiscVVirtPkg/Universal/Logo/LogoExtra.uni b/RiscVVirtPkg/Universal/Logo/LogoExtra.uni
deleted file mode 100644
index 665fbcdd65fba831d97c9f0d01f4179493f5ee2e..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/RiscVVirtPkg/Universal/Logo/RiscVLogo.bmp b/RiscVVirtPkg/Universal/Logo/RiscVLogo.bmp
deleted file mode 100644
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GIT binary patch
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diff --git a/RiscVVirtPkg/Universal/Logo/RiscVLogo.inf b/RiscVVirtPkg/Universal/Logo/RiscVLogo.inf
deleted file mode 100644
index cdd11b8..0000000
--- a/RiscVVirtPkg/Universal/Logo/RiscVLogo.inf
+++ /dev/null
@@ -1,34 +0,0 @@
-## @file
-# The default logo bitmap picture shown on setup screen.
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = Logo
- MODULE_UNI_FILE = Logo.uni
- FILE_GUID = 67329E16-19D3-46CA-9F2E-A3731A5FB339
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV32 RISCV64 RISCV128
-#
-
-[Binaries]
- BIN|RiscVLogo.bmp|*
-
-[UserExtensions.TianoCore."ExtraFiles"]
- LogoExtra.uni
diff --git a/RiscVVirtPkg/Universal/PciHostBridgeDxe/Ia32/IoFifo.S b/RiscVVirtPkg/Universal/PciHostBridgeDxe/Ia32/IoFifo.S
deleted file mode 100644
index 03a014d..0000000
--- a/RiscVVirtPkg/Universal/PciHostBridgeDxe/Ia32/IoFifo.S
+++ /dev/null
@@ -1,134 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials are licensed and made available
-# under the terms and conditions of the BSD License which accompanies this
-# distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoReadFifo8 (
-# IN UINTN Port,
-# IN UINTN Count,
-# IN VOID *Buffer
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoReadFifo8)
-ASM_PFX(IoReadFifo8):
- push %edi
- cld
- movw 8(%esp), %dx
- mov 12(%esp), %ecx
- mov 16(%esp), %edi
-rep insb
- pop %edi
- ret
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoReadFifo16 (
-# IN UINTN Port,
-# IN UINTN Count,
-# IN VOID *Buffer
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoReadFifo16)
-ASM_PFX(IoReadFifo16):
- push %edi
- cld
- movw 8(%esp), %dx
- mov 12(%esp), %ecx
- mov 16(%esp), %edi
-rep insw
- pop %edi
- ret
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoReadFifo32 (
-# IN UINTN Port,
-# IN UINTN Count,
-# IN VOID *Buffer
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoReadFifo32)
-ASM_PFX(IoReadFifo32):
- push %edi
- cld
- movw 8(%esp), %dx
- mov 12(%esp), %ecx
- mov 16(%esp), %edi
-rep insl
- pop %edi
- ret
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoWriteFifo8 (
-# IN UINTN Port,
-# IN UINTN Count,
-# IN VOID *Buffer
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoWriteFifo8)
-ASM_PFX(IoWriteFifo8):
- push %esi
- cld
- movw 8(%esp), %dx
- mov 12(%esp), %ecx
- mov 16(%esp), %esi
-rep outsb
- pop %esi
- ret
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoWriteFifo16 (
-# IN UINTN Port,
-# IN UINTN Count,
-# IN VOID *Buffer
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoWriteFifo16)
-ASM_PFX(IoWriteFifo16):
- push %esi
- cld
- movw 8(%esp), %dx
- mov 12(%esp), %ecx
- mov 16(%esp), %esi
-rep outsw
- pop %esi
- ret
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoWriteFifo32 (
-# IN UINTN Port,
-# IN UINTN Count,
-# IN VOID *Buffer
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoWriteFifo32)
-ASM_PFX(IoWriteFifo32):
- push %esi
- cld
- movw 8(%esp), %dx
- mov 12(%esp), %ecx
- mov 16(%esp), %esi
-rep outsl
- pop %esi
- ret
-
diff --git a/RiscVVirtPkg/Universal/PciHostBridgeDxe/Ia32/IoFifo.asm b/RiscVVirtPkg/Universal/PciHostBridgeDxe/Ia32/IoFifo.asm
deleted file mode 100644
index b1cc25e..0000000
--- a/RiscVVirtPkg/Universal/PciHostBridgeDxe/Ia32/IoFifo.asm
+++ /dev/null
@@ -1,140 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-;
-; This program and the accompanying materials are licensed and made available
-; under the terms and conditions of the BSD License which accompanies this
-; distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php.
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- .586P
- .model flat,C
- .code
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoReadFifo8 (
-; IN UINTN Port,
-; IN UINTN Size,
-; IN VOID *Buffer
-; );
-;------------------------------------------------------------------------------
-IoReadFifo8 PROC
- push edi
- cld
- mov dx, [esp + 8]
- mov ecx, [esp + 12]
- mov edi, [esp + 16]
-rep insb
- pop edi
- ret
-IoReadFifo8 ENDP
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoReadFifo16 (
-; IN UINTN Port,
-; IN UINTN Size,
-; IN VOID *Buffer
-; );
-;------------------------------------------------------------------------------
-IoReadFifo16 PROC
- push edi
- cld
- mov dx, [esp + 8]
- mov ecx, [esp + 12]
- mov edi, [esp + 16]
-rep insw
- pop edi
- ret
-IoReadFifo16 ENDP
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoReadFifo32 (
-; IN UINTN Port,
-; IN UINTN Size,
-; IN VOID *Buffer
-; );
-;------------------------------------------------------------------------------
-IoReadFifo32 PROC
- push edi
- cld
- mov dx, [esp + 8]
- mov ecx, [esp + 12]
- mov edi, [esp + 16]
-rep insd
- pop edi
- ret
-IoReadFifo32 ENDP
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoWriteFifo8 (
-; IN UINTN Port,
-; IN UINTN Size,
-; IN VOID *Buffer
-; );
-;------------------------------------------------------------------------------
-IoWriteFifo8 PROC
- push esi
- cld
- mov dx, [esp + 8]
- mov ecx, [esp + 12]
- mov esi, [esp + 16]
-rep outsb
- pop esi
- ret
-IoWriteFifo8 ENDP
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoWriteFifo16 (
-; IN UINTN Port,
-; IN UINTN Size,
-; IN VOID *Buffer
-; );
-;------------------------------------------------------------------------------
-IoWriteFifo16 PROC
- push esi
- cld
- mov dx, [esp + 8]
- mov ecx, [esp + 12]
- mov esi, [esp + 16]
-rep outsw
- pop esi
- ret
-IoWriteFifo16 ENDP
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoWriteFifo32 (
-; IN UINTN Port,
-; IN UINTN Size,
-; IN VOID *Buffer
-; );
-;------------------------------------------------------------------------------
-IoWriteFifo32 PROC
- push esi
- cld
- mov dx, [esp + 8]
- mov ecx, [esp + 12]
- mov esi, [esp + 16]
-rep outsd
- pop esi
- ret
-IoWriteFifo32 ENDP
-
- END
-
diff --git a/RiscVVirtPkg/Universal/PciHostBridgeDxe/IoFifo.h b/RiscVVirtPkg/Universal/PciHostBridgeDxe/IoFifo.h
deleted file mode 100644
index 9978f8b..0000000
--- a/RiscVVirtPkg/Universal/PciHostBridgeDxe/IoFifo.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/** @file
- I/O FIFO routines
-
- Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available
- under the terms and conditions of the BSD License which accompanies this
- distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _IO_FIFO_H_INCLUDED_
-#define _IO_FIFO_H_INCLUDED_
-
-/**
- Reads an 8-bit I/O port fifo into a block of memory.
-
- Reads the 8-bit I/O fifo port specified by Port.
-
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- );
-
-/**
- Reads a 16-bit I/O port fifo into a block of memory.
-
- Reads the 16-bit I/O fifo port specified by Port.
-
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo16 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- );
-
-/**
- Reads a 32-bit I/O port fifo into a block of memory.
-
- Reads the 32-bit I/O fifo port specified by Port.
-
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo32 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- );
-
-/**
- Writes a block of memory into an 8-bit I/O port fifo.
-
- Writes the 8-bit I/O fifo port specified by Port.
-
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to store the write data into.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- );
-
-/**
- Writes a block of memory into a 16-bit I/O port fifo.
-
- Writes the 16-bit I/O fifo port specified by Port.
-
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to store the write data into.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo16 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- );
-
-/**
- Writes a block of memory into a 32-bit I/O port fifo.
-
- Writes the 32-bit I/O fifo port specified by Port.
-
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to store the write data into.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo32 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- );
-
-#endif
-
diff --git a/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridge.c b/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridge.c
deleted file mode 100644
index efef2ed..0000000
--- a/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridge.c
+++ /dev/null
@@ -1,1551 +0,0 @@
-/** @file
- Provides the basic interfaces to abstract a PCI Host Bridge Resource
- Allocation
-
- Copyright (C) 2015, Red Hat, Inc.
- Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available
- under the terms and conditions of the BSD License which accompanies this
- distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Library/QemuFwCfgLib.h>
-
-#include "PciHostBridge.h"
-
-STATIC
-CONST
-EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
- {
- {
- ACPI_DEVICE_PATH,
- ACPI_DP,
- {
- (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
- (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
- }
- },
- EISA_PNP_ID(0x0A03), // HID
- 0 // UID
- },
-
- {
- END_DEVICE_PATH_TYPE,
- END_ENTIRE_DEVICE_PATH_SUBTYPE,
- {
- END_DEVICE_PATH_LENGTH,
- 0
- }
- }
-};
-
-EFI_HANDLE mDriverImageHandle;
-
-PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
- PCI_HOST_BRIDGE_SIGNATURE, // Signature
- NULL, // HostBridgeHandle
- {NULL, NULL}, // Head
- FALSE, // ResourceSubiteed
- TRUE, // CanRestarted
- {
- NotifyPhase,
- GetNextRootBridge,
- GetAttributes,
- StartBusEnumeration,
- SetBusNumbers,
- SubmitResources,
- GetProposedResources,
- PreprocessController
- }
-};
-
-//
-// Implementation
-//
-
-/**
- Allocate and initialize a root bridge.
-
- param[in] RootBusNumber The bus number of the root bus (root bridge) to
- create.
-
- param[in] MaxSubBusNumber The inclusive maximum bus number that can be
- assigned to any subordinate bus found behind any
- PCI bridge hanging off this root bus.
-
- The caller is repsonsible for ensuring that
- RootBusNumber <= MaxSubBusNumber. If
- RootBusNumber equals MaxSubBusNumber, then the
- root bus has no room for subordinate buses.
-
- param[in] HostBridgeHandle The EFI_HANDLE corresponding to the host bridge
- that is the parent of the root bridge to create.
- HostBridgeHandle is expected to have
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- installed on it.
-
- param[out] RootBus The private PCI_ROOT_BRIDGE_INSTANCE that has
- been created as the result of the function call.
-
- @retval EFI_SUCCESS Initialization successful. A new
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL has been
- created as the child of HostBridgeHandle. A
- device path consisting of an ACPI device path
- node, with UID = RootBusNumber, has been
- installed on the same new handle.
-
- @retval EFI_OUT_OF_RESOURCES Memory allocation failed.
-
- @return Error codes from
- gBS->InstallMultipleProtocolInterfaces().
-**/
-STATIC
-EFI_STATUS
-InitRootBridge (
- IN UINT8 RootBusNumber,
- IN UINT8 MaxSubBusNumber,
- IN EFI_HANDLE HostBridgeHandle,
- OUT PCI_ROOT_BRIDGE_INSTANCE **RootBus
- )
-{
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
- PCI_ROOT_BRIDGE_RESOURCE_APERTURE ResAperture;
- EFI_STATUS Status;
-
- ASSERT (RootBusNumber <= MaxSubBusNumber);
-
- PrivateData = AllocateZeroPool (sizeof *PrivateData);
- if (PrivateData == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
-
- CopyMem (&PrivateData->DevicePath, &mRootBridgeDevicePathTemplate,
- sizeof mRootBridgeDevicePathTemplate);
- PrivateData->DevicePath.AcpiDevicePath.UID = RootBusNumber;
-
- ResAperture.BusBase = RootBusNumber;
- ResAperture.BusLimit = MaxSubBusNumber;
- ResAperture.MemBase = BASE_2GB;
- ResAperture.MemLimit = BASE_4GB - 1;
- ResAperture.IoBase = 0;
- ResAperture.IoLimit = MAX_UINT16;
- //
- // The function call below allocates no resources and performs no actions
- // that have to be rolled back on later failure. It always succeeds.
- //
- Status = RootBridgeConstructor (&PrivateData->Io, HostBridgeHandle,
- EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM, &ResAperture);
- ASSERT_EFI_ERROR (Status);
-
- Status = gBS->InstallMultipleProtocolInterfaces (&PrivateData->Handle,
- &gEfiDevicePathProtocolGuid, &PrivateData->DevicePath,
- &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,
- NULL);
- if (EFI_ERROR (Status)) {
- goto FreePrivateData;
- }
-
- DEBUG ((EFI_D_INFO,
- "%a: installed root bus %d, with room for %d subordinate bus(es)\n",
- __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));
- *RootBus = PrivateData;
- return EFI_SUCCESS;
-
-FreePrivateData:
- FreePool (PrivateData);
- return Status;
-}
-
-
-/**
- Uninitialize and free a root bridge set up with InitRootBridge().
-
- On return, the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance and the device path
- will have been released, freeing RootBus->Handle as well.
-
- param[in] RootBus The private PCI_ROOT_BRIDGE_INSTANCE that has been created
- with InitRootBridge(), and should be released.
-**/
-STATIC
-VOID
-UninitRootBridge (
- IN PCI_ROOT_BRIDGE_INSTANCE *RootBus
- )
-{
- EFI_STATUS Status;
-
- Status = gBS->UninstallMultipleProtocolInterfaces (RootBus->Handle,
- &gEfiDevicePathProtocolGuid, &RootBus->DevicePath,
- &gEfiPciRootBridgeIoProtocolGuid, &RootBus->Io,
- NULL);
- ASSERT_EFI_ERROR (Status);
- FreePool (RootBus);
-}
-
-
-/**
- Entry point of this driver
-
- @param ImageHandle Handle of driver image
- @param SystemTable Point to EFI_SYSTEM_TABLE
-
- @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource
- @retval EFI_DEVICE_ERROR Can not install the protocol instance
- @retval EFI_SUCCESS Success to initialize the Pci host bridge.
-**/
-EFI_STATUS
-EFIAPI
-InitializePciHostBridge (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- FIRMWARE_CONFIG_ITEM FwCfgItem;
- UINTN FwCfgSize;
- UINT64 ExtraRootBridgesLeft;
- UINTN LastRootBridgeNumber;
- UINTN RootBridgeNumber;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *RootBus;
- EFI_STATUS UninstallStatus;
-
- mDriverImageHandle = ImageHandle;
-
- //
- // Create Host Bridge Device Handle
- //
- HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE),
- &mPciHostBridgeInstanceTemplate);
- if (HostBridge == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- InitializeListHead (&HostBridge->Head);
-
- Status = gBS->InstallMultipleProtocolInterfaces (
- &HostBridge->HostBridgeHandle,
- &gEfiPciHostBridgeResourceAllocationProtocolGuid,
- &HostBridge->ResAlloc,
- NULL
- );
- if (EFI_ERROR (Status)) {
- goto FreeHostBridge;
- }
-
- //
- // QEMU provides the number of extra root buses, shortening the exhaustive
- // search below. If there is no hint, the feature is missing.
- //
- Status = QemuFwCfgFindFile ("etc/extra-pci-roots", &FwCfgItem, &FwCfgSize);
- if (EFI_ERROR (Status) || FwCfgSize != sizeof ExtraRootBridgesLeft) {
- ExtraRootBridgesLeft = 0;
- } else {
- QemuFwCfgSelectItem (FwCfgItem);
- QemuFwCfgReadBytes (FwCfgSize, &ExtraRootBridgesLeft);
- DEBUG ((EFI_D_INFO, "%a: %Lu extra root buses reported by QEMU\n",
- __FUNCTION__, ExtraRootBridgesLeft));
- }
-
- //
- // The "main" root bus is always there.
- //
- LastRootBridgeNumber = 0;
-
- //
- // Scan all other root buses. If function 0 of any device on a bus returns a
- // VendorId register value different from all-bits-one, then that bus is
- // alive.
- //
- for (RootBridgeNumber = 1;
- RootBridgeNumber < 256 && ExtraRootBridgesLeft > 0;
- ++RootBridgeNumber) {
- UINTN Device;
-
- for (Device = 0; Device <= MAX_PCI_DEVICE_NUMBER; ++Device) {
- if (PciRead16 (PCI_LIB_ADDRESS (RootBridgeNumber, Device, 0,
- PCI_VENDOR_ID_OFFSET)) != MAX_UINT16) {
- break;
- }
- }
- if (Device <= MAX_PCI_DEVICE_NUMBER) {
- //
- // Found the next root bus. We can now install the *previous* one,
- // because now we know how big a bus number range *that* one has, for any
- // subordinate buses that might exist behind PCI bridges hanging off it.
- //
- Status = InitRootBridge ((UINT8)LastRootBridgeNumber,
- (UINT8)(RootBridgeNumber - 1), HostBridge->HostBridgeHandle,
- &RootBus);
- if (EFI_ERROR (Status)) {
- goto RollbackProtocols;
- }
- InsertTailList (&HostBridge->Head, &RootBus->Link);
- LastRootBridgeNumber = RootBridgeNumber;
- --ExtraRootBridgesLeft;
- }
- }
-
- //
- // Install the last root bus (which might be the only, ie. main, root bus, if
- // we've found no extra root buses).
- //
- Status = InitRootBridge ((UINT8)LastRootBridgeNumber, 255,
- HostBridge->HostBridgeHandle, &RootBus);
- if (EFI_ERROR (Status)) {
- goto RollbackProtocols;
- }
- InsertTailList (&HostBridge->Head, &RootBus->Link);
-
- return EFI_SUCCESS;
-
-RollbackProtocols:
- while (!IsListEmpty (&HostBridge->Head)) {
- LIST_ENTRY *Entry;
-
- Entry = GetFirstNode (&HostBridge->Head);
- RemoveEntryList (Entry);
- RootBus = DRIVER_INSTANCE_FROM_LIST_ENTRY (Entry);
- UninitRootBridge (RootBus);
- }
- UninstallStatus = gBS->UninstallMultipleProtocolInterfaces (
- HostBridge->HostBridgeHandle,
- &gEfiPciHostBridgeResourceAllocationProtocolGuid,
- &HostBridge->ResAlloc,
- NULL
- );
- ASSERT_EFI_ERROR (UninstallStatus);
-
-FreeHostBridge:
- FreePool (HostBridge);
-
- return Status;
-}
-
-
-/**
- These are the notifications from the PCI bus driver that it is about to enter
- a certain phase of the PCI enumeration process.
-
- This member function can be used to notify the host bridge driver to perform
- specific actions, including any chipset-specific initialization, so that the
- chipset is ready to enter the next phase. Eight notification points are
- defined at this time. See belows:
-
- EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures
- and internal data structures. The PCI
- enumerator should issue this
- notification before starting a fresh
- enumeration process. Enumeration
- cannot be restarted after sending any
- other notification such as
- EfiPciHostBridgeBeginBusAllocation.
-
- EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to
- begin. No specific action is required
- here. This notification can be used to
- perform any chipset-specific
- programming.
-
- EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming
- phase is complete. No specific action
- is required here. This notification
- can be used to perform any
- chipset-specific programming.
-
- EfiPciHostBridgeBeginResourceAllocation
- The resource allocation phase is about
- to begin. No specific action is
- required here. This notification can
- be used to perform any
- chipset-specific programming.
-
- EfiPciHostBridgeAllocateResources Allocates resources per previously
- submitted requests for all the PCI
- root bridges. These resource settings
- are returned on the next call to
- GetProposedResources(). Before calling
- NotifyPhase() with a Phase of
- EfiPciHostBridgeAllocateResource, the
- PCI bus enumerator is responsible for
- gathering I/O and memory requests for
- all the PCI root bridges and
- submitting these requests using
- SubmitResources(). This function pads
- the resource amount to suit the root
- bridge hardware, takes care of
- dependencies between the PCI root
- bridges, and calls the Global
- Coherency Domain (GCD) with the
- allocation request. In the case of
- padding, the allocated range could be
- bigger than what was requested.
-
- EfiPciHostBridgeSetResources Programs the host bridge hardware to
- decode previously allocated resources
- (proposed resources) for all the PCI
- root bridges. After the hardware is
- programmed, reassigning resources will
- not be supported. The bus settings are
- not affected.
-
- EfiPciHostBridgeFreeResources Deallocates resources that were
- previously allocated for all the PCI
- root bridges and resets the I/O and
- memory apertures to their initial
- state. The bus settings are not
- affected. If the request to allocate
- resources fails, the PCI enumerator
- can use this notification to
- deallocate previous resources, adjust
- the requests, and retry allocation.
-
- EfiPciHostBridgeEndResourceAllocation The resource allocation phase is
- completed. No specific action is
- required here. This notification can
- be used to perform any chipsetspecific
- programming.
-
- @param[in] This The instance pointer of
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
-
- @param[in] Phase The phase during enumeration
-
- @retval EFI_NOT_READY This phase cannot be entered at this time. For
- example, this error is valid for a Phase of
- EfiPciHostBridgeAllocateResources if
- SubmitResources() has not been called for one
- or more PCI root bridges before this call
-
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
- This error is valid for a Phase of
- EfiPciHostBridgeSetResources.
-
- @retval EFI_INVALID_PARAMETER Invalid phase parameter
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources. This error is valid for a
- Phase of EfiPciHostBridgeAllocateResources if
- the previously submitted resource requests
- cannot be fulfilled or were only partially
- fulfilled.
-
- @retval EFI_SUCCESS The notification was accepted without any
- errors.
-**/
-EFI_STATUS
-EFIAPI
-NotifyPhase(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
- )
-{
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- PCI_RESOURCE_TYPE Index;
- LIST_ENTRY *List;
- EFI_PHYSICAL_ADDRESS BaseAddress;
- UINT64 AddrLen;
- UINTN BitsOfAlignment;
- EFI_STATUS Status;
- EFI_STATUS ReturnStatus;
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
-
- switch (Phase) {
-
- case EfiPciHostBridgeBeginEnumeration:
- if (HostBridgeInstance->CanRestarted) {
- //
- // Reset the Each Root Bridge
- //
- List = HostBridgeInstance->Head.ForwardLink;
-
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- for (Index = TypeIo; Index < TypeMax; Index++) {
- RootBridgeInstance->ResAllocNode[Index].Type = Index;
- RootBridgeInstance->ResAllocNode[Index].Base = 0;
- RootBridgeInstance->ResAllocNode[Index].Length = 0;
- RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
- }
-
- List = List->ForwardLink;
- }
-
- HostBridgeInstance->ResourceSubmited = FALSE;
- HostBridgeInstance->CanRestarted = TRUE;
- } else {
- //
- // Can not restart
- //
- return EFI_NOT_READY;
- }
- break;
-
- case EfiPciHostBridgeEndEnumeration:
- break;
-
- case EfiPciHostBridgeBeginBusAllocation:
- //
- // No specific action is required here, can perform any chipset specific
- // programing
- //
- HostBridgeInstance->CanRestarted = FALSE;
- break;
-
- case EfiPciHostBridgeEndBusAllocation:
- //
- // No specific action is required here, can perform any chipset specific
- // programing
- //
- //HostBridgeInstance->CanRestarted = FALSE;
- break;
-
- case EfiPciHostBridgeBeginResourceAllocation:
- //
- // No specific action is required here, can perform any chipset specific
- // programing
- //
- //HostBridgeInstance->CanRestarted = FALSE;
- break;
-
- case EfiPciHostBridgeAllocateResources:
- ReturnStatus = EFI_SUCCESS;
- if (HostBridgeInstance->ResourceSubmited) {
- //
- // Take care of the resource dependencies between the root bridges
- //
- List = HostBridgeInstance->Head.ForwardLink;
-
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- for (Index = TypeIo; Index < TypeBus; Index++) {
- if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
-
- AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
-
- //
- // Get the number of '1' in Alignment.
- //
- BitsOfAlignment =
- (UINTN)(HighBitSet64 (
- RootBridgeInstance->ResAllocNode[Index].Alignment
- ) + 1);
-
- switch (Index) {
-
- case TypeIo:
- //
- // It is impossible for this chipset to align 0xFFFF for IO16
- // So clear it
- //
- if (BitsOfAlignment >= 16) {
- BitsOfAlignment = 0;
- }
-
- Status = gDS->AllocateIoSpace (
- EfiGcdAllocateAnySearchBottomUp,
- EfiGcdIoTypeIo,
- BitsOfAlignment,
- AddrLen,
- &BaseAddress,
- mDriverImageHandle,
- NULL
- );
-
- if (!EFI_ERROR (Status)) {
- RootBridgeInstance->ResAllocNode[Index].Base =
- (UINTN)BaseAddress;
- RootBridgeInstance->ResAllocNode[Index].Status =
- ResAllocated;
- } else {
- ReturnStatus = Status;
- if (Status != EFI_OUT_OF_RESOURCES) {
- RootBridgeInstance->ResAllocNode[Index].Length = 0;
- }
- }
-
- break;
-
-
- case TypeMem32:
- //
- // It is impossible for this chipset to align 0xFFFFFFFF for
- // Mem32
- // So clear it
- //
-
- if (BitsOfAlignment >= 32) {
- BitsOfAlignment = 0;
- }
-
- Status = gDS->AllocateMemorySpace (
- EfiGcdAllocateAnySearchBottomUp,
- EfiGcdMemoryTypeMemoryMappedIo,
- BitsOfAlignment,
- AddrLen,
- &BaseAddress,
- mDriverImageHandle,
- NULL
- );
-
- if (!EFI_ERROR (Status)) {
- // We were able to allocate the PCI memory
- RootBridgeInstance->ResAllocNode[Index].Base =
- (UINTN)BaseAddress;
- RootBridgeInstance->ResAllocNode[Index].Status =
- ResAllocated;
-
- } else {
- // Not able to allocate enough PCI memory
- ReturnStatus = Status;
-
- if (Status != EFI_OUT_OF_RESOURCES) {
- RootBridgeInstance->ResAllocNode[Index].Length = 0;
- }
- ASSERT (FALSE);
- }
- break;
-
- case TypePMem32:
- case TypeMem64:
- case TypePMem64:
- ReturnStatus = EFI_ABORTED;
- break;
- default:
- ASSERT (FALSE);
- break;
- }; //end switch
- }
- }
-
- List = List->ForwardLink;
- }
-
- return ReturnStatus;
-
- } else {
- return EFI_NOT_READY;
- }
- break;
-
- case EfiPciHostBridgeSetResources:
- break;
-
- case EfiPciHostBridgeFreeResources:
- ReturnStatus = EFI_SUCCESS;
- List = HostBridgeInstance->Head.ForwardLink;
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- for (Index = TypeIo; Index < TypeBus; Index++) {
- if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {
- AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
- BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;
- switch (Index) {
-
- case TypeIo:
- Status = gDS->FreeIoSpace (BaseAddress, AddrLen);
- if (EFI_ERROR (Status)) {
- ReturnStatus = Status;
- }
- break;
-
- case TypeMem32:
- Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);
- if (EFI_ERROR (Status)) {
- ReturnStatus = Status;
- }
- break;
-
- case TypePMem32:
- break;
-
- case TypeMem64:
- break;
-
- case TypePMem64:
- break;
-
- default:
- ASSERT (FALSE);
- break;
-
- }; //end switch
- RootBridgeInstance->ResAllocNode[Index].Type = Index;
- RootBridgeInstance->ResAllocNode[Index].Base = 0;
- RootBridgeInstance->ResAllocNode[Index].Length = 0;
- RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
- }
- }
-
- List = List->ForwardLink;
- }
-
- HostBridgeInstance->ResourceSubmited = FALSE;
- HostBridgeInstance->CanRestarted = TRUE;
- return ReturnStatus;
-
- case EfiPciHostBridgeEndResourceAllocation:
- HostBridgeInstance->CanRestarted = FALSE;
- break;
-
- default:
- return EFI_INVALID_PARAMETER;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Return the device handle of the next PCI root bridge that is associated with
- this Host Bridge.
-
- This function is called multiple times to retrieve the device handles of all
- the PCI root bridges that are associated with this PCI host bridge. Each PCI
- host bridge is associated with one or more PCI root bridges. On each call,
- the handle that was returned by the previous call is passed into the
- interface, and on output the interface returns the device handle of the next
- PCI root bridge. The caller can use the handle to obtain the instance of the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL for that root bridge. When there are no more
- PCI root bridges to report, the interface returns EFI_NOT_FOUND. A PCI
- enumerator must enumerate the PCI root bridges in the order that they are
- returned by this function.
-
- For D945 implementation, there is only one root bridge in PCI host bridge.
-
- @param[in] This The instance pointer of
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
-
- @param[in, out] RootBridgeHandle Returns the device handle of the next PCI
- root bridge.
-
- @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then
- return the first Rootbridge handle of the
- specific Host bridge and return EFI_SUCCESS.
-
- @retval EFI_NOT_FOUND Can not find the any more root bridge in
- specific host bridge.
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
- returned on a previous call to
- GetNextRootBridge().
-**/
-EFI_STATUS
-EFIAPI
-GetNextRootBridge(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN OUT EFI_HANDLE *RootBridgeHandle
- )
-{
- BOOLEAN NoRootBridge;
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
-
- NoRootBridge = TRUE;
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
-
- while (List != &HostBridgeInstance->Head) {
- NoRootBridge = FALSE;
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (*RootBridgeHandle == NULL) {
- //
- // Return the first Root Bridge Handle of the Host Bridge
- //
- *RootBridgeHandle = RootBridgeInstance->Handle;
- return EFI_SUCCESS;
- } else {
- if (*RootBridgeHandle == RootBridgeInstance->Handle) {
- //
- // Get next if have
- //
- List = List->ForwardLink;
- if (List!=&HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- *RootBridgeHandle = RootBridgeInstance->Handle;
- return EFI_SUCCESS;
- } else {
- return EFI_NOT_FOUND;
- }
- }
- }
-
- List = List->ForwardLink;
- } //end while
-
- if (NoRootBridge) {
- return EFI_NOT_FOUND;
- } else {
- return EFI_INVALID_PARAMETER;
- }
-}
-
-/**
- Returns the allocation attributes of a PCI root bridge.
-
- The function returns the allocation attributes of a specific PCI root bridge.
- The attributes can vary from one PCI root bridge to another. These attributes
- are different from the decode-related attributes that are returned by the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
- RootBridgeHandle parameter is used to specify the instance of the PCI root
- bridge. The device handles of all the root bridges that are associated with
- this host bridge must be obtained by calling GetNextRootBridge(). The
- attributes are static in the sense that they do not change during or after
- the enumeration process. The hardware may provide mechanisms to change the
- attributes on the fly, but such changes must be completed before
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is installed. The permitted
- values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
- "Related Definitions" below. The caller uses these attributes to combine
- multiple resource requests.
-
- For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI
- bus enumerator needs to include requests for the prefetchable memory in the
- nonprefetchable memory pool and not request any prefetchable memory.
-
- Attribute Description
- ------------------------------------ ---------------------------------------
- EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root
- bridge does not support separate
- windows for nonprefetchable and
- prefetchable memory. A PCI bus driver
- needs to include requests for
- prefetchable memory in the
- nonprefetchable memory pool.
-
- EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root
- bridge supports 64-bit memory windows.
- If this bit is not set, the PCI bus
- driver needs to include requests for a
- 64-bit memory address in the
- corresponding 32-bit memory pool.
-
- @param[in] This The instance pointer of
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
-
- @param[in] RootBridgeHandle The device handle of the PCI root bridge in
- which the caller is interested. Type
- EFI_HANDLE is defined in
- InstallProtocolInterface() in the UEFI 2.0
- Specification.
-
- @param[out] Attributes The pointer to attribte of root bridge, it is
- output parameter
-
- @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
-
- @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
-
- @retval EFI_SUCCESS Success to get attribute of interested root
- bridge.
-**/
-EFI_STATUS
-EFIAPI
-GetAttributes(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT UINT64 *Attributes
- )
-{
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
-
- if (Attributes == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- *Attributes = RootBridgeInstance->RootBridgeAttrib;
- return EFI_SUCCESS;
- }
- List = List->ForwardLink;
- }
-
- //
- // RootBridgeHandle is not an EFI_HANDLE
- // that was returned on a previous call to GetNextRootBridge()
- //
- return EFI_INVALID_PARAMETER;
-}
-
-/**
- Sets up the specified PCI root bridge for the bus enumeration process.
-
- This member function sets up the root bridge for bus enumeration and returns
- the PCI bus range over which the search should be performed in ACPI 2.0
- resource descriptor format.
-
- @param[in] This The
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- instance.
-
- @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
-
- @param[out] Configuration Pointer to the pointer to the PCI bus resource
- descriptor.
-
- @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
-
- @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
-
- @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
-**/
-EFI_STATUS
-EFIAPI
-StartBusEnumeration(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
- )
-{
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- VOID *Buffer;
- UINT8 *Temp;
- UINT64 BusStart;
- UINT64 BusEnd;
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- //
- // Set up the Root Bridge for Bus Enumeration
- //
- BusStart = RootBridgeInstance->BusBase;
- BusEnd = RootBridgeInstance->BusLimit;
- //
- // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
- //
-
- Buffer = AllocatePool (
- sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +
- sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)
- );
- if (Buffer == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- Temp = (UINT8 *)Buffer;
-
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen =
- BusEnd - BusStart + 1;
-
- Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
-
- *Configuration = Buffer;
- return EFI_SUCCESS;
- }
- List = List->ForwardLink;
- }
-
- return EFI_INVALID_PARAMETER;
-}
-
-/**
- Programs the PCI root bridge hardware so that it decodes the specified PCI
- bus range.
-
- This member function programs the specified PCI root bridge to decode the bus
- range that is specified by the input parameter Configuration.
- The bus range information is specified in terms of the ACPI 2.0 resource
- descriptor format.
-
- @param[in] This The
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- instance
-
- @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be
- programmed
-
- @param[in] Configuration The pointer to the PCI bus resource descriptor
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge
- handle.
-
- @retval EFI_INVALID_PARAMETER Configuration is NULL.
-
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI
- 2.0 resource descriptor.
-
- @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI
- 2.0 bus resource descriptor.
-
- @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource
- descriptors other than bus descriptors.
-
- @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid
- ACPI resource descriptors.
-
- @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this
- root bridge.
-
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this
- root bridge.
-
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
-
- @retval EFI_SUCCESS The bus range for the PCI root bridge was
- programmed.
-**/
-EFI_STATUS
-EFIAPI
-SetBusNumbers(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
- )
-{
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- UINT8 *Ptr;
- UINTN BusStart;
- UINTN BusEnd;
- UINTN BusLen;
-
- if (Configuration == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- Ptr = Configuration;
-
- //
- // Check the Configuration is valid
- //
- if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {
- return EFI_INVALID_PARAMETER;
- }
-
- Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
- if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {
- return EFI_INVALID_PARAMETER;
- }
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- Ptr = Configuration;
-
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
-
- Desc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr;
- BusStart = (UINTN)Desc->AddrRangeMin;
- BusLen = (UINTN)Desc->AddrLen;
- BusEnd = BusStart + BusLen - 1;
-
- if (BusStart > BusEnd) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((BusStart < RootBridgeInstance->BusBase) ||
- (BusEnd > RootBridgeInstance->BusLimit)) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Update the Bus Range
- //
- RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;
- RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;
- RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;
-
- //
- // Program the Root Bridge Hardware
- //
-
- return EFI_SUCCESS;
- }
-
- List = List->ForwardLink;
- }
-
- return EFI_INVALID_PARAMETER;
-}
-
-
-/**
- Submits the I/O and memory resource requirements for the specified PCI root
- bridge.
-
- This function is used to submit all the I/O and memory resources that are
- required by the specified PCI root bridge. The input parameter Configuration
- is used to specify the following:
- - The various types of resources that are required
- - The associated lengths in terms of ACPI 2.0 resource descriptor format
-
- @param[in] This Pointer to the
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- instance.
-
- @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory
- resource requirements are being submitted.
-
- @param[in] Configuration The pointer to the PCI I/O and PCI memory
- resource descriptor.
-
- @retval EFI_SUCCESS The I/O and memory resource requests for a PCI
- root bridge were accepted.
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge
- handle.
-
- @retval EFI_INVALID_PARAMETER Configuration is NULL.
-
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI
- 2.0 resource descriptor.
-
- @retval EFI_INVALID_PARAMETER Configuration includes requests for one or
- more resource types that are not supported by
- this PCI root bridge. This error will happen
- if the caller did not combine resources
- according to Attributes that were returned by
- GetAllocAttributes().
-
- @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
-
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for
- this PCI root bridge.
-**/
-EFI_STATUS
-EFIAPI
-SubmitResources(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
- )
-{
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- UINT8 *Temp;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
- UINT64 AddrLen;
- UINT64 Alignment;
-
- //
- // Check the input parameter: Configuration
- //
- if (Configuration == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- Temp = (UINT8 *)Configuration;
- while ( *Temp == 0x8A) {
- Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
- }
- if (*Temp != 0x79) {
- return EFI_INVALID_PARAMETER;
- }
-
- Temp = (UINT8 *)Configuration;
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- while ( *Temp == 0x8A) {
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
-
- //
- // Check Address Length
- //
- if (Ptr->AddrLen > 0xffffffff) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Check address range alignment
- //
- if (Ptr->AddrRangeMax >= 0xffffffff ||
- Ptr->AddrRangeMax != (GetPowerOfTwo64 (
- Ptr->AddrRangeMax + 1) - 1)) {
- return EFI_INVALID_PARAMETER;
- }
-
- switch (Ptr->ResType) {
-
- case 0:
-
- //
- // Check invalid Address Sapce Granularity
- //
- if (Ptr->AddrSpaceGranularity != 32) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // check the memory resource request is supported by PCI root bridge
- //
- if (RootBridgeInstance->RootBridgeAttrib ==
- EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&
- Ptr->SpecificFlag == 0x06) {
- return EFI_INVALID_PARAMETER;
- }
-
- AddrLen = Ptr->AddrLen;
- Alignment = Ptr->AddrRangeMax;
- if (Ptr->AddrSpaceGranularity == 32) {
- if (Ptr->SpecificFlag == 0x06) {
- //
- // Apply from GCD
- //
- RootBridgeInstance->ResAllocNode[TypePMem32].Status =
- ResSubmitted;
- } else {
- RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;
- RootBridgeInstance->ResAllocNode[TypeMem32].Alignment =
- Alignment;
- RootBridgeInstance->ResAllocNode[TypeMem32].Status =
- ResRequested;
- HostBridgeInstance->ResourceSubmited = TRUE;
- }
- }
-
- if (Ptr->AddrSpaceGranularity == 64) {
- if (Ptr->SpecificFlag == 0x06) {
- RootBridgeInstance->ResAllocNode[TypePMem64].Status =
- ResSubmitted;
- } else {
- RootBridgeInstance->ResAllocNode[TypeMem64].Status =
- ResSubmitted;
- }
- }
- break;
-
- case 1:
- AddrLen = (UINTN) Ptr->AddrLen;
- Alignment = (UINTN) Ptr->AddrRangeMax;
- RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;
- RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;
- RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;
- HostBridgeInstance->ResourceSubmited = TRUE;
- break;
-
- default:
- break;
- };
-
- Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
- }
-
- return EFI_SUCCESS;
- }
-
- List = List->ForwardLink;
- }
-
- return EFI_INVALID_PARAMETER;
-}
-
-/**
- Returns the proposed resource settings for the specified PCI root bridge.
-
- This member function returns the proposed resource settings for the
- specified PCI root bridge. The proposed resource settings are prepared when
- NotifyPhase() is called with a Phase of EfiPciHostBridgeAllocateResources.
- The output parameter Configuration specifies the following:
- - The various types of resources, excluding bus resources, that are
- allocated
- - The associated lengths in terms of ACPI 2.0 resource descriptor format
-
- @param[in] This Pointer to the
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- instance.
-
- @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is
- defined in InstallProtocolInterface() in the
- UEFI 2.0 Specification.
-
- @param[out] Configuration The pointer to the pointer to the PCI I/O and
- memory resource descriptor.
-
- @retval EFI_SUCCESS The requested parameters were returned.
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge
- handle.
-
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-GetProposedResources(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
- )
-{
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- UINTN Index;
- UINTN Number;
- VOID *Buffer;
- UINT8 *Temp;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
- UINT64 ResStatus;
-
- Buffer = NULL;
- Number = 0;
- //
- // Get the Host Bridge Instance from the resource allocation protocol
- //
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- //
- // Enumerate the root bridges in this host bridge
- //
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- for (Index = 0; Index < TypeBus; Index ++) {
- if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
- Number ++;
- }
- }
-
- if (Number == 0) {
- return EFI_INVALID_PARAMETER;
- }
-
- Buffer = AllocateZeroPool (
- Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +
- sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)
- );
- if (Buffer == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- Temp = Buffer;
- for (Index = 0; Index < TypeBus; Index ++) {
- if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
- ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
-
- switch (Index) {
-
- case TypeIo:
- //
- // Io
- //
- Ptr->Desc = 0x8A;
- Ptr->Len = 0x2B;
- Ptr->ResType = 1;
- Ptr->GenFlag = 0;
- Ptr->SpecificFlag = 0;
- Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
- Ptr->AddrRangeMax = 0;
- Ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ?
- EFI_RESOURCE_SATISFIED :
- EFI_RESOURCE_LESS;
- Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
- break;
-
- case TypeMem32:
- //
- // Memory 32
- //
- Ptr->Desc = 0x8A;
- Ptr->Len = 0x2B;
- Ptr->ResType = 0;
- Ptr->GenFlag = 0;
- Ptr->SpecificFlag = 0;
- Ptr->AddrSpaceGranularity = 32;
- Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
- Ptr->AddrRangeMax = 0;
- Ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ?
- EFI_RESOURCE_SATISFIED :
- EFI_RESOURCE_LESS;
- Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
- break;
-
- case TypePMem32:
- //
- // Prefetch memory 32
- //
- Ptr->Desc = 0x8A;
- Ptr->Len = 0x2B;
- Ptr->ResType = 0;
- Ptr->GenFlag = 0;
- Ptr->SpecificFlag = 6;
- Ptr->AddrSpaceGranularity = 32;
- Ptr->AddrRangeMin = 0;
- Ptr->AddrRangeMax = 0;
- Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
- Ptr->AddrLen = 0;
- break;
-
- case TypeMem64:
- //
- // Memory 64
- //
- Ptr->Desc = 0x8A;
- Ptr->Len = 0x2B;
- Ptr->ResType = 0;
- Ptr->GenFlag = 0;
- Ptr->SpecificFlag = 0;
- Ptr->AddrSpaceGranularity = 64;
- Ptr->AddrRangeMin = 0;
- Ptr->AddrRangeMax = 0;
- Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
- Ptr->AddrLen = 0;
- break;
-
- case TypePMem64:
- //
- // Prefetch memory 64
- //
- Ptr->Desc = 0x8A;
- Ptr->Len = 0x2B;
- Ptr->ResType = 0;
- Ptr->GenFlag = 0;
- Ptr->SpecificFlag = 6;
- Ptr->AddrSpaceGranularity = 64;
- Ptr->AddrRangeMin = 0;
- Ptr->AddrRangeMax = 0;
- Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
- Ptr->AddrLen = 0;
- break;
- };
-
- Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
- }
- }
-
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
-
- *Configuration = Buffer;
-
- return EFI_SUCCESS;
- }
-
- List = List->ForwardLink;
- }
-
- return EFI_INVALID_PARAMETER;
-}
-
-/**
- Provides the hooks from the PCI bus driver to every PCI controller
- (device/function) at various stages of the PCI enumeration process that allow
- the host bridge driver to preinitialize individual PCI controllers before
- enumeration.
-
- This function is called during the PCI enumeration process. No specific
- action is expected from this member function. It allows the host bridge
- driver to preinitialize individual PCI controllers before enumeration.
-
- @param This Pointer to the
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- instance.
-
- @param RootBridgeHandle The associated PCI root bridge handle. Type
- EFI_HANDLE is defined in InstallProtocolInterface()
- in the UEFI 2.0 Specification.
-
- @param PciAddress The address of the PCI device on the PCI bus. This
- address can be passed to the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to
- access the PCI configuration space of the device.
- See Table 12-1 in the UEFI 2.0 Specification for the
- definition of
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
-
- @param Phase The phase of the PCI device enumeration.
-
- @retval EFI_SUCCESS The requested parameters were returned.
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge
- handle.
-
- @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined
- in
- EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
-
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
- The PCI enumerator should not enumerate this
- device, including its child devices if it is
- a PCI-to-PCI bridge.
-**/
-EFI_STATUS
-EFIAPI
-PreprocessController (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
- )
-{
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- LIST_ENTRY *List;
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- //
- // Enumerate the root bridges in this host bridge
- //
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- break;
- }
- List = List->ForwardLink;
- }
- if (List == &HostBridgeInstance->Head) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
- return EFI_INVALID_PARAMETER;
- }
-
- return EFI_SUCCESS;
-}
diff --git a/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridge.h b/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridge.h
deleted file mode 100644
index 617c68e..0000000
--- a/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridge.h
+++ /dev/null
@@ -1,651 +0,0 @@
-/** @file
- The Header file of the Pci Host Bridge Driver
-
- Copyright (C) 2015, Red Hat, Inc.
- Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available
- under the terms and conditions of the BSD License which accompanies this
- distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#ifndef _PCI_HOST_BRIDGE_H_
-#define _PCI_HOST_BRIDGE_H_
-
-#include <PiDxe.h>
-
-#include <IndustryStandard/Pci.h>
-#include <IndustryStandard/Acpi.h>
-
-#include <Protocol/PciHostBridgeResourceAllocation.h>
-#include <Protocol/PciRootBridgeIo.h>
-#include <Protocol/Metronome.h>
-#include <Protocol/DevicePath.h>
-
-
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/DxeServicesTableLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/IoLib.h>
-#include <Library/PciLib.h>
-
-#define MAX_PCI_DEVICE_NUMBER 31
-#define MAX_PCI_FUNCTION_NUMBER 7
-#define MAX_PCI_REG_ADDRESS 0xFF
-
-typedef enum {
- IoOperation,
- MemOperation,
- PciOperation
-} OPERATION_TYPE;
-
-#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')
-typedef struct {
- UINTN Signature;
- EFI_HANDLE HostBridgeHandle;
- LIST_ENTRY Head;
- BOOLEAN ResourceSubmited;
- BOOLEAN CanRestarted;
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
-} PCI_HOST_BRIDGE_INSTANCE;
-
-#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \
- CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
-
-//
-// HostBridge Resource Allocation interface
-//
-
-/**
- These are the notifications from the PCI bus driver that it is about to enter
- a certain phase of the PCI enumeration process.
-
- This member function can be used to notify the host bridge driver to perform
- specific actions, including any chipset-specific initialization, so that the
- chipset is ready to enter the next phase. Eight notification points are
- defined at this time. See belows:
-
- EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures
- and internal data structures. The PCI
- enumerator should issue this
- notification before starting a fresh
- enumeration process. Enumeration
- cannot be restarted after sending any
- other notification such as
- EfiPciHostBridgeBeginBusAllocation.
-
- EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to
- begin. No specific action is required
- here. This notification can be used to
- perform any chipset-specific
- programming.
-
- EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming
- phase is complete. No specific action
- is required here. This notification
- can be used to perform any
- chipset-specific programming.
-
- EfiPciHostBridgeBeginResourceAllocation
- The resource allocation phase is about
- to begin. No specific action is
- required here. This notification can
- be used to perform any
- chipset-specific programming.
-
- EfiPciHostBridgeAllocateResources Allocates resources per previously
- submitted requests for all the PCI
- root bridges. These resource settings
- are returned on the next call to
- GetProposedResources(). Before calling
- NotifyPhase() with a Phase of
- EfiPciHostBridgeAllocateResource, the
- PCI bus enumerator is responsible for
- gathering I/O and memory requests for
- all the PCI root bridges and
- submitting these requests using
- SubmitResources(). This function pads
- the resource amount to suit the root
- bridge hardware, takes care of
- dependencies between the PCI root
- bridges, and calls the Global
- Coherency Domain (GCD) with the
- allocation request. In the case of
- padding, the allocated range could be
- bigger than what was requested.
-
- EfiPciHostBridgeSetResources Programs the host bridge hardware to
- decode previously allocated resources
- (proposed resources) for all the PCI
- root bridges. After the hardware is
- programmed, reassigning resources will
- not be supported. The bus settings are
- not affected.
-
- EfiPciHostBridgeFreeResources Deallocates resources that were
- previously allocated for all the PCI
- root bridges and resets the I/O and
- memory apertures to their initial
- state. The bus settings are not
- affected. If the request to allocate
- resources fails, the PCI enumerator
- can use this notification to
- deallocate previous resources, adjust
- the requests, and retry allocation.
-
- EfiPciHostBridgeEndResourceAllocation The resource allocation phase is
- completed. No specific action is
- required here. This notification can
- be used to perform any chipsetspecific
- programming.
-
- @param[in] This The instance pointer of
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
-
- @param[in] Phase The phase during enumeration
-
- @retval EFI_NOT_READY This phase cannot be entered at this time. For
- example, this error is valid for a Phase of
- EfiPciHostBridgeAllocateResources if
- SubmitResources() has not been called for one
- or more PCI root bridges before this call
-
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
- This error is valid for a Phase of
- EfiPciHostBridgeSetResources.
-
- @retval EFI_INVALID_PARAMETER Invalid phase parameter
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources. This error is valid for a
- Phase of EfiPciHostBridgeAllocateResources if
- the previously submitted resource requests
- cannot be fulfilled or were only partially
- fulfilled.
-
- @retval EFI_SUCCESS The notification was accepted without any
- errors.
-**/
-EFI_STATUS
-EFIAPI
-NotifyPhase(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
- );
-
-/**
- Return the device handle of the next PCI root bridge that is associated with
- this Host Bridge.
-
- This function is called multiple times to retrieve the device handles of all
- the PCI root bridges that are associated with this PCI host bridge. Each PCI
- host bridge is associated with one or more PCI root bridges. On each call,
- the handle that was returned by the previous call is passed into the
- interface, and on output the interface returns the device handle of the next
- PCI root bridge. The caller can use the handle to obtain the instance of the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL for that root bridge. When there are no more
- PCI root bridges to report, the interface returns EFI_NOT_FOUND. A PCI
- enumerator must enumerate the PCI root bridges in the order that they are
- returned by this function.
-
- For D945 implementation, there is only one root bridge in PCI host bridge.
-
- @param[in] This The instance pointer of
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
-
- @param[in, out] RootBridgeHandle Returns the device handle of the next PCI
- root bridge.
-
- @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then
- return the first Rootbridge handle of the
- specific Host bridge and return EFI_SUCCESS.
-
- @retval EFI_NOT_FOUND Can not find the any more root bridge in
- specific host bridge.
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
- returned on a previous call to
- GetNextRootBridge().
-**/
-EFI_STATUS
-EFIAPI
-GetNextRootBridge(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN OUT EFI_HANDLE *RootBridgeHandle
- );
-
-/**
- Returns the allocation attributes of a PCI root bridge.
-
- The function returns the allocation attributes of a specific PCI root bridge.
- The attributes can vary from one PCI root bridge to another. These attributes
- are different from the decode-related attributes that are returned by the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
- RootBridgeHandle parameter is used to specify the instance of the PCI root
- bridge. The device handles of all the root bridges that are associated with
- this host bridge must be obtained by calling GetNextRootBridge(). The
- attributes are static in the sense that they do not change during or after
- the enumeration process. The hardware may provide mechanisms to change the
- attributes on the fly, but such changes must be completed before
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is installed. The permitted
- values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
- "Related Definitions" below. The caller uses these attributes to combine
- multiple resource requests.
-
- For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI
- bus enumerator needs to include requests for the prefetchable memory in the
- nonprefetchable memory pool and not request any prefetchable memory.
-
- Attribute Description
- ------------------------------------ ---------------------------------------
- EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root
- bridge does not support separate
- windows for nonprefetchable and
- prefetchable memory. A PCI bus driver
- needs to include requests for
- prefetchable memory in the
- nonprefetchable memory pool.
-
- EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root
- bridge supports 64-bit memory windows.
- If this bit is not set, the PCI bus
- driver needs to include requests for a
- 64-bit memory address in the
- corresponding 32-bit memory pool.
-
- @param[in] This The instance pointer of
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
-
- @param[in] RootBridgeHandle The device handle of the PCI root bridge in
- which the caller is interested. Type
- EFI_HANDLE is defined in
- InstallProtocolInterface() in the UEFI 2.0
- Specification.
-
- @param[out] Attributes The pointer to attribte of root bridge, it is
- output parameter
-
- @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
-
- @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
-
- @retval EFI_SUCCESS Success to get attribute of interested root
- bridge.
-**/
-EFI_STATUS
-EFIAPI
-GetAttributes(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT UINT64 *Attributes
- );
-
-/**
- Sets up the specified PCI root bridge for the bus enumeration process.
-
- This member function sets up the root bridge for bus enumeration and returns
- the PCI bus range over which the search should be performed in ACPI 2.0
- resource descriptor format.
-
- @param[in] This The
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- instance.
-
- @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
-
- @param[out] Configuration Pointer to the pointer to the PCI bus resource
- descriptor.
-
- @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
-
- @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
-
- @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
-**/
-EFI_STATUS
-EFIAPI
-StartBusEnumeration(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
- );
-
-/**
- Programs the PCI root bridge hardware so that it decodes the specified PCI
- bus range.
-
- This member function programs the specified PCI root bridge to decode the bus
- range that is specified by the input parameter Configuration.
- The bus range information is specified in terms of the ACPI 2.0 resource
- descriptor format.
-
- @param[in] This The
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- instance
-
- @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be
- programmed
-
- @param[in] Configuration The pointer to the PCI bus resource descriptor
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge
- handle.
-
- @retval EFI_INVALID_PARAMETER Configuration is NULL.
-
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI
- 2.0 resource descriptor.
-
- @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI
- 2.0 bus resource descriptor.
-
- @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource
- descriptors other than bus descriptors.
-
- @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid
- ACPI resource descriptors.
-
- @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this
- root bridge.
-
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this
- root bridge.
-
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
-
- @retval EFI_SUCCESS The bus range for the PCI root bridge was
- programmed.
-**/
-EFI_STATUS
-EFIAPI
-SetBusNumbers(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
- );
-
-/**
- Submits the I/O and memory resource requirements for the specified PCI root
- bridge.
-
- This function is used to submit all the I/O and memory resources that are
- required by the specified PCI root bridge. The input parameter Configuration
- is used to specify the following:
- - The various types of resources that are required
- - The associated lengths in terms of ACPI 2.0 resource descriptor format
-
- @param[in] This Pointer to the
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- instance.
-
- @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory
- resource requirements are being submitted.
-
- @param[in] Configuration The pointer to the PCI I/O and PCI memory
- resource descriptor.
-
- @retval EFI_SUCCESS The I/O and memory resource requests for a PCI
- root bridge were accepted.
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge
- handle.
-
- @retval EFI_INVALID_PARAMETER Configuration is NULL.
-
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI
- 2.0 resource descriptor.
-
- @retval EFI_INVALID_PARAMETER Configuration includes requests for one or
- more resource types that are not supported by
- this PCI root bridge. This error will happen
- if the caller did not combine resources
- according to Attributes that were returned by
- GetAllocAttributes().
-
- @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
-
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for
- this PCI root bridge.
-**/
-EFI_STATUS
-EFIAPI
-SubmitResources(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
- );
-
-/**
- Returns the proposed resource settings for the specified PCI root bridge.
-
- This member function returns the proposed resource settings for the
- specified PCI root bridge. The proposed resource settings are prepared when
- NotifyPhase() is called with a Phase of EfiPciHostBridgeAllocateResources.
- The output parameter Configuration specifies the following:
- - The various types of resources, excluding bus resources, that are
- allocated
- - The associated lengths in terms of ACPI 2.0 resource descriptor format
-
- @param[in] This Pointer to the
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- instance.
-
- @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is
- defined in InstallProtocolInterface() in the
- UEFI 2.0 Specification.
-
- @param[out] Configuration The pointer to the pointer to the PCI I/O and
- memory resource descriptor.
-
- @retval EFI_SUCCESS The requested parameters were returned.
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge
- handle.
-
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-GetProposedResources(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
- );
-
-/**
- Provides the hooks from the PCI bus driver to every PCI controller
- (device/function) at various stages of the PCI enumeration process that allow
- the host bridge driver to preinitialize individual PCI controllers before
- enumeration.
-
- This function is called during the PCI enumeration process. No specific
- action is expected from this member function. It allows the host bridge
- driver to preinitialize individual PCI controllers before enumeration.
-
- @param This Pointer to the
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- instance.
-
- @param RootBridgeHandle The associated PCI root bridge handle. Type
- EFI_HANDLE is defined in InstallProtocolInterface()
- in the UEFI 2.0 Specification.
-
- @param PciAddress The address of the PCI device on the PCI bus. This
- address can be passed to the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to
- access the PCI configuration space of the device.
- See Table 12-1 in the UEFI 2.0 Specification for the
- definition of
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
-
- @param Phase The phase of the PCI device enumeration.
-
- @retval EFI_SUCCESS The requested parameters were returned.
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge
- handle.
-
- @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined
- in
- EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
-
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
- The PCI enumerator should not enumerate this
- device, including its child devices if it is
- a PCI-to-PCI bridge.
-**/
-EFI_STATUS
-EFIAPI
-PreprocessController (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
- );
-
-
-//
-// Define resource status constant
-//
-#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
-#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
-
-
-//
-// Driver Instance Data Prototypes
-//
-
-typedef struct {
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
- UINTN NumberOfBytes;
- UINTN NumberOfPages;
- EFI_PHYSICAL_ADDRESS HostAddress;
- EFI_PHYSICAL_ADDRESS MappedHostAddress;
-} MAP_INFO;
-
-typedef struct {
- ACPI_HID_DEVICE_PATH AcpiDevicePath;
- EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
-} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
-
-typedef struct {
- UINT64 BusBase;
- UINT64 BusLimit;
-
- UINT64 MemBase;
- UINT64 MemLimit;
-
- UINT64 IoBase;
- UINT64 IoLimit;
-} PCI_ROOT_BRIDGE_RESOURCE_APERTURE;
-
-typedef enum {
- TypeIo = 0,
- TypeMem32,
- TypePMem32,
- TypeMem64,
- TypePMem64,
- TypeBus,
- TypeMax
-} PCI_RESOURCE_TYPE;
-
-typedef enum {
- ResNone = 0,
- ResSubmitted,
- ResRequested,
- ResAllocated,
- ResStatusMax
-} RES_STATUS;
-
-typedef struct {
- PCI_RESOURCE_TYPE Type;
- UINT64 Base;
- UINT64 Length;
- UINT64 Alignment;
- RES_STATUS Status;
-} PCI_RES_NODE;
-
-#pragma pack(1)
-typedef struct {
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesc[TypeMax];
- EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;
-} RESOURCE_CONFIGURATION;
-#pragma pack()
-
-#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')
-
-typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
- EFI_HANDLE Handle;
- UINT64 RootBridgeAttrib;
- UINT64 Attributes;
- UINT64 Supports;
-
- //
- // Specific for this memory controller: Bus, I/O, Mem
- //
- PCI_RES_NODE ResAllocNode[6];
-
- //
- // Addressing for Memory and I/O and Bus arrange
- //
- UINT64 BusBase;
- UINT64 MemBase;
- UINT64 IoBase;
- UINT64 BusLimit;
- UINT64 MemLimit;
- UINT64 IoLimit;
-
- EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
-
- RESOURCE_CONFIGURATION ConfigBuffer;
-} PCI_ROOT_BRIDGE_INSTANCE;
-
-
-//
-// Driver Instance Data Macros
-//
-#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \
- CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
-
-
-#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \
- CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
-
-/**
-
- Construct the Pci Root Bridge Io protocol
-
- @param Protocol Point to protocol instance
- @param HostBridgeHandle Handle of host bridge
- @param Attri Attribute of host bridge
- @param ResAperture ResourceAperture for host bridge
-
- @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
-**/
-EFI_STATUS
-RootBridgeConstructor (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
- IN EFI_HANDLE HostBridgeHandle,
- IN UINT64 Attri,
- IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture
- );
-
-#endif
diff --git a/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridgeDxe.inf b/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridgeDxe.inf
deleted file mode 100644
index 72d18e5..0000000
--- a/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciHostBridgeDxe.inf
+++ /dev/null
@@ -1,65 +0,0 @@
-## @file
-# The basic interfaces implementation to a single segment PCI Host Bridge
-# driver.
-#
-# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials are licensed and made available
-# under the terms and conditions of the BSD License which accompanies this
-# distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-# IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PciHostBridge
- FILE_GUID = 25409195-B74D-419A-9641-A86D1CB32D62
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = InitializePciHostBridge
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Packages]
- MdePkg/MdePkg.dec
- OvmfPkg/OvmfPkg.dec
- RiscVVirtPkg/RiscVVirtPkg.dec
-
-[LibraryClasses]
- UefiDriverEntryPoint
- UefiBootServicesTableLib
- DxeServicesTableLib
- UefiLib
- MemoryAllocationLib
- BaseMemoryLib
- BaseLib
- DebugLib
- DevicePathLib
- IoLib
- PciLib
- QemuFwCfgLib
-
-[Sources]
- PciHostBridge.c
- PciRootBridgeIo.c
- PciHostBridge.h
- IoFifo.h
-
-[Protocols]
- gEfiPciHostBridgeResourceAllocationProtocolGuid ## PRODUCES
- gEfiPciRootBridgeIoProtocolGuid ## PRODUCES
- gEfiMetronomeArchProtocolGuid ## CONSUMES
- gEfiDevicePathProtocolGuid ## PRODUCES
-
-[depex]
- gEfiMetronomeArchProtocolGuid
diff --git a/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciRootBridgeIo.c b/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciRootBridgeIo.c
deleted file mode 100644
index c61fd1d..0000000
--- a/RiscVVirtPkg/Universal/PciHostBridgeDxe/PciRootBridgeIo.c
+++ /dev/null
@@ -1,2628 +0,0 @@
-/** @file
- PCI Root Bridge Io Protocol implementation
-
- Copyright (C) 2015, Red Hat, Inc.
- Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available
- under the terms and conditions of the BSD License which accompanies this
- distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
- WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#include "PciHostBridge.h"
-#include "IoFifo.h"
-
-STATIC
-CONST
-RESOURCE_CONFIGURATION mConfigurationTemplate = {
- {
- { 0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0 }, // SpaceDesc[TypeIo]
- { 0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0 }, // SpaceDesc[TypeMem32]
- { 0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0 }, // SpaceDesc[TypePMem32]
- { 0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0 }, // SpaceDesc[TypeMem64]
- { 0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0 }, // SpaceDesc[TypePMem64]
- { 0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0 } // SpaceDesc[TypeBus]
- },
- { 0x79, 0 } // EndDesc
-};
-
-//
-// Protocol Member Function Prototypes
-//
-
-/**
- Polls an address in memory mapped I/O space until an exit condition is met,
- or a timeout occurs.
-
- This function provides a standard way to poll a PCI memory location. A PCI
- memory read operation is performed at the PCI memory address specified by
- Address for the width specified by Width. The result of this PCI memory read
- operation is stored in Result. This PCI memory read operation is repeated
- until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
- is equal to Value.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] Address The base address of the memory operations. The caller
- is responsible for aligning Address if required.
-
- @param[in] Mask Mask used for the polling criteria. Bytes above Width
- in Mask are ignored. The bits in the bytes below Width
- which are zero in Mask are ignored when polling the
- memory address.
-
- @param[in] Value The comparison value used for the polling exit
- criteria.
-
- @param[in] Delay The number of 100 ns units to poll. Note that timer
- available may be of poorer granularity.
-
- @param[out] Result Pointer to the last value read from the memory
- location.
-
- @retval EFI_SUCCESS The last data returned from the access matched
- the poll exit criteria.
-
- @retval EFI_INVALID_PARAMETER Width is invalid.
-
- @retval EFI_INVALID_PARAMETER Result is NULL.
-
- @retval EFI_TIMEOUT Delay expired before a match occurred.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPollMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINT64 Mask,
- IN UINT64 Value,
- IN UINT64 Delay,
- OUT UINT64 *Result
- );
-
-/**
- Reads from the I/O space of a PCI Root Bridge. Returns when either the
- polling exit criteria is satisfied or after a defined duration.
-
- This function provides a standard way to poll a PCI I/O location. A PCI I/O
- read operation is performed at the PCI I/O address specified by Address for
- the width specified by Width. The result of this PCI I/O read operation is
- stored in Result. This PCI I/O read operation is repeated until either a
- timeout of Delay 100 ns units has expired, or (Result & Mask) is equal to
- Value.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the I/O operations.
-
- @param[in] Address The base address of the I/O operations. The caller is
- responsible for aligning Address if required.
-
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in
- Mask are ignored. The bits in the bytes below Width
- which are zero in Mask are ignored when polling the I/O
- address.
-
- @param[in] Value The comparison value used for the polling exit criteria.
-
-
- @param[in] Delay The number of 100 ns units to poll. Note that timer
- available may be of poorer granularity.
-
- @param[out] Result Pointer to the last value read from the memory location.
-
- @retval EFI_SUCCESS The last data returned from the access matched
- the poll exit criteria.
-
- @retval EFI_INVALID_PARAMETER Width is invalid.
-
- @retval EFI_INVALID_PARAMETER Result is NULL.
-
- @retval EFI_TIMEOUT Delay expired before a match occurred.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPollIo (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINT64 Mask,
- IN UINT64 Value,
- IN UINT64 Delay,
- OUT UINT64 *Result
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root
- bridge memory space.
-
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
- controller registers in the PCI root bridge memory space.
- The memory operations are carried out exactly as requested. The caller is
- responsible for satisfying any alignment and memory width restrictions that a
- PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operation.
-
- @param[in] Address The base address of the memory operation. The caller
- is responsible for aligning the Address if required.
-
- @param[in] Count The number of memory operations to perform. Bytes
- moved is Width size * Count, starting at Address.
-
- @param[out] Buffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMemRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root
- bridge memory space.
-
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
- controller registers in the PCI root bridge memory space.
- The memory operations are carried out exactly as requested. The caller is
- responsible for satisfying any alignment and memory width restrictions that a
- PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operation.
-
- @param[in] Address The base address of the memory operation. The caller
- is responsible for aligning the Address if required.
-
- @param[in] Count The number of memory operations to perform. Bytes
- moved is Width size * Count, starting at Address.
-
- @param[in] Buffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMemWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root
- bridge I/O space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] UserAddress The base address of the I/O operation. The caller is
- responsible for aligning the Address if required.
-
- @param[in] Count The number of I/O operations to perform. Bytes moved
- is Width size * Count, starting at Address.
-
- @param[out] UserBuffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoIoRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 UserAddress,
- IN UINTN Count,
- OUT VOID *UserBuffer
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root
- bridge I/O space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] UserAddress The base address of the I/O operation. The caller is
- responsible for aligning the Address if required.
-
- @param[in] Count The number of I/O operations to perform. Bytes moved
- is Width size * Count, starting at Address.
-
- @param[in] UserBuffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoIoWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 UserAddress,
- IN UINTN Count,
- IN VOID *UserBuffer
- );
-
-/**
- Enables a PCI driver to copy one region of PCI root bridge memory space to
- another region of PCI root bridge memory space.
-
- The CopyMem() function enables a PCI driver to copy one region of PCI root
- bridge memory space to another region of PCI root bridge memory space. This
- is especially useful for video scroll operation on a memory mapped video
- buffer.
- The memory operations are carried out exactly as requested. The caller is
- responsible for satisfying any alignment and memory width restrictions that a
- PCI root bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
- instance.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] DestAddress The destination address of the memory operation. The
- caller is responsible for aligning the DestAddress if
- required.
-
- @param[in] SrcAddress The source address of the memory operation. The caller
- is responsible for aligning the SrcAddress if
- required.
-
- @param[in] Count The number of memory operations to perform. Bytes
- moved is Width size * Count, starting at DestAddress
- and SrcAddress.
-
-
- @retval EFI_SUCCESS The data was copied from one memory region
- to another memory region.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoCopyMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 DestAddress,
- IN UINT64 SrcAddress,
- IN UINTN Count
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in a PCI root
- bridge's configuration space.
-
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI
- configuration registers for a PCI controller.
- The PCI Configuration operations are carried out exactly as requested. The
- caller is responsible for any alignment and PCI configuration width issues
- that a PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] Address The address within the PCI configuration space for the
- PCI controller.
-
- @param[in] Count The number of PCI configuration operations to perform.
- Bytes moved is Width size * Count, starting at
- Address.
-
- @param[out] Buffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPciRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in a PCI root
- bridge's configuration space.
-
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI
- configuration registers for a PCI controller.
- The PCI Configuration operations are carried out exactly as requested. The
- caller is responsible for any alignment and PCI configuration width issues
- that a PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] Address The address within the PCI configuration space for the
- PCI controller.
-
- @param[in] Count The number of PCI configuration operations to perform.
- Bytes moved is Width size * Count, starting at
- Address.
-
- @param[in] Buffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPciWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- );
-
-/**
- Provides the PCI controller-specific addresses required to access system
- memory from a DMA bus master.
-
- The Map() function provides the PCI controller specific addresses needed to
- access system memory. This function is used to map system memory for PCI bus
- master DMA accesses.
-
- @param[in] This A pointer to the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Operation Indicates if the bus master is going to read
- or write to system memory.
-
- @param[in] HostAddress The system memory address to map to the PCI
- controller.
-
- @param[in, out] NumberOfBytes On input the number of bytes to map. On
- output the number of bytes that were mapped.
-
- @param[out] DeviceAddress The resulting map address for the bus master
- PCI controller to use to access the system
- memory's HostAddress.
-
- @param[out] Mapping The value to pass to Unmap() when the bus
- master DMA operation is complete.
-
- @retval EFI_SUCCESS The range was mapped for the returned
- NumberOfBytes.
-
- @retval EFI_INVALID_PARAMETER Operation is invalid.
-
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.
-
- @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
-
- @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
-
- @retval EFI_INVALID_PARAMETER Mapping is NULL.
-
- @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common
- buffer.
-
- @retval EFI_DEVICE_ERROR The system hardware could not map the
- requested address.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMap (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
- IN VOID *HostAddress,
- IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
- );
-
-/**
- Completes the Map() operation and releases any corresponding resources.
-
- The Unmap() function completes the Map() operation and releases any
- corresponding resources.
- If the operation was an EfiPciOperationBusMasterWrite or
- EfiPciOperationBusMasterWrite64, the data is committed to the target system
- memory.
- Any resources used for the mapping are freed.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Mapping The mapping value returned from Map().
-
- @retval EFI_SUCCESS The range was unmapped.
-
- @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by
- Map().
-
- @retval EFI_DEVICE_ERROR The data was not committed to the target
- system memory.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoUnmap (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN VOID *Mapping
- );
-
-/**
- Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
- or EfiPciOperationBusMasterCommonBuffer64 mapping.
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param Type This parameter is not used and must be ignored.
-
- @param MemoryType The type of memory to allocate, EfiBootServicesData or
- EfiRuntimeServicesData.
-
- @param Pages The number of pages to allocate.
-
- @param HostAddress A pointer to store the base system memory address of the
- allocated range.
-
- @param Attributes The requested bit mask of attributes for the allocated
- range. Only the attributes
- EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
- EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
- EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
- function.
-
- @retval EFI_SUCCESS The requested memory pages were allocated.
-
- @retval EFI_INVALID_PARAMETER MemoryType is invalid.
-
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.
-
- @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal
- attribute bits are MEMORY_WRITE_COMBINE,
- MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
-
- @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoAllocateBuffer (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_ALLOCATE_TYPE Type,
- IN EFI_MEMORY_TYPE MemoryType,
- IN UINTN Pages,
- OUT VOID **HostAddress,
- IN UINT64 Attributes
- );
-
-/**
- Frees memory that was allocated with AllocateBuffer().
-
- The FreeBuffer() function frees memory that was allocated with
- AllocateBuffer().
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param Pages The number of pages to free.
-
- @param HostAddress The base system memory address of the allocated range.
-
- @retval EFI_SUCCESS The requested memory pages were freed.
-
- @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and
- Pages was not allocated with AllocateBuffer().
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoFreeBuffer (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN UINTN Pages,
- OUT VOID *HostAddress
- );
-
-/**
- Flushes all PCI posted write transactions from a PCI host bridge to system
- memory.
-
- The Flush() function flushes any PCI posted write transactions from a PCI
- host bridge to system memory. Posted write transactions are generated by PCI
- bus masters when they perform write transactions to target addresses in
- system memory.
- This function does not flush posted write transactions from any PCI bridges.
- A PCI controller specific action must be taken to guarantee that the posted
- write transactions have been flushed from the PCI controller and from all the
- PCI bridges into the PCI host bridge. This is typically done with a PCI read
- transaction from the PCI controller prior to calling Flush().
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @retval EFI_SUCCESS The PCI posted write transactions were flushed
- from the PCI host bridge to system memory.
-
- @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed
- from the PCI host bridge due to a hardware error.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoFlush (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
- );
-
-/**
- Gets the attributes that a PCI root bridge supports setting with
- SetAttributes(), and the attributes that a PCI root bridge is currently
- using.
-
- The GetAttributes() function returns the mask of attributes that this PCI
- root bridge supports and the mask of attributes that the PCI root bridge is
- currently using.
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param Supported A pointer to the mask of attributes that this PCI root
- bridge supports setting with SetAttributes().
-
- @param Attributes A pointer to the mask of attributes that this PCI root
- bridge is currently using.
-
-
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes
- that the PCI root bridge supports is returned
- in Supports. If Attributes is not NULL, then
- the attributes that the PCI root bridge is
- currently using is returned in Attributes.
-
- @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoGetAttributes (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- OUT UINT64 *Supported,
- OUT UINT64 *Attributes
- );
-
-/**
- Sets attributes for a resource range on a PCI root bridge.
-
- The SetAttributes() function sets the attributes specified in Attributes for
- the PCI root bridge on the resource range specified by ResourceBase and
- ResourceLength. Since the granularity of setting these attributes may vary
- from resource type to resource type, and from platform to platform, the
- actual resource range and the one passed in by the caller may differ. As a
- result, this function may set the attributes specified by Attributes on a
- larger resource range than the caller requested. The actual range is returned
- in ResourceBase and ResourceLength. The caller is responsible for verifying
- that the actual range for which the attributes were set is acceptable.
-
- @param[in] This A pointer to the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Attributes The mask of attributes to set. If the
- attribute bit MEMORY_WRITE_COMBINE,
- MEMORY_CACHED, or MEMORY_DISABLE is set,
- then the resource range is specified by
- ResourceBase and ResourceLength. If
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
- MEMORY_DISABLE are not set, then
- ResourceBase and ResourceLength are ignored,
- and may be NULL.
-
- @param[in, out] ResourceBase A pointer to the base address of the
- resource range to be modified by the
- attributes specified by Attributes.
-
- @param[in, out] ResourceLength A pointer to the length of the resource
- range to be modified by the attributes
- specified by Attributes.
-
- @retval EFI_SUCCESS The current configuration of this PCI root bridge
- was returned in Resources.
-
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
- could not be retrieved.
-
- @retval EFI_INVALID_PARAMETER Invalid pointer of
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoSetAttributes (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN UINT64 Attributes,
- IN OUT UINT64 *ResourceBase,
- IN OUT UINT64 *ResourceLength
- );
-
-/**
- Retrieves the current resource settings of this PCI root bridge in the form
- of a set of ACPI 2.0 resource descriptors.
-
- There are only two resource descriptor types from the ACPI Specification that
- may be used to describe the current resources allocated to a PCI root bridge.
- These are the QWORD Address Space Descriptor (ACPI 2.0 Section 6.4.3.5.1),
- and the End Tag (ACPI 2.0 Section 6.4.2.8). The QWORD Address Space
- Descriptor can describe memory, I/O, and bus number ranges for dynamic or
- fixed resources. The configuration of a PCI root bridge is described with one
- or more QWORD Address Space Descriptors followed by an End Tag.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that
- describe the current configuration of this PCI root
- bridge. The storage for the ACPI 2.0 resource
- descriptors is allocated by this function. The
- caller must treat the return buffer as read-only
- data, and the buffer must not be freed by the
- caller.
-
- @retval EFI_SUCCESS The current configuration of this PCI root bridge
- was returned in Resources.
-
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
- could not be retrieved.
-
- @retval EFI_INVALID_PARAMETER Invalid pointer of
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoConfiguration (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- OUT VOID **Resources
- );
-
-//
-// Memory Controller Pci Root Bridge Io Module Variables
-//
-EFI_METRONOME_ARCH_PROTOCOL *mMetronome;
-
-//
-// Lookup table for increment values based on transfer widths
-//
-UINT8 mInStride[] = {
- 1, // EfiPciWidthUint8
- 2, // EfiPciWidthUint16
- 4, // EfiPciWidthUint32
- 8, // EfiPciWidthUint64
- 0, // EfiPciWidthFifoUint8
- 0, // EfiPciWidthFifoUint16
- 0, // EfiPciWidthFifoUint32
- 0, // EfiPciWidthFifoUint64
- 1, // EfiPciWidthFillUint8
- 2, // EfiPciWidthFillUint16
- 4, // EfiPciWidthFillUint32
- 8 // EfiPciWidthFillUint64
-};
-
-//
-// Lookup table for increment values based on transfer widths
-//
-UINT8 mOutStride[] = {
- 1, // EfiPciWidthUint8
- 2, // EfiPciWidthUint16
- 4, // EfiPciWidthUint32
- 8, // EfiPciWidthUint64
- 1, // EfiPciWidthFifoUint8
- 2, // EfiPciWidthFifoUint16
- 4, // EfiPciWidthFifoUint32
- 8, // EfiPciWidthFifoUint64
- 0, // EfiPciWidthFillUint8
- 0, // EfiPciWidthFillUint16
- 0, // EfiPciWidthFillUint32
- 0 // EfiPciWidthFillUint64
-};
-
-/**
- Construct the Pci Root Bridge Io protocol
-
- @param Protocol Point to protocol instance
-
- @param HostBridgeHandle Handle of host bridge
-
- @param Attri Attribute of host bridge
-
- @param ResAperture ResourceAperture for host bridge
-
- @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
-**/
-EFI_STATUS
-RootBridgeConstructor (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
- IN EFI_HANDLE HostBridgeHandle,
- IN UINT64 Attri,
- IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture
- )
-{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
- PCI_RESOURCE_TYPE Index;
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);
-
- //
- // The host to pci bridge, the host memory and io addresses are
- // direct mapped to pci addresses, so no need translate, set bases to 0.
- //
- PrivateData->MemBase = ResAperture->MemBase;
- PrivateData->IoBase = ResAperture->IoBase;
-
- //
- // The host bridge only supports 32bit addressing for memory
- // and standard IA32 16bit io
- //
- PrivateData->MemLimit = ResAperture->MemLimit;
- PrivateData->IoLimit = ResAperture->IoLimit;
-
- //
- // Bus Aperture for this Root Bridge (Possible Range)
- //
- PrivateData->BusBase = ResAperture->BusBase;
- PrivateData->BusLimit = ResAperture->BusLimit;
-
- //
- // Specific for this chipset
- //
- for (Index = TypeIo; Index < TypeMax; Index++) {
- PrivateData->ResAllocNode[Index].Type = Index;
- PrivateData->ResAllocNode[Index].Base = 0;
- PrivateData->ResAllocNode[Index].Length = 0;
- PrivateData->ResAllocNode[Index].Status = ResNone;
- }
-
- PrivateData->RootBridgeAttrib = Attri;
-
- PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
- EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
- EFI_PCI_ATTRIBUTE_ISA_IO_16 |
- EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
- EFI_PCI_ATTRIBUTE_VGA_MEMORY |
- EFI_PCI_ATTRIBUTE_VGA_IO_16 |
- EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
- PrivateData->Attributes = PrivateData->Supports;
-
- Protocol->ParentHandle = HostBridgeHandle;
-
- Protocol->PollMem = RootBridgeIoPollMem;
- Protocol->PollIo = RootBridgeIoPollIo;
-
- Protocol->Mem.Read = RootBridgeIoMemRead;
- Protocol->Mem.Write = RootBridgeIoMemWrite;
-
- Protocol->Io.Read = RootBridgeIoIoRead;
- Protocol->Io.Write = RootBridgeIoIoWrite;
-
- Protocol->CopyMem = RootBridgeIoCopyMem;
-
- Protocol->Pci.Read = RootBridgeIoPciRead;
- Protocol->Pci.Write = RootBridgeIoPciWrite;
-
- Protocol->Map = RootBridgeIoMap;
- Protocol->Unmap = RootBridgeIoUnmap;
-
- Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;
- Protocol->FreeBuffer = RootBridgeIoFreeBuffer;
-
- Protocol->Flush = RootBridgeIoFlush;
-
- Protocol->GetAttributes = RootBridgeIoGetAttributes;
- Protocol->SetAttributes = RootBridgeIoSetAttributes;
-
- Protocol->Configuration = RootBridgeIoConfiguration;
-
- Protocol->SegmentNumber = 0;
-
- Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL,
- (VOID **)&mMetronome);
- ASSERT_EFI_ERROR (Status);
-
- return EFI_SUCCESS;
-}
-
-/**
- Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
-
- The I/O operations are carried out exactly as requested. The caller is
- responsible for satisfying any alignment and I/O width restrictions that a PI
- System on a platform might require. For example on some platforms, width
- requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other
- hand, will be handled by the driver.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] OperationType I/O operation type: IO/MMIO/PCI.
-
- @param[in] Width Signifies the width of the I/O or Memory operation.
-
- @param[in] Address The base address of the I/O operation.
-
- @param[in] Count The number of I/O operations to perform. The number
- of bytes moved is Width size * Count, starting at
- Address.
-
- @param[in] Buffer For read operations, the destination buffer to
- store the results. For write operations, the source
- buffer from which to write data.
-
- @retval EFI_SUCCESS The parameters for this request pass the
- checks.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
-
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,
- and Count is not valid for this PI system.
-**/
-EFI_STATUS
-RootBridgeIoCheckParameter (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN OPERATION_TYPE OperationType,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
- UINT64 MaxCount;
- UINT64 Base;
- UINT64 Limit;
-
- //
- // Check to see if Buffer is NULL
- //
- if (Buffer == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Check to see if Width is in the valid range
- //
- if ((UINT32)Width >= EfiPciWidthMaximum) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // For FIFO type, the target address won't increase during the access,
- // so treat Count as 1
- //
- if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
- Count = 1;
- }
-
- //
- // Check to see if Width is in the valid range for I/O Port operations
- //
- Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
- if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {
- ASSERT (FALSE);
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Check to see if Address is aligned
- //
- if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
- return EFI_UNSUPPORTED;
- }
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
-
- //
- // Check to see if any address associated with this transfer exceeds the
- // maximum allowed address. The maximum address implied by the parameters
- // passed in is Address + Size * Count. If the following condition is met,
- // then the transfer is not supported.
- //
- // Address + Size * Count > Limit + 1
- //
- // Since Limit can be the maximum integer value supported by the CPU and
- // Count can also be the maximum integer value supported by the CPU, this
- // range check must be adjusted to avoid all oveflow conditions.
- //
- // The following form of the range check is equivalent but assumes that
- // Limit is of the form (2^n - 1).
- //
- if (OperationType == IoOperation) {
- Base = PrivateData->IoBase;
- Limit = PrivateData->IoLimit;
- } else if (OperationType == MemOperation) {
- Base = PrivateData->MemBase;
- Limit = PrivateData->MemLimit;
- } else {
- PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
- if (PciRbAddr->Bus < PrivateData->BusBase ||
- PciRbAddr->Bus > PrivateData->BusLimit) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER ||
- PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (PciRbAddr->ExtendedRegister != 0) {
- Address = PciRbAddr->ExtendedRegister;
- } else {
- Address = PciRbAddr->Register;
- }
- Base = 0;
- Limit = MAX_PCI_REG_ADDRESS;
- }
-
- if (Address < Base) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (Count == 0) {
- if (Address > Limit) {
- return EFI_UNSUPPORTED;
- }
- } else {
- MaxCount = RShiftU64 (Limit, Width);
- if (MaxCount < (Count - 1)) {
- return EFI_UNSUPPORTED;
- }
- if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
- return EFI_UNSUPPORTED;
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Internal help function for read and write memory space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Write Switch value for Read or Write.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] UserAddress The address within the PCI configuration space for
- the PCI controller.
-
- @param[in] Count The number of PCI configuration operations to
- perform. Bytes moved is Width size * Count,
- starting at Address.
-
- @param[in, out] UserBuffer For read operations, the destination buffer to
- store the results. For write operations, the
- source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-RootBridgeIoMemRW (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN BOOLEAN Write,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT8 InStride;
- UINT8 OutStride;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
- UINT8 *Uint8Buffer;
-
- Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
- Count, Buffer);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
- for (Uint8Buffer = Buffer;
- Count > 0;
- Address += InStride, Uint8Buffer += OutStride, Count--) {
- if (Write) {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- MmioWrite8 ((UINTN)Address, *Uint8Buffer);
- break;
- case EfiPciWidthUint16:
- MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
- break;
- case EfiPciWidthUint32:
- MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
- break;
- case EfiPciWidthUint64:
- MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- } else {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- *Uint8Buffer = MmioRead8 ((UINTN)Address);
- break;
- case EfiPciWidthUint16:
- *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
- break;
- case EfiPciWidthUint32:
- *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
- break;
- case EfiPciWidthUint64:
- *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- }
- }
- return EFI_SUCCESS;
-}
-
-/**
- Internal help function for read and write IO space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Write Switch value for Read or Write.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] UserAddress The address within the PCI configuration space for
- the PCI controller.
-
- @param[in] Count The number of PCI configuration operations to
- perform. Bytes moved is Width size * Count,
- starting at Address.
-
- @param[in, out] UserBuffer For read operations, the destination buffer to
- store the results. For write operations, the
- source buffer to write data from.
-
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-RootBridgeIoIoRW (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN BOOLEAN Write,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT8 InStride;
- UINT8 OutStride;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
- UINT8 *Uint8Buffer;
-
- Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address,
- Count, Buffer);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
-
-#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
- if (InStride == 0) {
- if (Write) {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- IoWriteFifo8 ((UINTN) Address, Count, Buffer);
- return EFI_SUCCESS;
- case EfiPciWidthUint16:
- IoWriteFifo16 ((UINTN) Address, Count, Buffer);
- return EFI_SUCCESS;
- case EfiPciWidthUint32:
- IoWriteFifo32 ((UINTN) Address, Count, Buffer);
- return EFI_SUCCESS;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- } else {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- IoReadFifo8 ((UINTN) Address, Count, Buffer);
- return EFI_SUCCESS;
- case EfiPciWidthUint16:
- IoReadFifo16 ((UINTN) Address, Count, Buffer);
- return EFI_SUCCESS;
- case EfiPciWidthUint32:
- IoReadFifo32 ((UINTN) Address, Count, Buffer);
- return EFI_SUCCESS;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- }
- }
-#endif
-
- for (Uint8Buffer = Buffer;
- Count > 0;
- Address += InStride, Uint8Buffer += OutStride, Count--) {
- if (Write) {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- IoWrite8 ((UINTN)Address, *Uint8Buffer);
- break;
- case EfiPciWidthUint16:
- IoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
- break;
- case EfiPciWidthUint32:
- IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- } else {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- *Uint8Buffer = IoRead8 ((UINTN)Address);
- break;
- case EfiPciWidthUint16:
- *((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);
- break;
- case EfiPciWidthUint32:
- *((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- }
- }
- return EFI_SUCCESS;
-}
-
-/**
- Internal help function for read and write PCI configuration space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Write Switch value for Read or Write.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] UserAddress The address within the PCI configuration space for
- the PCI controller.
-
- @param[in] Count The number of PCI configuration operations to
- perform. Bytes moved is Width size * Count,
- starting at Address.
-
- @param[in, out] UserBuffer For read operations, the destination buffer to
- store the results. For write operations, the
- source buffer to write data from.
-
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-RootBridgeIoPciRW (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN BOOLEAN Write,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT8 InStride;
- UINT8 OutStride;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
- UINT8 *Uint8Buffer;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
- UINTN PcieRegAddr;
-
- Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address,
- Count, Buffer);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
-
- PcieRegAddr = (UINTN) PCI_LIB_ADDRESS (
- PciRbAddr->Bus,
- PciRbAddr->Device,
- PciRbAddr->Function,
- (PciRbAddr->ExtendedRegister != 0) ? \
- PciRbAddr->ExtendedRegister :
- PciRbAddr->Register
- );
-
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
- for (Uint8Buffer = Buffer;
- Count > 0;
- PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {
- if (Write) {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- PciWrite8 (PcieRegAddr, *Uint8Buffer);
- break;
- case EfiPciWidthUint16:
- PciWrite16 (PcieRegAddr, *((UINT16 *)Uint8Buffer));
- break;
- case EfiPciWidthUint32:
- PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- } else {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- *Uint8Buffer = PciRead8 (PcieRegAddr);
- break;
- case EfiPciWidthUint16:
- *((UINT16 *)Uint8Buffer) = PciRead16 (PcieRegAddr);
- break;
- case EfiPciWidthUint32:
- *((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Polls an address in memory mapped I/O space until an exit condition is met,
- or a timeout occurs.
-
- This function provides a standard way to poll a PCI memory location. A PCI
- memory read operation is performed at the PCI memory address specified by
- Address for the width specified by Width. The result of this PCI memory read
- operation is stored in Result. This PCI memory read operation is repeated
- until either a timeout of Delay 100 ns units has expired, or (Result & Mask)
- is equal to Value.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] Address The base address of the memory operations. The caller
- is responsible for aligning Address if required.
-
- @param[in] Mask Mask used for the polling criteria. Bytes above Width
- in Mask are ignored. The bits in the bytes below Width
- which are zero in Mask are ignored when polling the
- memory address.
-
- @param[in] Value The comparison value used for the polling exit
- criteria.
-
- @param[in] Delay The number of 100 ns units to poll. Note that timer
- available may be of poorer granularity.
-
- @param[out] Result Pointer to the last value read from the memory
- location.
-
- @retval EFI_SUCCESS The last data returned from the access matched
- the poll exit criteria.
-
- @retval EFI_INVALID_PARAMETER Width is invalid.
-
- @retval EFI_INVALID_PARAMETER Result is NULL.
-
- @retval EFI_TIMEOUT Delay expired before a match occurred.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPollMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINT64 Mask,
- IN UINT64 Value,
- IN UINT64 Delay,
- OUT UINT64 *Result
- )
-{
- EFI_STATUS Status;
- UINT64 NumberOfTicks;
- UINT32 Remainder;
-
- if (Result == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((UINT32)Width > EfiPciWidthUint64) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // No matter what, always do a single poll.
- //
- Status = This->Mem.Read (This, Width, Address, 1, Result);
- if (EFI_ERROR (Status)) {
- return Status;
- }
- if ((*Result & Mask) == Value) {
- return EFI_SUCCESS;
- }
-
- if (Delay == 0) {
- return EFI_SUCCESS;
-
- } else {
-
- //
- // Determine the proper # of metronome ticks to wait for polling the
- // location. The nuber of ticks is Roundup (Delay /
- // mMetronome->TickPeriod)+1
- // The "+1" to account for the possibility of the first tick being short
- // because we started in the middle of a tick.
- //
- // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
- // protocol definition is updated.
- //
- NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod,
- &Remainder);
- if (Remainder != 0) {
- NumberOfTicks += 1;
- }
- NumberOfTicks += 1;
-
- while (NumberOfTicks != 0) {
-
- mMetronome->WaitForTick (mMetronome, 1);
-
- Status = This->Mem.Read (This, Width, Address, 1, Result);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- if ((*Result & Mask) == Value) {
- return EFI_SUCCESS;
- }
-
- NumberOfTicks -= 1;
- }
- }
- return EFI_TIMEOUT;
-}
-
-/**
- Reads from the I/O space of a PCI Root Bridge. Returns when either the
- polling exit criteria is satisfied or after a defined duration.
-
- This function provides a standard way to poll a PCI I/O location. A PCI I/O
- read operation is performed at the PCI I/O address specified by Address for
- the width specified by Width.
- The result of this PCI I/O read operation is stored in Result. This PCI I/O
- read operation is repeated until either a timeout of Delay 100 ns units has
- expired, or (Result & Mask) is equal to Value.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the I/O operations.
-
- @param[in] Address The base address of the I/O operations. The caller is
- responsible for aligning Address if required.
-
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in
- Mask are ignored. The bits in the bytes below Width
- which are zero in Mask are ignored when polling the I/O
- address.
-
- @param[in] Value The comparison value used for the polling exit criteria.
-
- @param[in] Delay The number of 100 ns units to poll. Note that timer
- available may be of poorer granularity.
-
- @param[out] Result Pointer to the last value read from the memory location.
-
- @retval EFI_SUCCESS The last data returned from the access matched
- the poll exit criteria.
-
- @retval EFI_INVALID_PARAMETER Width is invalid.
-
- @retval EFI_INVALID_PARAMETER Result is NULL.
-
- @retval EFI_TIMEOUT Delay expired before a match occurred.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPollIo (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINT64 Mask,
- IN UINT64 Value,
- IN UINT64 Delay,
- OUT UINT64 *Result
- )
-{
- EFI_STATUS Status;
- UINT64 NumberOfTicks;
- UINT32 Remainder;
-
- //
- // No matter what, always do a single poll.
- //
-
- if (Result == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((UINT32)Width > EfiPciWidthUint64) {
- return EFI_INVALID_PARAMETER;
- }
-
- Status = This->Io.Read (This, Width, Address, 1, Result);
- if (EFI_ERROR (Status)) {
- return Status;
- }
- if ((*Result & Mask) == Value) {
- return EFI_SUCCESS;
- }
-
- if (Delay == 0) {
- return EFI_SUCCESS;
-
- } else {
-
- //
- // Determine the proper # of metronome ticks to wait for polling the
- // location. The number of ticks is Roundup (Delay /
- // mMetronome->TickPeriod)+1
- // The "+1" to account for the possibility of the first tick being short
- // because we started in the middle of a tick.
- //
- NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod,
- &Remainder);
- if (Remainder != 0) {
- NumberOfTicks += 1;
- }
- NumberOfTicks += 1;
-
- while (NumberOfTicks != 0) {
-
- mMetronome->WaitForTick (mMetronome, 1);
-
- Status = This->Io.Read (This, Width, Address, 1, Result);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- if ((*Result & Mask) == Value) {
- return EFI_SUCCESS;
- }
-
- NumberOfTicks -= 1;
- }
- }
- return EFI_TIMEOUT;
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root
- bridge memory space.
-
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
- controller registers in the PCI root bridge memory space.
- The memory operations are carried out exactly as requested. The caller is
- responsible for satisfying any alignment and memory width restrictions that a
- PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operation.
-
- @param[in] Address The base address of the memory operation. The caller
- is responsible for aligning the Address if required.
-
- @param[in] Count The number of memory operations to perform. Bytes
- moved is Width size * Count, starting at Address.
-
- @param[out] Buffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMemRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root
- bridge memory space.
-
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI
- controller registers in the PCI root bridge memory space.
- The memory operations are carried out exactly as requested. The caller is
- responsible for satisfying any alignment and memory width restrictions that a
- PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operation.
-
- @param[in] Address The base address of the memory operation. The caller
- is responsible for aligning the Address if required.
-
- @param[in] Count The number of memory operations to perform. Bytes
- moved is Width size * Count, starting at Address.
-
- @param[in] Buffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMemWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root
- bridge I/O space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] Address The base address of the I/O operation. The caller is
- responsible for aligning the Address if required.
-
- @param[in] Count The number of I/O operations to perform. Bytes moved
- is Width size * Count, starting at Address.
-
- @param[out] Buffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoIoRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root
- bridge I/O space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] Address The base address of the I/O operation. The caller is
- responsible for aligning the Address if required.
-
- @param[in] Count The number of I/O operations to perform. Bytes moved
- is Width size * Count, starting at Address.
-
- @param[in] Buffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoIoWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);
-}
-
-/**
- Enables a PCI driver to copy one region of PCI root bridge memory space to
- another region of PCI root bridge memory space.
-
- The CopyMem() function enables a PCI driver to copy one region of PCI root
- bridge memory space to another region of PCI root bridge memory space. This
- is especially useful for video scroll operation on a memory mapped video
- buffer.
- The memory operations are carried out exactly as requested. The caller is
- responsible for satisfying any alignment and memory width restrictions that a
- PCI root bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
- instance.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] DestAddress The destination address of the memory operation. The
- caller is responsible for aligning the DestAddress if
- required.
-
- @param[in] SrcAddress The source address of the memory operation. The caller
- is responsible for aligning the SrcAddress if
- required.
-
- @param[in] Count The number of memory operations to perform. Bytes
- moved is Width size * Count, starting at DestAddress
- and SrcAddress.
-
- @retval EFI_SUCCESS The data was copied from one memory region
- to another memory region.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoCopyMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 DestAddress,
- IN UINT64 SrcAddress,
- IN UINTN Count
- )
-{
- EFI_STATUS Status;
- BOOLEAN Direction;
- UINTN Stride;
- UINTN Index;
- UINT64 Result;
-
- if ((UINT32)Width > EfiPciWidthUint64) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (DestAddress == SrcAddress) {
- return EFI_SUCCESS;
- }
-
- Stride = (UINTN)(1 << Width);
-
- Direction = TRUE;
- if ((DestAddress > SrcAddress) &&
- (DestAddress < (SrcAddress + Count * Stride))) {
- Direction = FALSE;
- SrcAddress = SrcAddress + (Count-1) * Stride;
- DestAddress = DestAddress + (Count-1) * Stride;
- }
-
- for (Index = 0;Index < Count;Index++) {
- Status = RootBridgeIoMemRead (
- This,
- Width,
- SrcAddress,
- 1,
- &Result
- );
- if (EFI_ERROR (Status)) {
- return Status;
- }
- Status = RootBridgeIoMemWrite (
- This,
- Width,
- DestAddress,
- 1,
- &Result
- );
- if (EFI_ERROR (Status)) {
- return Status;
- }
- if (Direction) {
- SrcAddress += Stride;
- DestAddress += Stride;
- } else {
- SrcAddress -= Stride;
- DestAddress -= Stride;
- }
- }
- return EFI_SUCCESS;
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in a PCI root
- bridge's configuration space.
-
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI
- configuration registers for a PCI controller.
- The PCI Configuration operations are carried out exactly as requested. The
- caller is responsible for any alignment and PCI configuration width issues
- that a PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] Address The address within the PCI configuration space for the
- PCI controller.
-
- @param[in] Count The number of PCI configuration operations to perform.
- Bytes moved is Width size * Count, starting at
- Address.
-
- @param[out] Buffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPciRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in a PCI root
- bridge's configuration space.
-
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI
- configuration registers for a PCI controller.
- The PCI Configuration operations are carried out exactly as requested. The
- caller is responsible for any alignment and PCI configuration width issues
- that a PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Width Signifies the width of the memory operations.
-
- @param[in] Address The address within the PCI configuration space for the
- PCI controller.
-
- @param[in] Count The number of PCI configuration operations to perform.
- Bytes moved is Width size * Count, starting at
- Address.
-
- @param[in] Buffer For read operations, the destination buffer to store
- the results. For write operations, the source buffer
- to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI
- root bridge.
-
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
-
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPciWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
-}
-
-/**
- Provides the PCI controller-specific addresses required to access system
- memory from a DMA bus master.
-
- The Map() function provides the PCI controller specific addresses needed to
- access system memory. This function is used to map system memory for PCI bus
- master DMA accesses.
-
- @param[in] This A pointer to the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Operation Indicates if the bus master is going to read
- or write to system memory.
-
- @param[in] HostAddress The system memory address to map to the PCI
- controller.
-
- @param[in, out] NumberOfBytes On input the number of bytes to map. On
- output the number of bytes that were mapped.
-
- @param[out] DeviceAddress The resulting map address for the bus master
- PCI controller to use to access the system
- memory's HostAddress.
-
- @param[out] Mapping The value to pass to Unmap() when the bus
- master DMA operation is complete.
-
- @retval EFI_SUCCESS The range was mapped for the returned
- NumberOfBytes.
-
- @retval EFI_INVALID_PARAMETER Operation is invalid.
-
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.
-
- @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
-
- @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
-
- @retval EFI_INVALID_PARAMETER Mapping is NULL.
-
- @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common
- buffer.
-
- @retval EFI_DEVICE_ERROR The system hardware could not map the
- requested address.
-
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
- lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMap (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
- IN VOID *HostAddress,
- IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PhysicalAddress;
- MAP_INFO *MapInfo;
-
- if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||
- Mapping == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Initialize the return values to their defaults
- //
- *Mapping = NULL;
-
- //
- // Make sure that Operation is valid
- //
- if ((UINT32)Operation >= EfiPciOperationMaximum) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Most PCAT like chipsets can not handle performing DMA above 4GB.
- // If any part of the DMA transfer being mapped is above 4GB, then
- // map the DMA transfer to a buffer below 4GB.
- //
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
- if ((PhysicalAddress + *NumberOfBytes) > 0x100000000ULL) {
-
- //
- // Common Buffer operations can not be remapped. If the common buffer
- // if above 4GB, then it is not possible to generate a mapping, so return
- // an error.
- //
- if (Operation == EfiPciOperationBusMasterCommonBuffer ||
- Operation == EfiPciOperationBusMasterCommonBuffer64) {
- return EFI_UNSUPPORTED;
- }
-
- //
- // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
- // called later.
- //
- Status = gBS->AllocatePool (
- EfiBootServicesData,
- sizeof(MAP_INFO),
- (VOID **)&MapInfo
- );
- if (EFI_ERROR (Status)) {
- *NumberOfBytes = 0;
- return Status;
- }
-
- //
- // Return a pointer to the MAP_INFO structure in Mapping
- //
- *Mapping = MapInfo;
-
- //
- // Initialize the MAP_INFO structure
- //
- MapInfo->Operation = Operation;
- MapInfo->NumberOfBytes = *NumberOfBytes;
- MapInfo->NumberOfPages = EFI_SIZE_TO_PAGES(*NumberOfBytes);
- MapInfo->HostAddress = PhysicalAddress;
- MapInfo->MappedHostAddress = 0x00000000ffffffff;
-
- //
- // Allocate a buffer below 4GB to map the transfer to.
- //
- Status = gBS->AllocatePages (
- AllocateMaxAddress,
- EfiBootServicesData,
- MapInfo->NumberOfPages,
- &MapInfo->MappedHostAddress
- );
- if (EFI_ERROR (Status)) {
- gBS->FreePool (MapInfo);
- *NumberOfBytes = 0;
- return Status;
- }
-
- //
- // If this is a read operation from the Bus Master's point of view,
- // then copy the contents of the real buffer into the mapped buffer
- // so the Bus Master can read the contents of the real buffer.
- //
- if (Operation == EfiPciOperationBusMasterRead ||
- Operation == EfiPciOperationBusMasterRead64) {
- CopyMem (
- (VOID *)(UINTN)MapInfo->MappedHostAddress,
- (VOID *)(UINTN)MapInfo->HostAddress,
- MapInfo->NumberOfBytes
- );
- }
-
- //
- // The DeviceAddress is the address of the maped buffer below 4GB
- //
- *DeviceAddress = MapInfo->MappedHostAddress;
- } else {
- //
- // The transfer is below 4GB, so the DeviceAddress is simply the
- // HostAddress
- //
- *DeviceAddress = PhysicalAddress;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Completes the Map() operation and releases any corresponding resources.
-
- The Unmap() function completes the Map() operation and releases any
- corresponding resources.
- If the operation was an EfiPciOperationBusMasterWrite or
- EfiPciOperationBusMasterWrite64, the data is committed to the target system
- memory.
- Any resources used for the mapping are freed.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Mapping The mapping value returned from Map().
-
- @retval EFI_SUCCESS The range was unmapped.
-
- @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by
- Map().
-
- @retval EFI_DEVICE_ERROR The data was not committed to the target
- system memory.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoUnmap (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN VOID *Mapping
- )
-{
- MAP_INFO *MapInfo;
-
- //
- // See if the Map() operation associated with this Unmap() required a mapping
- // buffer. If a mapping buffer was not required, then this function simply
- // returns EFI_SUCCESS.
- //
- if (Mapping != NULL) {
- //
- // Get the MAP_INFO structure from Mapping
- //
- MapInfo = (MAP_INFO *)Mapping;
-
- //
- // If this is a write operation from the Bus Master's point of view,
- // then copy the contents of the mapped buffer into the real buffer
- // so the processor can read the contents of the real buffer.
- //
- if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||
- MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
- CopyMem (
- (VOID *)(UINTN)MapInfo->HostAddress,
- (VOID *)(UINTN)MapInfo->MappedHostAddress,
- MapInfo->NumberOfBytes
- );
- }
-
- //
- // Free the mapped buffer and the MAP_INFO structure.
- //
- gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);
- gBS->FreePool (Mapping);
- }
- return EFI_SUCCESS;
-}
-
-/**
- Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer
- or EfiPciOperationBusMasterCommonBuffer64 mapping.
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param Type This parameter is not used and must be ignored.
-
- @param MemoryType The type of memory to allocate, EfiBootServicesData or
- EfiRuntimeServicesData.
-
- @param Pages The number of pages to allocate.
-
- @param HostAddress A pointer to store the base system memory address of the
- allocated range.
-
- @param Attributes The requested bit mask of attributes for the allocated
- range. Only the attributes
- EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE,
- EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and
- EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this
- function.
-
- @retval EFI_SUCCESS The requested memory pages were allocated.
-
- @retval EFI_INVALID_PARAMETER MemoryType is invalid.
-
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.
-
- @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal
- attribute bits are MEMORY_WRITE_COMBINE,
- MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
-
- @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoAllocateBuffer (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_ALLOCATE_TYPE Type,
- IN EFI_MEMORY_TYPE MemoryType,
- IN UINTN Pages,
- OUT VOID **HostAddress,
- IN UINT64 Attributes
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PhysicalAddress;
-
- //
- // Validate Attributes
- //
- if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {
- return EFI_UNSUPPORTED;
- }
-
- //
- // Check for invalid inputs
- //
- if (HostAddress == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // The only valid memory types are EfiBootServicesData and
- // EfiRuntimeServicesData
- //
- if (MemoryType != EfiBootServicesData &&
- MemoryType != EfiRuntimeServicesData) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Limit allocations to memory below 4GB
- //
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);
-
- Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages,
- &PhysicalAddress);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- *HostAddress = (VOID *)(UINTN)PhysicalAddress;
-
- return EFI_SUCCESS;
-}
-
-/**
- Frees memory that was allocated with AllocateBuffer().
-
- The FreeBuffer() function frees memory that was allocated with
- AllocateBuffer().
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param Pages The number of pages to free.
-
- @param HostAddress The base system memory address of the allocated range.
-
- @retval EFI_SUCCESS The requested memory pages were freed.
-
- @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and
- Pages was not allocated with AllocateBuffer().
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoFreeBuffer (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN UINTN Pages,
- OUT VOID *HostAddress
- )
-{
- return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);
-}
-
-/**
- Flushes all PCI posted write transactions from a PCI host bridge to system
- memory.
-
- The Flush() function flushes any PCI posted write transactions from a PCI
- host bridge to system memory. Posted write transactions are generated by PCI
- bus masters when they perform write transactions to target addresses in
- system memory.
- This function does not flush posted write transactions from any PCI bridges.
- A PCI controller specific action must be taken to guarantee that the posted
- write transactions have been flushed from the PCI controller and from all the
- PCI bridges into the PCI host bridge. This is typically done with a PCI read
- transaction from the PCI controller prior to calling Flush().
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @retval EFI_SUCCESS The PCI posted write transactions were flushed
- from the PCI host bridge to system memory.
-
- @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed
- from the PCI host bridge due to a hardware error.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoFlush (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
- )
-{
- //
- // not supported yet
- //
- return EFI_SUCCESS;
-}
-
-/**
- Gets the attributes that a PCI root bridge supports setting with
- SetAttributes(), and the attributes that a PCI root bridge is currently
- using.
-
- The GetAttributes() function returns the mask of attributes that this PCI
- root bridge supports and the mask of attributes that the PCI root bridge is
- currently using.
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param Supported A pointer to the mask of attributes that this PCI root
- bridge supports setting with SetAttributes().
-
- @param Attributes A pointer to the mask of attributes that this PCI root
- bridge is currently using.
-
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes
- that the PCI root bridge supports is returned
- in Supports. If Attributes is not NULL, then
- the attributes that the PCI root bridge is
- currently using is returned in Attributes.
-
- @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoGetAttributes (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- OUT UINT64 *Supported,
- OUT UINT64 *Attributes
- )
-{
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
-
- if (Attributes == NULL && Supported == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Set the return value for Supported and Attributes
- //
- if (Supported != NULL) {
- *Supported = PrivateData->Supports;
- }
-
- if (Attributes != NULL) {
- *Attributes = PrivateData->Attributes;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Sets attributes for a resource range on a PCI root bridge.
-
- The SetAttributes() function sets the attributes specified in Attributes for
- the PCI root bridge on the resource range specified by ResourceBase and
- ResourceLength. Since the granularity of setting these attributes may vary
- from resource type to resource type, and from platform to platform, the
- actual resource range and the one passed in by the caller may differ. As a
- result, this function may set the attributes specified by Attributes on a
- larger resource range than the caller requested. The actual range is returned
- in ResourceBase and ResourceLength. The caller is responsible for verifying
- that the actual range for which the attributes were set is acceptable.
-
- @param[in] This A pointer to the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[in] Attributes The mask of attributes to set. If the
- attribute bit MEMORY_WRITE_COMBINE,
- MEMORY_CACHED, or MEMORY_DISABLE is set,
- then the resource range is specified by
- ResourceBase and ResourceLength. If
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
- MEMORY_DISABLE are not set, then
- ResourceBase and ResourceLength are ignored,
- and may be NULL.
-
- @param[in, out] ResourceBase A pointer to the base address of the
- resource range to be modified by the
- attributes specified by Attributes.
-
- @param[in, out] ResourceLength A pointer to the length of the resource
- range to be modified by the attributes
- specified by Attributes.
-
- @retval EFI_SUCCESS The current configuration of this PCI root bridge
- was returned in Resources.
-
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
- could not be retrieved.
-
- @retval EFI_INVALID_PARAMETER Invalid pointer of
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoSetAttributes (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN UINT64 Attributes,
- IN OUT UINT64 *ResourceBase,
- IN OUT UINT64 *ResourceLength
- )
-{
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
-
- if (Attributes != 0) {
- if ((Attributes & (~(PrivateData->Supports))) != 0) {
- return EFI_UNSUPPORTED;
- }
- }
-
- //
- // This is a generic driver for a PC-AT class system. It does not have any
- // chipset specific knowlegde, so none of the attributes can be set or
- // cleared. Any attempt to set attribute that are already set will succeed,
- // and any attempt to set an attribute that is not supported will fail.
- //
- if (Attributes & (~PrivateData->Attributes)) {
- return EFI_UNSUPPORTED;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Retrieves the current resource settings of this PCI root bridge in the form
- of a set of ACPI 2.0 resource descriptors.
-
- There are only two resource descriptor types from the ACPI Specification that
- may be used to describe the current resources allocated to a PCI root bridge.
- These are the QWORD Address Space Descriptor (ACPI 2.0 Section 6.4.3.5.1),
- and the End Tag (ACPI 2.0 Section 6.4.2.8). The QWORD Address Space
- Descriptor can describe memory, I/O, and bus number ranges for dynamic or
- fixed resources. The configuration of a PCI root bridge is described with one
- or more QWORD Address Space Descriptors followed by an End Tag.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that
- describe the current configuration of this PCI root
- bridge. The storage for the ACPI 2.0 resource
- descriptors is allocated by this function. The
- caller must treat the return buffer as read-only
- data, and the buffer must not be freed by the
- caller.
-
- @retval EFI_SUCCESS The current configuration of this PCI root bridge
- was returned in Resources.
-
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge
- could not be retrieved.
-
- @retval EFI_INVALID_PARAMETER Invalid pointer of
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoConfiguration (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- OUT VOID **Resources
- )
-{
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
- UINTN Index;
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
- CopyMem (&PrivateData->ConfigBuffer, &mConfigurationTemplate,
- sizeof mConfigurationTemplate);
-
- for (Index = 0; Index < TypeMax; Index++) {
- if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
-
- Desc = &PrivateData->ConfigBuffer.SpaceDesc[Index];
- Desc->AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
- Desc->AddrRangeMax = PrivateData->ResAllocNode[Index].Base +
- PrivateData->ResAllocNode[Index].Length - 1;
- Desc->AddrLen = PrivateData->ResAllocNode[Index].Length;
- }
- }
-
- *Resources = &PrivateData->ConfigBuffer;
- return EFI_SUCCESS;
-}
-
diff --git a/RiscVVirtPkg/Universal/PciHostBridgeDxe/X64/IoFifo.S b/RiscVVirtPkg/Universal/PciHostBridgeDxe/X64/IoFifo.S
deleted file mode 100644
index decb382..0000000
--- a/RiscVVirtPkg/Universal/PciHostBridgeDxe/X64/IoFifo.S
+++ /dev/null
@@ -1,122 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials are licensed and made available
-# under the terms and conditions of the BSD License which accompanies this
-# distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoReadFifo8 (
-# IN UINTN Port, // rcx
-# IN UINTN Count, // rdx
-# IN VOID *Buffer // r8
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoReadFifo8)
-ASM_PFX(IoReadFifo8):
- cld
- xchg %rcx, %rdx
- xchg %r8, %rdi # rdi: buffer address; r8: save register
-rep insb
- mov %r8, %rdi # restore rdi
- ret
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoReadFifo16 (
-# IN UINTN Port, // rcx
-# IN UINTN Count, // rdx
-# IN VOID *Buffer // r8
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoReadFifo16)
-ASM_PFX(IoReadFifo16):
- cld
- xchg %rcx, %rdx
- xchg %r8, %rdi # rdi: buffer address; r8: save register
-rep insw
- mov %r8, %rdi # restore rdi
- ret
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoReadFifo32 (
-# IN UINTN Port, // rcx
-# IN UINTN Count, // rdx
-# IN VOID *Buffer // r8
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoReadFifo32)
-ASM_PFX(IoReadFifo32):
- cld
- xchg %rcx, %rdx
- xchg %r8, %rdi # rdi: buffer address; r8: save register
-rep insl
- mov %r8, %rdi # restore rdi
- ret
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoWriteFifo8 (
-# IN UINTN Port, // rcx
-# IN UINTN Count, // rdx
-# IN VOID *Buffer // r8
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoWriteFifo8)
-ASM_PFX(IoWriteFifo8):
- cld
- xchg %rcx, %rdx
- xchg %r8, %rsi # rsi: buffer address; r8: save register
-rep outsb
- mov %r8, %rsi # restore rsi
- ret
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoWriteFifo16 (
-# IN UINTN Port, // rcx
-# IN UINTN Count, // rdx
-# IN VOID *Buffer // r8
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoWriteFifo16)
-ASM_PFX(IoWriteFifo16):
- cld
- xchg %rcx, %rdx
- xchg %r8, %rsi # rsi: buffer address; r8: save register
-rep outsw
- mov %r8, %rsi # restore rsi
- ret
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# IoWriteFifo32 (
-# IN UINTN Port, // rcx
-# IN UINTN Count, // rdx
-# IN VOID *Buffer // r8
-# );
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX(IoWriteFifo32)
-ASM_PFX(IoWriteFifo32):
- cld
- xchg %rcx, %rdx
- xchg %r8, %rsi # rsi: buffer address; r8: save register
-rep outsl
- mov %r8, %rsi # restore rsi
- ret
-
diff --git a/RiscVVirtPkg/Universal/PciHostBridgeDxe/X64/IoFifo.asm b/RiscVVirtPkg/Universal/PciHostBridgeDxe/X64/IoFifo.asm
deleted file mode 100644
index 1a3f0ef..0000000
--- a/RiscVVirtPkg/Universal/PciHostBridgeDxe/X64/IoFifo.asm
+++ /dev/null
@@ -1,126 +0,0 @@
-;------------------------------------------------------------------------------
-;
-; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-;
-; This program and the accompanying materials are licensed and made available
-; under the terms and conditions of the BSD License which accompanies this
-; distribution. The full text of the license may be found at
-; http://opensource.org/licenses/bsd-license.php.
-;
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-;
-;------------------------------------------------------------------------------
-
- .code
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoReadFifo8 (
-; IN UINTN Port, // rcx
-; IN UINTN Size, // rdx
-; IN VOID *Buffer // r8
-; );
-;------------------------------------------------------------------------------
-IoReadFifo8 PROC
- cld
- xchg rcx, rdx
- xchg rdi, r8 ; rdi: buffer address; r8: save rdi
-rep insb
- mov rdi, r8 ; restore rdi
- ret
-IoReadFifo8 ENDP
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoReadFifo16 (
-; IN UINTN Port, // rcx
-; IN UINTN Size, // rdx
-; IN VOID *Buffer // r8
-; );
-;------------------------------------------------------------------------------
-IoReadFifo16 PROC
- cld
- xchg rcx, rdx
- xchg rdi, r8 ; rdi: buffer address; r8: save rdi
-rep insw
- mov rdi, r8 ; restore rdi
- ret
-IoReadFifo16 ENDP
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoReadFifo32 (
-; IN UINTN Port, // rcx
-; IN UINTN Size, // rdx
-; IN VOID *Buffer // r8
-; );
-;------------------------------------------------------------------------------
-IoReadFifo32 PROC
- cld
- xchg rcx, rdx
- xchg rdi, r8 ; rdi: buffer address; r8: save rdi
-rep insd
- mov rdi, r8 ; restore rdi
- ret
-IoReadFifo32 ENDP
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoWriteFifo8 (
-; IN UINTN Port, // rcx
-; IN UINTN Size, // rdx
-; IN VOID *Buffer // r8
-; );
-;------------------------------------------------------------------------------
-IoWriteFifo8 PROC
- cld
- xchg rcx, rdx
- xchg rsi, r8 ; rsi: buffer address; r8: save rsi
-rep outsb
- mov rsi, r8 ; restore rsi
- ret
-IoWriteFifo8 ENDP
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoWriteFifo16 (
-; IN UINTN Port, // rcx
-; IN UINTN Size, // rdx
-; IN VOID *Buffer // r8
-; );
-;------------------------------------------------------------------------------
-IoWriteFifo16 PROC
- cld
- xchg rcx, rdx
- xchg rsi, r8 ; rsi: buffer address; r8: save rsi
-rep outsw
- mov rsi, r8 ; restore rsi
- ret
-IoWriteFifo16 ENDP
-
-;------------------------------------------------------------------------------
-; VOID
-; EFIAPI
-; IoWriteFifo32 (
-; IN UINTN Port, // rcx
-; IN UINTN Size, // rdx
-; IN VOID *Buffer // r8
-; );
-;------------------------------------------------------------------------------
-IoWriteFifo32 PROC
- cld
- xchg rcx, rdx
- xchg rsi, r8 ; rsi: buffer address; r8: save rsi
-rep outsd
- mov rsi, r8 ; restore rsi
- ret
-IoWriteFifo32 ENDP
-
- END
-
diff --git a/RiscVVirtPkg/Universal/PlatformPei/Cmos.c b/RiscVVirtPkg/Universal/PlatformPei/Cmos.c
deleted file mode 100644
index 629c3cf..0000000
--- a/RiscVVirtPkg/Universal/PlatformPei/Cmos.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/** @file
- PC/AT CMOS access routines
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "Cmos.h"
-#include "Library/IoLib.h"
-
-/**
- Reads 8-bits of CMOS data.
-
- Reads the 8-bits of CMOS data at the location specified by Index.
- The 8-bit read value is returned.
-
- @param Index The CMOS location to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-CmosRead8 (
- IN UINTN Index
- )
-{
- IoWrite8 (0x70, (UINT8) Index);
- return IoRead8 (0x71);
-}
-
-/**
- Writes 8-bits of CMOS data.
-
- Writes 8-bits of CMOS data to the location specified by Index
- with the value specified by Value and returns Value.
-
- @param Index The CMOS location to write.
- @param Value The value to write to CMOS.
-
- @return The value written to CMOS.
-
-**/
-UINT8
-EFIAPI
-CmosWrite8 (
- IN UINTN Index,
- IN UINT8 Value
- )
-{
- IoWrite8 (0x70, (UINT8) Index);
- IoWrite8 (0x71, Value);
- return Value;
-}
diff --git a/RiscVVirtPkg/Universal/PlatformPei/Cmos.h b/RiscVVirtPkg/Universal/PlatformPei/Cmos.h
deleted file mode 100644
index 04cc5af..0000000
--- a/RiscVVirtPkg/Universal/PlatformPei/Cmos.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/** @file
- PC/AT CMOS access routines
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __CMOS_H__
-#define __CMOS_H__
-
-/**
- Reads 8-bits of CMOS data.
-
- Reads the 8-bits of CMOS data at the location specified by Index.
- The 8-bit read value is returned.
-
- @param Index The CMOS location to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-CmosRead8 (
- IN UINTN Index
- );
-
-/**
- Writes 8-bits of CMOS data.
-
- Writes 8-bits of CMOS data to the location specified by Index
- with the value specified by Value and returns Value.
-
- @param Index The CMOS location to write.
- @param Value The value to write to CMOS.
-
- @return The value written to CMOS.
-
-**/
-UINT8
-EFIAPI
-CmosWrite8 (
- IN UINTN Index,
- IN UINT8 Value
- );
-
-
-#endif
diff --git a/RiscVVirtPkg/Universal/PlatformPei/Fv.c b/RiscVVirtPkg/Universal/PlatformPei/Fv.c
deleted file mode 100644
index e03587e..0000000
--- a/RiscVVirtPkg/Universal/PlatformPei/Fv.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/** @file
- Build FV related hobs for platform.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "PiPei.h"
-#include "Platform.h"
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/PcdLib.h>
-
-/**
- Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
- and DXE know about them.
-
- @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.
-
-**/
-EFI_STATUS
-PeiFvInitialization (
- VOID
- )
-{
- DEBUG ((EFI_D_INFO, "Platform PEI Firmware Volume Initialization\n"));
-
- //
- // Create a memory allocation HOB for the PEI FV.
- //
- // Allocate as ACPI NVS is S3 is supported
- //
- BuildMemoryAllocationHob (
- PcdGet32 (PcdOvmfPeiMemFvBase),
- PcdGet32 (PcdOvmfPeiMemFvSize),
- mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
- );
-
- //
- // Let DXE know about the DXE FV
- //
- BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
- DEBUG ((EFI_D_INFO, "Platform builds DXE FV at %x, size %x.\n", PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)));
-
- //
- // Create a memory allocation HOB for the DXE FV.
- //
- BuildMemoryAllocationHob (
- PcdGet32 (PcdOvmfDxeMemFvBase),
- PcdGet32 (PcdOvmfDxeMemFvSize),
- EfiBootServicesData
- );
-
- //
- // Let PEI know about the DXE FV so it can find the DXE Core
- //
- PeiServicesInstallFvInfoPpi (
- NULL,
- (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
- PcdGet32 (PcdRiscVDxeFvSize),
- NULL,
- NULL
- );
-
- return EFI_SUCCESS;
-}
diff --git a/RiscVVirtPkg/Universal/PlatformPei/MemDetect.c b/RiscVVirtPkg/Universal/PlatformPei/MemDetect.c
deleted file mode 100644
index 2723b04..0000000
--- a/RiscVVirtPkg/Universal/PlatformPei/MemDetect.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/**@file
- Memory Detection for Virtual Machines.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-Module Name:
-
- MemDetect.c
-
-**/
-
-//
-// The package level header files this module uses
-//
-#include <PiPei.h>
-
-//
-// The Library classes this module consumes
-//
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PeimEntryPoint.h>
-#include <Library/ResourcePublicationLib.h>
-
-#include "Platform.h"
-#include "Cmos.h"
-
-UINT8 mPhysMemAddressWidth = 32;
-
-UINT32
-GetSystemMemorySizeBelow4gb (
- VOID
- )
-{
- UINT8 Cmos0x34;
- UINT8 Cmos0x35;
-
- //
- // CMOS 0x34/0x35 specifies the system memory above 16 MB.
- // * CMOS(0x35) is the high byte
- // * CMOS(0x34) is the low byte
- // * The size is specified in 64kb chunks
- // * Since this is memory above 16MB, the 16MB must be added
- // into the calculation to get the total memory size.
- //
-
- Cmos0x34 = (UINT8) CmosRead8 (0x34);
- Cmos0x35 = (UINT8) CmosRead8 (0x35);
-
- return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);
-}
-
-
-STATIC
-UINT64
-GetSystemMemorySizeAbove4gb (
- )
-{
- UINT32 Size;
- UINTN CmosIndex;
-
- //
- // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
- // * CMOS(0x5d) is the most significant size byte
- // * CMOS(0x5c) is the middle size byte
- // * CMOS(0x5b) is the least significant size byte
- // * The size is specified in 64kb chunks
- //
-
- Size = 0;
- for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {
- Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);
- }
-
- return LShiftU64 (Size, 16);
-}
-
-
-/**
- Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
-**/
-VOID
-AddressWidthInitialization (
- VOID
- )
-{
-}
-
-
-/**
- Calculate the cap for the permanent PEI memory.
-**/
-STATIC
-UINT32
-GetPeiMemoryCap (
- VOID
- )
-{
- return SIZE_64MB;
-}
-
-
-/**
- Publish PEI core memory
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-PublishPeiMemory (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS MemoryBase;
- UINT64 MemorySize;
- UINT64 LowerMemorySize;
- UINT32 PeiMemoryCap;
-
- if (mBootMode == BOOT_ON_S3_RESUME) {
- MemoryBase = PcdGet32 (PcdS3AcpiReservedMemoryBase);
- MemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize);
- } else {
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();
-
- PeiMemoryCap = GetPeiMemoryCap ();
- DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB Lower memory size=%u MB\n",
- __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10, LowerMemorySize >> 20));
-
- //
- // Determine the range of memory to use during PEI
- //
- MemoryBase = PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
- MemorySize = LowerMemorySize - MemoryBase;
- if (MemorySize > PeiMemoryCap) {
- MemoryBase = LowerMemorySize - PeiMemoryCap;
- MemorySize = PeiMemoryCap;
- }
- }
-
- //
- // Publish this memory to the PEI Core
- //
- Status = PublishSystemMemory(MemoryBase, MemorySize);
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
-
-
-/**
- Peform Memory Detection for QEMU / KVM
-
-**/
-STATIC
-VOID
-QemuInitializeRam (
- VOID
- )
-{
- UINT64 LowerMemorySize;
- UINT64 UpperMemorySize;
-
- DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));
-
- //
- // Determine total memory size available
- //
- LowerMemorySize = GetSystemMemorySizeBelow4gb ();
- UpperMemorySize = GetSystemMemorySizeAbove4gb ();
-
- if (mBootMode != BOOT_ON_S3_RESUME) {
- //
- // Create memory HOBs
- //
- AddMemoryRangeHob (BASE_64KB, BASE_512KB + BASE_128KB); // From 64K, first 64K reserved by memory map I/O.
- AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
- if (UpperMemorySize != 0) {
- AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
- }
- }
-}
-
-/**
- Publish system RAM and reserve memory regions
-
-**/
-VOID
-InitializeRamRegions (
- VOID
- )
-{
- if (!mXen) {
- QemuInitializeRam ();
- } else {
- XenPublishRamRegions ();
- }
-
- if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {
- //
- // This is the memory range that will be used for PEI on S3 resume
- //
- BuildMemoryAllocationHob (
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdS3AcpiReservedMemoryBase),
- (UINT64)(UINTN) PcdGet32 (PcdS3AcpiReservedMemorySize),
- EfiACPIMemoryNVS
- );
-
- //
- // Cover the initial RAM area used as stack and temporary PEI heap.
- //
- // This is reserved as ACPI NVS so it can be used on S3 resume.
- //
- BuildMemoryAllocationHob (
- PcdGet32 (PcdRiscVSecPeiTempRamBase),
- PcdGet32 (PcdRiscVSecPeiTempRamSize),
- EfiACPIMemoryNVS
- );
-
- //
- // SEC stores its table of GUIDed section handlers here.
- //
- BuildMemoryAllocationHob (
- PcdGet64 (PcdGuidedExtractHandlerTableAddress),
- PcdGet32 (PcdGuidedExtractHandlerTableSize),
- EfiACPIMemoryNVS
- );
- }
-
- if (mBootMode != BOOT_ON_S3_RESUME) {
- //
- // Reserve the lock box storage area
- //
- // Since this memory range will be used on S3 resume, it must be
- // reserved as ACPI NVS.
- //
- // If S3 is unsupported, then various drivers might still write to the
- // LockBox area. We ought to prevent DXE from serving allocation requests
- // such that they would overlap the LockBox storage.
- //
- ZeroMem (
- (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
- (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)
- );
- BuildMemoryAllocationHob (
- (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
- (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),
- mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData
- );
- }
-}
diff --git a/RiscVVirtPkg/Universal/PlatformPei/Platform.c b/RiscVVirtPkg/Universal/PlatformPei/Platform.c
deleted file mode 100644
index f024590..0000000
--- a/RiscVVirtPkg/Universal/PlatformPei/Platform.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/**@file
- Platform PEI driver
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-//
-// The package level header files this module uses
-//
-#include <PiPei.h>
-
-//
-// The Library classes this module consumes
-//
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PciLib.h>
-#include <Library/PeimEntryPoint.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/QemuFwCfgLib.h>
-#include <Library/ResourcePublicationLib.h>
-#include <Guid/MemoryTypeInformation.h>
-#include <Ppi/MasterBootMode.h>
-#include <IndustryStandard/Pci22.h>
-#include <OvmfPlatforms.h>
-
-#include "Platform.h"
-#include "Cmos.h"
-
-EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
- { EfiACPIMemoryNVS, 0x004 },
- { EfiACPIReclaimMemory, 0x008 },
- { EfiReservedMemoryType, 0x004 },
- { EfiRuntimeServicesData, 0x024 },
- { EfiRuntimeServicesCode, 0x030 },
- { EfiBootServicesCode, 0x180 },
- { EfiBootServicesData, 0xF00 },
- { EfiMaxMemoryType, 0x000 }
-};
-
-
-EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
- &gEfiPeiMasterBootModePpiGuid,
- NULL
- }
-};
-
-EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
-
-BOOLEAN mS3Supported = FALSE;
-
-
-VOID
-AddIoMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- )
-{
- BuildResourceDescriptorHob (
- EFI_RESOURCE_MEMORY_MAPPED_IO,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
- MemoryBase,
- MemorySize
- );
-}
-
-VOID
-AddReservedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- )
-{
- BuildResourceDescriptorHob (
- EFI_RESOURCE_MEMORY_RESERVED,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
- MemoryBase,
- MemorySize
- );
-}
-
-VOID
-AddIoMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- )
-{
- AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
-}
-
-
-VOID
-AddMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- )
-{
- BuildResourceDescriptorHob (
- EFI_RESOURCE_SYSTEM_MEMORY,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
- MemoryBase,
- MemorySize
- );
-}
-
-
-VOID
-AddMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- )
-{
- AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
-}
-
-
-VOID
-AddUntestedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- )
-{
- BuildResourceDescriptorHob (
- EFI_RESOURCE_SYSTEM_MEMORY,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
- MemoryBase,
- MemorySize
- );
-}
-
-
-VOID
-AddUntestedMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- )
-{
- AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
-}
-
-VOID
-MemMapInitialization (
- VOID
- )
-{
- UINT32 TopOfLowRam;
-
- //
- // Create Memory Type Information HOB
- //
- BuildGuidDataHob (
- &gEfiMemoryTypeInformationGuid,
- mDefaultMemoryTypeInformation,
- sizeof(mDefaultMemoryTypeInformation)
- );
-
- //
- // Add PCI IO Port space available for PCI resource allocations.
- //
- BuildResourceDescriptorHob (
- EFI_RESOURCE_IO,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
- 0xC000,
- 0x4000
- );
-
- //
- // Video memory + Legacy BIOS region
- //
- AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
-
- if (!mXen) {
- TopOfLowRam = GetSystemMemorySizeBelow4gb ();
-
- //
- // address purpose size
- // ------------ -------- -------------------------
- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
- // 0xFC000000 gap 44 MB
- // 0xFEC01000 gap 1020 KB
- // 0xFED00400 gap 111 KB
- // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
- // 0xFED20000 gap 896 KB
- //
- AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?
- BASE_2GB : TopOfLowRam, 0xFC000000);
- DEBUG ((DEBUG_INFO, "Memroy reserved for PCI Base: %x to %x\n", TopOfLowRam < BASE_2GB ? BASE_2GB : TopOfLowRam,0xFC000000));
-// if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
-// AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
-// }
- }
-}
-
-
-VOID
-MiscInitialization (
- UINT16 mHostBridgeDevId
- )
-{
- UINTN PmCmd;
- UINTN Pmba;
- UINTN AcpiCtlReg;
- UINT8 AcpiEnBit;
-
- //
- // Build the CPU HOB with guest RAM size dependent address width and 16-bits
- // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
- // S3 resume as well, so we build it unconditionally.)
- //
- BuildCpuHob (mPhysMemAddressWidth, 32);
-
- //
- // Determine platform type and save Host Bridge DID to PCD
- //
- switch (mHostBridgeDevId) {
- case INTEL_82441_DEVICE_ID:
- PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
- Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
- AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
- break;
- case INTEL_Q35_MCH_DEVICE_ID:
- PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
- Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
- AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
- AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
- break;
- default:
- DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
- __FUNCTION__, mHostBridgeDevId));
- ASSERT (FALSE);
- return;DEBUG ((EFI_D_INFO, "Platform address width set.\n"));
- }
- PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
-
- //
- // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
- // has been configured (e.g., by Xen) and skip the setup here.
- // This matches the logic in AcpiTimerLibConstructor ().
- //
- if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
- DEBUG ((EFI_D_INFO, "Config PMBase address= %x\n", PcdGet16 (PcdAcpiPmBaseAddress)));
- //
- // The PEI phase should be exited with fully accessibe ACPI PM IO space:
- // 1. set PMBA
- //
- PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
-
- //
- // 2. set PCICMD/IOSE
- //
- PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
-
- //
- // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
- //
- PciOr8 (AcpiCtlReg, AcpiEnBit);
- } else {
- DEBUG ((EFI_D_INFO, "ACPI PM base already set= %x\n", PciRead16 (AcpiCtlReg)));
- }
-
- if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
- //
- // Set Root Complex Register Block BAR
- //
- PciWrite32 (
- POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
- ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
- );
- }
-}
-
-
-VOID
-BootModeInitialization (
- VOID
- )
-{
- EFI_STATUS Status;
-
- if (CmosRead8 (0xF) == 0xFE) {
- mBootMode = BOOT_ON_S3_RESUME;
- DEBUG ((EFI_D_INFO, "This is S3 resume\n"));
- }
- DEBUG ((EFI_D_INFO, "This is normal boot\n"));
-
- Status = PeiServicesSetBootMode (mBootMode);
- ASSERT_EFI_ERROR (Status);
-
- Status = PeiServicesInstallPpi (mPpiBootMode);
- ASSERT_EFI_ERROR (Status);
-}
-
-
-VOID
-ReserveEmuVariableNvStore (
- )
-{
- EFI_PHYSICAL_ADDRESS VariableStore;
-
- //
- // Allocate storage for NV variables early on so it will be
- // at a consistent address. Since VM memory is preserved
- // across reboots, this allows the NV variable storage to survive
- // a VM reboot.
- //
- VariableStore =
- (EFI_PHYSICAL_ADDRESS)(UINTN)
- AllocateAlignedRuntimePages (
- EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
- PcdGet32 (PcdFlashNvStorageFtwSpareSize)
- );
- DEBUG ((EFI_D_INFO,
- "Reserved variable store memory: 0x%lX; size: %dkb\n",
- VariableStore,
- (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
- ));
- PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
-}
-
-
-VOID
-DebugDumpCmos (
- VOID
- )
-{
- UINT32 Loop;
-
- DEBUG ((EFI_D_INFO, "CMOS:\n"));
-
- for (Loop = 0; Loop < 0x80; Loop++) {
- if ((Loop % 0x10) == 0) {
- DEBUG ((EFI_D_INFO, "%02x:", Loop));
- }
- DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
- if ((Loop % 0x10) == 0xf) {
- DEBUG ((EFI_D_INFO, "\n"));
- }
- }
-}
-
-
-/**
- Perform Platform PEI initialization.
-
- @param FileHandle Handle of the file being invoked.
- @param PeiServices Describes the list of possible PEI Services.
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-InitializePlatform (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- UINT16 mHostBridgeDevId;
-
- DEBUG ((EFI_D_INFO, "Platform PEIM Loaded\n"));
-
- DebugDumpCmos ();
-#if 0
- XenDetect ();
-
- if (QemuFwCfgS3Enabled ()) {
- DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
- mS3Supported = TRUE;
- }
-#endif
- BootModeInitialization ();
- DEBUG ((EFI_D_INFO, "Platform BOOT mode initiated.\n"));
- AddressWidthInitialization ();
- DEBUG ((EFI_D_INFO, "Platform address width set.\n"));
- PublishPeiMemory ();
- DEBUG ((EFI_D_INFO, "PEI memory published.\n"));
- InitializeRamRegions ();
- DEBUG ((EFI_D_INFO, "Platform RAM regions initiated.\n"));
-
-#if 0
- if (mXen) {
- DEBUG ((EFI_D_INFO, "Xen was detected\n"));
- InitializeXen ();
- }
-#endif
- //
- // Query Host Bridge DID
- //
- mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
- DEBUG ((EFI_D_INFO, "mHostBridgeDevId = %x.\n", mHostBridgeDevId));
- if (mBootMode != BOOT_ON_S3_RESUME) {
- ReserveEmuVariableNvStore ();
- PeiFvInitialization ();
- MemMapInitialization ();
- }
-
- MiscInitialization (mHostBridgeDevId);
- return EFI_SUCCESS;
-}
diff --git a/RiscVVirtPkg/Universal/PlatformPei/Platform.h b/RiscVVirtPkg/Universal/PlatformPei/Platform.h
deleted file mode 100644
index 8884c25..0000000
--- a/RiscVVirtPkg/Universal/PlatformPei/Platform.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/** @file
- Platform PEI module include file.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _PLATFORM_PEI_H_INCLUDED_
-#define _PLATFORM_PEI_H_INCLUDED_
-
-#include <IndustryStandard/E820.h>
-
-VOID
-AddIoMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- );
-
-VOID
-AddIoMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- );
-
-VOID
-AddMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- );
-
-VOID
-AddMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- );
-
-VOID
-AddUntestedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- );
-
-VOID
-AddReservedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- );
-
-VOID
-AddUntestedMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- );
-
-VOID
-AddressWidthInitialization (
- VOID
- );
-
-EFI_STATUS
-PublishPeiMemory (
- VOID
- );
-
-UINT32
-GetSystemMemorySizeBelow4gb (
- VOID
- );
-
-VOID
-InitializeRamRegions (
- VOID
- );
-
-EFI_STATUS
-PeiFvInitialization (
- VOID
- );
-
-EFI_STATUS
-InitializeXen (
- VOID
- );
-
-BOOLEAN
-XenDetect (
- VOID
- );
-
-extern BOOLEAN mXen;
-
-VOID
-XenPublishRamRegions (
- VOID
- );
-
-extern EFI_BOOT_MODE mBootMode;
-
-extern BOOLEAN mS3Supported;
-
-extern UINT8 mPhysMemAddressWidth;
-
-#endif // _PLATFORM_PEI_H_INCLUDED_
diff --git a/RiscVVirtPkg/Universal/PlatformPei/PlatformPei.inf b/RiscVVirtPkg/Universal/PlatformPei/PlatformPei.inf
deleted file mode 100644
index 3554602..0000000
--- a/RiscVVirtPkg/Universal/PlatformPei/PlatformPei.inf
+++ /dev/null
@@ -1,92 +0,0 @@
-## @file
-# Platform PEI driver
-#
-# This module provides platform specific function to detect boot mode.
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PlatformPei
- FILE_GUID = 222c386d-5abc-4fb4-b124-fbb82488acf4
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializePlatform
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
-#
-
-[Sources]
- Cmos.c
- Fv.c
- MemDetect.c
- Platform.c
- Xen.c
-
-[Packages]
- IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- UefiCpuPkg/UefiCpuPkg.dec
- RiscVVirtPkg/RiscVVirtPkg.dec
- RiscVPkg/RiscVPkg.dec
- OvmfPkg/OvmfPkg.dec
-
-[Guids]
- gEfiMemoryTypeInformationGuid
- gEfiXenInfoGuid
-
-[LibraryClasses]
- DebugLib
- HobLib
- IoLib
- PciLib
- PeiResourcePublicationLib
- PeiServicesLib
- PeiServicesTablePointerLib
- PeimEntryPoint
- #QemuFwCfgLib
- PcdLib
-
-[Pcd]
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize
- gUefiOvmfPkgTokenSpaceGuid.PcdS3AcpiReservedMemoryBase
- gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase
- gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize
- gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
- gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVDxeFvBase
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVDxeFvSize
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVSecPeiTempRamBase
- gUefiRiscVPkgTokenSpaceGuid.PcdRiscVSecPeiTempRamSize
- gUefiRiscVVirtPkgTokenSpaceGuid.PcdAcpiPmBaseAddress
-
-[Ppis]
- gEfiPeiMasterBootModePpiGuid
-
-[Depex]
- TRUE
-
diff --git a/RiscVVirtPkg/Universal/PlatformPei/Xen.c b/RiscVVirtPkg/Universal/PlatformPei/Xen.c
deleted file mode 100644
index 6fa118b..0000000
--- a/RiscVVirtPkg/Universal/PlatformPei/Xen.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/**@file
- Xen Platform PEI support
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-//
-// The package level header files this module uses
-//
-#include <PiPei.h>
-
-//
-// The Library classes this module consumes
-//
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PcdLib.h>
-#include <Guid/XenInfo.h>
-#include <IndustryStandard/E820.h>
-#include <Library/ResourcePublicationLib.h>
-#include <Library/MtrrLib.h>
-
-#include "Platform.h"
-#include "Xen.h"
-
-BOOLEAN mXen = FALSE;
-
-STATIC UINT32 mXenLeaf = 0;
-
-EFI_XEN_INFO mXenInfo;
-
-/**
- Returns E820 map provided by Xen
-
- @param Entries Pointer to E820 map
- @param Count Number of entries
-
- @return EFI_STATUS
-**/
-EFI_STATUS
-XenGetE820Map (
- EFI_E820_ENTRY64 **Entries,
- UINT32 *Count
- )
-{
- EFI_XEN_OVMF_INFO *Info =
- (EFI_XEN_OVMF_INFO *)(UINTN) OVMF_INFO_PHYSICAL_ADDRESS;
-
- if (AsciiStrCmp ((CHAR8 *) Info->Signature, "XenHVMOVMF")) {
- return EFI_NOT_FOUND;
- }
-
- ASSERT (Info->E820 < MAX_ADDRESS);
- *Entries = (EFI_E820_ENTRY64 *)(UINTN) Info->E820;
- *Count = Info->E820EntriesCount;
-
- return EFI_SUCCESS;
-}
-
-/**
- Connects to the Hypervisor.
-
- @param XenLeaf CPUID index used to connect.
-
- @return EFI_STATUS
-
-**/
-EFI_STATUS
-XenConnect (
- UINT32 XenLeaf
- )
-{
- return EFI_SUCCESS;
-}
-
-/**
- Figures out if we are running inside Xen HVM.
-
- @retval TRUE Xen was detected
- @retval FALSE Xen was not detected
-
-**/
-BOOLEAN
-XenDetect (
- VOID
- )
-{
- return FALSE;
-}
-
-
-VOID
-XenPublishRamRegions (
- VOID
- )
-{
- EFI_E820_ENTRY64 *E820Map;
- UINT32 E820EntriesCount;
- EFI_STATUS Status;
-
- if (!mXen) {
- return;
- }
-
- DEBUG ((EFI_D_INFO, "Using memory map provided by Xen\n"));
-
- //
- // Parse RAM in E820 map
- //
- Status = XenGetE820Map (&E820Map, &E820EntriesCount);
-
- ASSERT_EFI_ERROR (Status);
-
- if (E820EntriesCount > 0) {
- EFI_E820_ENTRY64 *Entry;
- UINT32 Loop;
-
- for (Loop = 0; Loop < E820EntriesCount; Loop++) {
- Entry = E820Map + Loop;
-
- //
- // Only care about RAM
- //
- if (Entry->Type != EfiAcpiAddressRangeMemory) {
- continue;
- }
-
- if (Entry->BaseAddr >= BASE_4GB) {
- AddUntestedMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length);
- } else {
- AddMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length);
- }
- }
- }
-}
-
-
-/**
- Perform Xen PEI initialization.
-
- @return EFI_SUCCESS Xen initialized successfully
- @return EFI_NOT_FOUND Not running under Xen
-
-**/
-EFI_STATUS
-InitializeXen (
- VOID
- )
-{
- if (mXenLeaf == 0) {
- return EFI_NOT_FOUND;
- }
-
- XenConnect (mXenLeaf);
-
- //
- // Reserve away HVMLOADER reserved memory [0xFC000000,0xFD000000).
- // This needs to match HVMLOADER RESERVED_MEMBASE/RESERVED_MEMSIZE.
- //
- AddReservedMemoryBaseSizeHob (0xFC000000, 0x1000000);
-
- PcdSetBool (PcdPciDisableBusEnumeration, TRUE);
-
- return EFI_SUCCESS;
-}
diff --git a/RiscVVirtPkg/Universal/PlatformPei/Xen.h b/RiscVVirtPkg/Universal/PlatformPei/Xen.h
deleted file mode 100644
index a4a37e3..0000000
--- a/RiscVVirtPkg/Universal/PlatformPei/Xen.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/** @file
- Ovmf info structure passed by Xen
-
-Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-Copyright (c) 2013, Citrix Systems UK Ltd.<BR>
-
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __XEN_H__
-#define __XEN_H__
-
-#include <PiPei.h>
-
-// Physical address of OVMF info
-#define OVMF_INFO_PHYSICAL_ADDRESS 0x00001000
-
-// This structure must match the definition on Xen side
-#pragma pack(1)
-typedef struct {
- CHAR8 Signature[14]; // XenHVMOVMF\0
- UINT8 Length; // Length of this structure
- UINT8 Checksum; // Set such that the sum over bytes 0..length == 0
- //
- // Physical address of an array of TablesCount elements.
- //
- // Each element contains the physical address of a BIOS table.
- //
- EFI_PHYSICAL_ADDRESS Tables;
- UINT32 TablesCount;
- //
- // Physical address of the E820 table, contains E820EntriesCount entries.
- //
- EFI_PHYSICAL_ADDRESS E820;
- UINT32 E820EntriesCount;
-} EFI_XEN_OVMF_INFO;
-#pragma pack()
-
-#endif /* __XEN_H__ */
diff --git a/RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadging.c b/RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadging.c
deleted file mode 100644
index a7b5de9..0000000
--- a/RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadging.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/** @file
- RISC-V logos on POST screen.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#include "RiscVBadging.h"
-
-/**
-
- Load an OEM badge image and return its data and attributes.
-
- @param This The pointer to this protocol instance.
- @param Instance The visible image instance is found.
- @param Format The format of the image. Examples: BMP, JPEG.
- @param ImageData The image data for the badge file. Currently only
- supports the .bmp file format.
- @param ImageSize The size of the image returned.
- @param Attribute The display attributes of the image returned.
- @param CoordinateX The X coordinate of the image.
- @param CoordinateY The Y coordinate of the image.
-
- @retval EFI_SUCCESS The image was fetched successfully.
- @retval EFI_NOT_FOUND The specified image could not be found.
-
-**/
-
-EFI_STATUS
-RiscvBadgingGetImage (
- IN EFI_OEM_BADGING_PROTOCOL *This,
- IN OUT UINT32 *Instance,
- OUT EFI_BADGING_FORMAT *Format,
- OUT UINT8 **ImageData,
- OUT UINTN *ImageSize,
- OUT EFI_BADGING_DISPLAY_ATTRIBUTE *Attribute,
- OUT UINTN *CoordinateX,
- OUT UINTN *CoordinateY
-)
-{
- EFI_STATUS Status;
-
- if (*Instance == 0) {
- //
- // Tiano logo
- //
- *Attribute = EfiBadgingDisplayAttributeCustomized;
- *CoordinateX = 187;
- *CoordinateY = 271;
- Status = GetSectionFromAnyFv (PcdGetPtr(PcdLogoFile), EFI_SECTION_RAW, 0, (VOID **) ImageData, ImageSize);
- if (EFI_ERROR (Status)) {
- return EFI_UNSUPPORTED;
- }
- DEBUG ((DEBUG_INFO, "Disaply Tiano logo\n"));
- } else if (*Instance == 1) {
- //
- // RISC-V logo
- //
- *Attribute = EfiBadgingDisplayAttributeCustomized;
- *CoordinateX = 420;
- *CoordinateY = 271;
- Status = GetSectionFromAnyFv (PcdGetPtr(PcdRiscVLogoFile), EFI_SECTION_RAW, 0, (VOID **) ImageData, ImageSize);
- if (EFI_ERROR (Status)) {
- return EFI_UNSUPPORTED;
- }
- DEBUG ((DEBUG_INFO, "Disaply RISC-V logo\n"));
- } else {
- return EFI_NOT_FOUND;
- }
-
- *Format = EfiBadgingFormatBMP;
- *Instance = *Instance + 1;
- return EFI_SUCCESS;
-}
-
-EFI_OEM_BADGING_PROTOCOL mRiscvBadging = {
- RiscvBadgingGetImage
-};
-
-EFI_STATUS
-EFIAPI
-RiscVBadgingEntry (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
-
- //
- // Install OEM Badging protocol.
- //
- Status = gBS->InstallMultipleProtocolInterfaces (
- &ImageHandle,
- &gEfiOEMBadgingProtocolGuid,
- &mRiscvBadging,
- NULL
- );
- ASSERT_EFI_ERROR (Status);
- return Status;
-}
diff --git a/RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadging.h b/RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadging.h
deleted file mode 100644
index 160922b..0000000
--- a/RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadging.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/** @file
- RISC-V logos on POST screen.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#ifndef _RISCV_BADGING_H_
-#define _RISCV_BADGING_H_
-
-
-#include <Uefi.h>
-#include <Protocol/DevicePath.h>
-#include <Protocol/OEMBadging.h>
-#include <Library/DebugLib.h>
-#include <Library/UefiDriverEntryPoint.h>
-#include <Library/UefiLib.h>
-#include <Library/PcdLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/DxeServicesLib.h>
-
-#endif
diff --git a/RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadgingDxe.inf b/RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadgingDxe.inf
deleted file mode 100644
index bee42bb..0000000
--- a/RiscVVirtPkg/Universal/RiscVBadgingDxe/RiscVBadgingDxe.inf
+++ /dev/null
@@ -1,54 +0,0 @@
-## @file
-# RISC-V DXE module to show logos on POST screen.
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = RiscVBadging
- FILE_GUID = D652F3FB-FADF-49B4-9C21-B45E751C5210
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = RiscVBadgingEntry
-
-[Sources.common]
- RiscVBadging.c
- RiscVBadging.h
-
-[Packages]
- MdePkg/MdePkg.dec
- IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
- RiscVVirtPkg/RiscVVirtPkg.dec
- RiscVPkg/RiscVPkg.dec
-
-[LibraryClasses]
- BaseMemoryLib
- DebugLib
- MemoryAllocationLib
- PrintLib
- UefiBootServicesTableLib
- UefiDriverEntryPoint
- UefiLib
- DxeServicesLib
-
-[Protocols]
- gEfiOEMBadgingProtocolGuid # PROTOCOL ALWAYS_PRODUCED
-
-[Pcd]
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile
- gUefiRiscVVirtPkgTokenSpaceGuid.PcdRiscVLogoFile
-
-[Depex]
- TRUE
-
diff --git a/RiscVVirtPkg/VarStore.fdf.inc b/RiscVVirtPkg/VarStore.fdf.inc
deleted file mode 100644
index 6745281..0000000
--- a/RiscVVirtPkg/VarStore.fdf.inc
+++ /dev/null
@@ -1,92 +0,0 @@
-## @file
-# FDF include file with Layout Regions that define an empty variable store.
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-# Copyright (C) 2014, Red Hat, Inc.
-# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials are licensed and made available
-# under the terms and conditions of the BSD License which accompanies this
-# distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-# IMPLIED.
-#
-##
-
-0x00000000|0x0000e000
-gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
-#
-# NV_VARIABLE_STORE
-#
-DATA = {
- ## This is the EFI_FIRMWARE_VOLUME_HEADER
- # ZeroVector []
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- # FileSystemGuid: gEfiSystemNvDataFvGuid =
- # { 0xFFF12B8D, 0x7696, 0x4C8B,
- # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
- 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
- 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
- # FvLength: 0x20000
- 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
- # Signature "_FVH" # Attributes
- 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
- # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
- 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02,
- # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block
- 0x20, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
- # Blockmap[1]: End
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is the VARIABLE_STORE_HEADER
-!if $(SECURE_BOOT_ENABLE) == TRUE
- # Signature: gEfiAuthenticatedVariableGuid =
- # { 0xaaf32c78, 0x947b, 0x439a,
- # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
- 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
- 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
-!else
- # Signature: gEfiVariableGuid =
- # { 0xddcf3616, 0x3275, 0x4164,
- # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
- 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
- 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
-!endif
- # Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
- # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdfb8
- # This can speed up the Variable Dispatch a bit.
- 0xB8, 0xDF, 0x00, 0x00,
- # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
- 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-}
-
-0x0000e000|0x00001000
-gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize
-#
-#NV_EVENT_LOG
-#
-
-0x0000f000|0x00001000
-gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
-#
-#NV_FTW_WORKING
-#
-DATA = {
- # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
- # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
- 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
- 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
- # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
- 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF,
- # WriteQueueSize: UINT64
- 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-}
-
-0x00010000|0x00010000
-gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
-#
-#NV_FTW_SPARE
-#
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 13/14]: RiscVPkg/Library: Add/Update/Remove Library instances for RISC-V platform
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
` (9 preceding siblings ...)
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 12/14]: RiscVVirtPkg: Remove RISC-V virtual package Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 14/14]: MdeModulePkg/DxeIplPeim: Abstract platform DXEIPL on " Abner Chang
2019-08-28 8:17 ` [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for " jonathan.cameron
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
RiscVCpuLib
- Add general CSR assembly functions for C source code.
RiscVDxeIplHandoffLib
RiscVDxeIplHandoffOpenSbiLib
- Provide DxeIpl platform implementation-specifc library for RISC-V platform. Two libraries are provided in this commit,
* Defualt library which simply switch stack and transfer
control to DXE core.
* Switch stack, privilege mode and then transfer control to
DXE core through RISC-V opensbi.
RiscvOpensbiLib
- EDK2 RISC-V OpenSBI library which pull in external source files under RiscVPkg/opensbi to the build process.
PeiServicesTablePointerLibOpenSbi
- Library instance of PEI Service Table for RISC-V platform based on OpenSBI.
RiscVPlatformTempMemoryInitLibNull
- NULL lib to return temporary memory information.
RiscVDxeIplHandoffOpenSbiLib
- This is the instance of platform level DXE IPL library based on RISC-V OpenSBI implementation.
RiscVExceptionLib
- Add RISC-V Supervisor Mode trap handler
RiscVTimerLib
- Due to RISC-V timer CSR is platform implementation specific, RISC-V timer library invokes platform level timer library mputo access to timer CSRs.
PeiServicesTablePointerLibScratch
- Remove this library becasue it doesn't comform with RISC-V OpenSBI implementation.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../PeiServicesTablePointerLibOpenSbi.inf | 45 ++++++++
.../PeiServicesTablePointerLibOpenSbi.uni | Bin 0 -> 2462 bytes
.../PeiServicesTablePointerOpenSbi.c | 127 +++++++++++++++++++++
.../PeiServicesTablePointerLibScratch.inf | 46 --------
.../PeiServicesTablePointerLibScratch.uni | Bin 2520 -> 0 bytes
.../PeiServicesTablePointerScratch.c | 120 -------------------
RiscVPkg/Library/RiscVCpuLib/Cpu.s | 84 +++++++++++---
.../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 47 ++++++++
.../RiscVDxeIplHandoffLib.inf | 39 +++++++
.../RiscVDxeIplHandoffOpenSbiLib.c | 108 ++++++++++++++++++
.../RiscVDxeIplHandoffOpenSbiLib.inf | 39 +++++++
.../RiscVExceptionLib/CpuExceptionHandler.s | 94 +++++++++++++++
.../CpuExceptionHandlerDxeLib.inf | 7 +-
.../RiscVExceptionLib/CpuExceptionHandlerLib.c | 44 +++----
.../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 65 +++++++++++
.../Riscv64/TempMemInit.s | 4 +-
.../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 3 +-
17 files changed, 660 insertions(+), 212 deletions(-)
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
delete mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.inf
delete mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.uni
delete mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerScratch.c
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s
create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
new file mode 100644
index 0000000..c49377b
--- /dev/null
+++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
@@ -0,0 +1,45 @@
+## @file
+# Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
+#
+# PEI Services Table Pointer Library implementation that retrieves a pointer to the
+# PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiServicesTablePointerLibOpenSbi
+ MODULE_UNI_FILE = PeiServicesTablePointerLibOpenSbi.uni
+ FILE_GUID = B4054E46-FE75-4290-B442-4836B1265D8F
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE
+
+ CONSTRUCTOR = PeiServicesTablePointerLibOpenSbiConstructor
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PeiServicesTablePointerOpenSbi.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[Pcd]
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
new file mode 100644
index 0000000000000000000000000000000000000000..e7a0c4702e4b6db9a4dd433d212f34195baf6290
GIT binary patch
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cYuyCu^?T?}$q@bb(VZq+`X^K*SF<Yl3Gf+@ZvX%Q
literal 0
HcmV?d00001
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
new file mode 100644
index 0000000..da68fca
--- /dev/null
+++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
@@ -0,0 +1,127 @@
+/** @file
+ PEI Services Table Pointer Library.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include <PiPei.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/SbiFirmwareContext.h>
+
+/**
+ Caches a pointer PEI Services Table.
+
+ Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
+ in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
+ Pre-EFI Initialization Core Interface Specification.
+
+ If PeiServicesTablePointer is NULL, then ASSERT().
+
+ @param PeiServicesTablePointer The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+ IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+ )
+{
+ struct sbi_platform *ThisSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context;
+ FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer;
+
+ DEBUG ((EFI_D_ERROR, "[OpenSBI]: Set PEI Service 0x%x at Firmware Context at 0x%x\n",
+ PeiServicesTablePointer,
+ ThisSbiPlatform->firmware_context
+ ));
+}
+
+/**
+ Retrieves the cached value of the PEI Services Table pointer.
+
+ Returns the cached value of the PEI Services Table pointer in a CPU specific manner
+ as specified in the CPU binding section of the Platform Initialization Pre-EFI
+ Initialization Core Interface Specification.
+
+ If the cached PEI Services Table pointer is NULL, then ASSERT().
+
+ @return The pointer to PeiServices.
+
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+ VOID
+ )
+{
+ struct sbi_platform *ThisSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context;
+ return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;
+}
+
+/**
+ The constructor function caches the pointer to PEI services.
+
+ The constructor function caches the pointer to PEI services.
+ It will always return EFI_SUCCESS.
+
+ @param FileHandle The handle of FFS header the loaded driver.
+ @param PeiServices The pointer to the PEI services.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesTablePointerLibOpenSbiConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ SetPeiServicesTablePointer (PeiServices);
+ return EFI_SUCCESS;
+}
+
+/**
+ Perform CPU specific actions required to migrate the PEI Services Table
+ pointer from temporary RAM to permanent RAM.
+
+ For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
+ a dedicated CPU register. This means that there is no memory storage
+ associated with storing the PEI Services Table pointer, so no additional
+ migration actions are required for Itanium or ARM CPUs.
+
+**/
+VOID
+EFIAPI
+MigratePeiServicesTablePointer (
+ VOID
+ )
+{
+ //
+ // PEI Services Table pointer is cached in the global variable. No additional
+ // migration actions are required.
+ //
+ return;
+}
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.inf b/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.inf
deleted file mode 100644
index 0b7cf65..0000000
--- a/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.inf
+++ /dev/null
@@ -1,46 +0,0 @@
-## @file
-# Instance of PEI Services Table Pointer Library using global variable for the table pointer.
-#
-# PEI Services Table Pointer Library implementation that retrieves a pointer to the
-# PEI Services Table from a global variable. Not available to modules that execute from
-# read-only memory.
-#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PeiServicesTablePointerLibScratch
- MODULE_UNI_FILE = PeiServicesTablePointerLibScratch.uni
- FILE_GUID = A25AEF27-1FA3-43CC-8870-A89D1D2079C2
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE
-
- CONSTRUCTOR = PeiServicesTablePointerLibScratchConstructor
-
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Sources]
- PeiServicesTablePointerScratch.c
-
-[Packages]
- MdePkg/MdePkg.dec
- RiscVPkg/RiscVPkg.dec
-
-[Pcd]
-
-[LibraryClasses]
- DebugLib
- RiscVCpuLib
-
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.uni b/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerLibScratch.uni
deleted file mode 100644
index 8cc751e99fff60f17030a3078e64cab3b382a90b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001
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z39~BB*u6uHDG}6Naio~)^`@TeVVhwSPa|>(-6OI*W_)f>?U}u>ZNB%3bK$6#?$aVu
z-@fpklQE#gLSZwHwQ!6z-r`=WnmHDENrNrW1lz?TrKRkuS#@Z?G(8}C*<M-I+V*;b
zraE9AJ5$P=Q-hQpJ2G`-g;s^PkB8KwlXS(tsQL->csiu@GomF<RiD^C!&|3ICsCNx
z!x&$?PuyoySI^xmp1cA{%r$Y;MHC@ZyfH|kmc>Lo=f%D%C%wk1PH@7KuwFP9ecnR1
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zxD2qVvBPQug?0I=JHuU0YK`wUK1GDYe#7>#9k5f8n|w*hdY2d#S5ZrhRiA6NeWUgx
z?26j-jKPlZYCEz6)*D1sjHYLAGZS{LDQ5>?`6z4jdW)~Je`b7-MaXqxbvH!ps-kY6
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diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerScratch.c b/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerScratch.c
deleted file mode 100644
index eccef62..0000000
--- a/RiscVPkg/Library/PeiServicesTablePointerLibScratch/PeiServicesTablePointerScratch.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/** @file
- PEI Services Table Pointer Library.
-
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#include <PiPei.h>
-#include <Library/PeiServicesTablePointerLib.h>
-#include <Library/DebugLib.h>
-#include <Library/RiscVCpuLib.h>
-
-/**
- Caches a pointer PEI Services Table.
-
- Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
- in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
- Pre-EFI Initialization Core Interface Specification.
-
- If PeiServicesTablePointer is NULL, then ASSERT().
-
- @param PeiServicesTablePointer The address of PeiServices pointer.
-**/
-VOID
-EFIAPI
-SetPeiServicesTablePointer (
- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
- )
-{
- RISCV_MACHINE_MODE_CONTEXT *Context;
-
- Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
- //DEBUG ((DEBUG_INFO, "PEI set RISC-V Machine mode context at %x, PEI Service\n", Context, PeiServicesTablePointer));
- Context->PeiService = (EFI_PHYSICAL_ADDRESS)(UINTN)PeiServicesTablePointer;
-}
-
-/**
- Retrieves the cached value of the PEI Services Table pointer.
-
- Returns the cached value of the PEI Services Table pointer in a CPU specific manner
- as specified in the CPU binding section of the Platform Initialization Pre-EFI
- Initialization Core Interface Specification.
-
- If the cached PEI Services Table pointer is NULL, then ASSERT().
-
- @return The pointer to PeiServices.
-
-**/
-CONST EFI_PEI_SERVICES **
-EFIAPI
-GetPeiServicesTablePointer (
- VOID
- )
-{
- RISCV_MACHINE_MODE_CONTEXT *Context;
- EFI_PEI_SERVICES **PeiServices;
-
- Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
- PeiServices = (EFI_PEI_SERVICES **)Context->PeiService;
- //DEBUG ((DEBUG_INFO, "PEI Get RISC-V Machine mode context at %x, PEI Service\n", Context, PeiServices));
-
- return (CONST EFI_PEI_SERVICES **)PeiServices;
-}
-
-/**
- The constructor function caches the pointer to PEI services.
-
- The constructor function caches the pointer to PEI services.
- It will always return EFI_SUCCESS.
-
- @param FileHandle The handle of FFS header the loaded driver.
- @param PeiServices The pointer to the PEI services.
-
- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
-
-**/
-EFI_STATUS
-EFIAPI
-PeiServicesTablePointerLibScratchConstructor (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- SetPeiServicesTablePointer (PeiServices);
- return EFI_SUCCESS;
-}
-
-/**
- Perform CPU specific actions required to migrate the PEI Services Table
- pointer from temporary RAM to permanent RAM.
-
- For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
- immediately preceding the Interrupt Descriptor Table (IDT) in memory.
- For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
- immediately preceding the Interrupt Descriptor Table (IDT) in memory.
- For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
- a dedicated CPU register. This means that there is no memory storage
- associated with storing the PEI Services Table pointer, so no additional
- migration actions are required for Itanium or ARM CPUs.
-
-**/
-VOID
-EFIAPI
-MigratePeiServicesTablePointer (
- VOID
- )
-{
- //
- // PEI Services Table pointer is cached in the global variable. No additional
- // migration actions are required.
- //
- return;
-}
diff --git a/RiscVPkg/Library/RiscVCpuLib/Cpu.s b/RiscVPkg/Library/RiscVCpuLib/Cpu.s
index 5dc6bc1..27fc091 100644
--- a/RiscVPkg/Library/RiscVCpuLib/Cpu.s
+++ b/RiscVPkg/Library/RiscVCpuLib/Cpu.s
@@ -2,7 +2,7 @@
//
// RISC-V CPU functions.
//
-// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
@@ -23,10 +23,16 @@
.global ASM_PFX(RiscVSetScratch)
.global ASM_PFX(RiscVGetScratch)
-.global ASM_PFX(RiscVReadMachineTimer)
-.global ASM_PFX(RiscVSetMachineTimerCmp)
.global ASM_PFX(RiscVGetMachineTrapCause)
-
+.global ASM_PFX(RiscVReadMachineIE)
+.global ASM_PFX(RiscVReadMachineIP)
+.global ASM_PFX(RiscVReadMachineStatus)
+.global ASM_PFX(RiscVWriteMachineStatus)
+.global ASM_PFX(RiscVReadMachineTvec)
+.global ASM_PFX(RiscVReadMisa)
+.global ASM_PFX(RiscVReadMVendorId)
+.global ASM_PFX(RiscVReadMArchId)
+.global ASM_PFX(RiscVReadMImplId)
//
// Set machine mode scratch.
// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
@@ -44,24 +50,72 @@ ASM_PFX (RiscVGetScratch):
ret
//
-// Read machine timer CSR.
-// @retval a0 : 32-bit machine timer.
+// Get machine trap cause CSR.
//
-ASM_PFX (RiscVReadMachineTimer):
- csrrs a0, RISCV_CSR_MACHINE_MTIME, 0
+ASM_PFX (RiscVGetMachineTrapCause):
+ csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
ret
//
-// Set machine timer compare CSR.
-// @param a0 : UINT32
+// Get machine interrupt enable
//
-ASM_PFX (RiscVSetMachineTimerCmp):
- csrrw a1, RISCV_CSR_MACHINE_MTIMECMP, a0
+ASM_PFX (RiscVReadMachineIE):
+ csrr a0, RISCV_CSR_MACHINE_MIE
ret
//
-// Get machine trap cause CSR.
+// Get machine interrupt pending
//
-ASM_PFX (RiscVGetMachineTrapCause):
- csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
+ASM_PFX (RiscVReadMachineIP):
+ csrr a0, RISCV_CSR_MACHINE_MIP
+ ret
+
+//
+// Get machine status
+//
+ASM_PFX(RiscVReadMachineStatus):
+ csrr a0, RISCV_CSR_MACHINE_MSTATUS
+ ret
+
+//
+// Set machine status
+//
+ASM_PFX(RiscVWriteMachineStatus):
+ csrw RISCV_CSR_MACHINE_MSTATUS, a0
+ ret
+
+//
+// Get machine trap vector
+//
+ASM_PFX(RiscVReadMachineTvec):
+ csrr a0, RISCV_CSR_MACHINE_MTVEC
+ ret
+
+//
+// Read machine ISA
+//
+ASM_PFX(RiscVReadMisa):
+ csrr a0, RISCV_CSR_MACHINE_MISA
+ ret
+
+//
+// Read machine vendor ID
+//
+ASM_PFX(RiscVReadMVendorId):
+ csrr a0, RISCV_CSR_MACHINE_MVENDORID
ret
+
+//
+// Read machine architecture ID
+//
+ASM_PFX(RiscVReadMArchId):
+ csrr a0, RISCV_CSR_MACHINE_MARCHID
+ ret
+
+//
+// Read machine implementation ID
+//
+ASM_PFX(RiscVReadMImplId):
+ csrr a0, RISCV_CSR_MACHINE_MIMPID
+ ret
+
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
new file mode 100644
index 0000000..309cb19
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
@@ -0,0 +1,47 @@
+/** @file
+ RISC-V platform level DXE core hand off library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+
+ //
+ // Transfer the control to the entry point of DxeCore.
+ //
+ SwitchStack (
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
+ HobList.Raw,
+ NULL,
+ TopOfStack
+ );
+}
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
new file mode 100644
index 0000000..62599ac
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
@@ -0,0 +1,39 @@
+## @file
+# Instance of RISC-V DXE IPL to DXE core handoff platform library
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RiscVPlatformDxeIplLib
+ FILE_GUID = 2A77EE71-9F55-43F9-8773-7854A5B56086
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscVDxeIplHandoffLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+
+[Pcd]
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
new file mode 100644
index 0000000..37b4d32
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
@@ -0,0 +1,108 @@
+/** @file
+ RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+
+#include <sbi/sbi.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_init.h>
+#include <sbi/riscv_encoding.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/RiscVPlatformDxeIpl.h>
+
+/**
+ RISC-V platform DXE IPL to DXE OpenSBI mdoe switch handler.
+ This function is executed in RISC-V Supervisor mode.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+RiscVDxeIplHandoffOpenSbiHandler (
+ IN UINTN HardId,
+ IN OPENSBI_SWITCH_MODE_CONTEXT *ThisSwitchContext
+ )
+{
+ DEBUG ((EFI_D_INFO, "[OpenSBI]: OpenSBI mode switch DXE IPL Handoff handler entry\n"));
+
+ SwitchStack (
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)ThisSwitchContext->DxeCoreEntryPoint,
+ ThisSwitchContext->HobList.Raw,
+ NULL,
+ ThisSwitchContext->TopOfStack
+ );
+
+ //
+ // Shold never came back.
+ //
+ __builtin_unreachable();
+}
+
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+ struct sbi_scratch *ThisScratch;
+ OPENSBI_SWITCH_MODE_CONTEXT OpenSbiSwitchModeContext;
+
+ DEBUG ((EFI_D_INFO, "[OpenSBI]: DXE IPL to DXE Core using OpenSBI\n"));
+ //
+ // Setup next address in OpenSBI scratch
+ //
+ OpenSbiSwitchModeContext.BaseOfStack = BaseOfStack;
+ OpenSbiSwitchModeContext.TopOfStack = TopOfStack;
+ OpenSbiSwitchModeContext.HobList = HobList;
+ OpenSbiSwitchModeContext.DxeCoreEntryPoint = DxeCoreEntryPoint;
+ ThisScratch = sbi_scratch_thishart_ptr ();
+ ThisScratch->next_arg1 = (unsigned long)(UINTN)&OpenSbiSwitchModeContext;
+ ThisScratch->next_addr = (unsigned long)(UINTN)RiscVDxeIplHandoffOpenSbiHandler;
+ ThisScratch->next_mode = PRV_S;
+
+ DEBUG ((EFI_D_INFO, " Base address of satck: 0x%x\n", BaseOfStack));
+ DEBUG ((EFI_D_INFO, " Top address of satck: 0x%x\n", TopOfStack));
+ DEBUG ((EFI_D_INFO, " HOB list address: 0x%x\n", &HobList));
+ DEBUG ((EFI_D_INFO, " DXE core entry pointer: 0x%x\n", DxeCoreEntryPoint));
+ DEBUG ((EFI_D_INFO, " OpenSBI Switch mode arg1: 0x%x\n", (UINTN)&OpenSbiSwitchModeContext));
+ DEBUG ((EFI_D_INFO, " OpenSBI Switch mode handler address: 0x%x\n", (UINTN)RiscVDxeIplHandoffOpenSbiHandler));
+ DEBUG ((EFI_D_INFO, " OpenSBI Switch mode to privilege 0x%x\n", PRV_S));
+ sbi_init (ThisScratch);
+}
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
new file mode 100644
index 0000000..3ddfe41
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
@@ -0,0 +1,39 @@
+## @file
+# Instance of RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RiscVPlatformDxeIplLib
+ FILE_GUID = 906A4BB9-8DE2-4CE0-A609-23818A8FF514
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscVDxeIplHandoffOpenSbiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+
+[Pcd]
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s
new file mode 100644
index 0000000..a987c9b
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s
@@ -0,0 +1,94 @@
+/** @file
+ RISC-V Processor supervisor mode trap handler
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <RiscV.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_trap.h>
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl _strap_handler
+_strap_handler:
+ addi sp, sp, -34*8
+ /* Save all general regisers except SP and T0 */
+ sd ra, 1*8(sp)
+ sd gp, 2*8(sp)
+ sd tp, 3*8(sp)
+ sd t1, 4*8(sp)
+ sd t2, 5*8(sp)
+ sd s0, 6*8(sp)
+ sd s1, 7*8(sp)
+ sd a0, 8*8(sp)
+ sd a1, 9*8(sp)
+ sd a2, 10*8(sp)
+ sd a3, 11*8(sp)
+ sd a4, 12*8(sp)
+ sd a5, 13*8(sp)
+ sd a6, 14*8(sp)
+ sd a7, 15*8(sp)
+ sd s2, 16*8(sp)
+ sd s3, 17*8(sp)
+ sd s4, 18*8(sp)
+ sd s5, 19*8(sp)
+ sd s6, 20*8(sp)
+ sd s7, 21*8(sp)
+ sd s8, 22*8(sp)
+ sd s9, 23*8(sp)
+ sd s10, 24*8(sp)
+ sd s11, 25*8(sp)
+ sd t3, 26*8(sp)
+ sd t4, 27*8(sp)
+ sd t5, 28*8(sp)
+ sd t6, 29*8(sp)
+
+ /* Call C routine */
+ call RiscVSupervisorModeTrapHandler
+
+ /* Restore all general regisers except SP and T0 */
+ ld ra, 1*8(sp)
+ ld gp, 2*8(sp)
+ ld tp, 3*8(sp)
+ ld t1, 4*8(sp)
+ ld t2, 5*8(sp)
+ ld s0, 6*8(sp)
+ ld s1, 7*8(sp)
+ ld a0, 8*8(sp)
+ ld a1, 9*8(sp)
+ ld a2, 10*8(sp)
+ ld a3, 11*8(sp)
+ ld a4, 12*8(sp)
+ ld a5, 13*8(sp)
+ ld a6, 14*8(sp)
+ ld a7, 15*8(sp)
+ ld s2, 16*8(sp)
+ ld s3, 17*8(sp)
+ ld s4, 18*8(sp)
+ ld s5, 19*8(sp)
+ ld s6, 20*8(sp)
+ ld s7, 21*8(sp)
+ ld s8, 22*8(sp)
+ ld s9, 23*8(sp)
+ ld s10, 24*8(sp)
+ ld s11, 25*8(sp)
+ ld t3, 26*8(sp)
+ ld t4, 27*8(sp)
+ ld t5, 28*8(sp)
+ ld t6, 29*8(sp)
+ addi sp, sp, 34*8
+ sret
\ No newline at end of file
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
index f9bcd01..04bdd6a 100644
--- a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
@@ -1,7 +1,7 @@
## @file
# RISC-V CPU Exception Handler Library
#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -25,9 +25,12 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = RISCV64
#
+[Sources.RISCV64]
+ CpuExceptionHandler.s
+
[Sources.common]
CpuExceptionHandlerLib.c
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
index d185ce1..e3d42b3 100644
--- a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
@@ -1,7 +1,7 @@
/** @file
RISC-V Exception Handler library implementition.
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -16,7 +16,13 @@
#include <Library/CpuExceptionHandlerLib.h>
#include <Library/DebugLib.h>
#include <Library/RiscVCpuLib.h>
+#include <sbi/sbi_types.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+
+extern void _strap_handler(void);
+EFI_CPU_INTERRUPT_HANDLER gInterruptHandlers[2];
/**
Initializes all CPU exceptions entries and provides the default exception handlers.
@@ -97,15 +103,9 @@ RegisterCpuInterruptHandler (
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
- RISCV_MACHINE_MODE_CONTEXT *Context;
- EFI_PHYSICAL_ADDRESS *InterruptHandlerPtr;
- //
- // Set machine mode interrupt handler.
- //
- Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
+
DEBUG ((DEBUG_INFO, "RegisterCpuInterruptHandler: Type:%x Handler: %x\n", InterruptType, InterruptHandler));
- InterruptHandlerPtr = &Context->MModeHandler.IntHandlerContext.SoftwareIntHandler;
- *(InterruptHandlerPtr + InterruptType) = (EFI_PHYSICAL_ADDRESS)(UINTN)InterruptHandler;
+ gInterruptHandlers[InterruptType] = InterruptHandler;
return EFI_SUCCESS;
}
/**
@@ -113,26 +113,18 @@ RegisterCpuInterruptHandler (
**/
VOID
-RiscVMachineModeTrapHandler (
+RiscVSupervisorModeTrapHandler (
VOID
)
{
- RISCV_MACHINE_MODE_CONTEXT *Context;
- EFI_PHYSICAL_ADDRESS InterruptHandlerPtr;
EFI_SYSTEM_CONTEXT RiscVSystemContext;
- Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
-
//
- // Check machine casue register.
+ // Check scasue register.
//
-
- InterruptHandlerPtr = Context->MModeHandler.IntHandlerContext.TimerIntHandler;
- ((EFI_CPU_INTERRUPT_HANDLER)InterruptHandlerPtr) (
- EXCEPT_RISCV_TIMER_INT,
- (CONST EFI_SYSTEM_CONTEXT)RiscVSystemContext
- );
-
+ if(gInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL) {
+ gInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, (CONST EFI_SYSTEM_CONTEXT)RiscVSystemContext);
+ }
}
/**
@@ -153,12 +145,10 @@ CpuExceptionHandlerLibConstructor (
IN EFI_SYSTEM_TABLE *SystemTable
)
{
- RISCV_MACHINE_MODE_CONTEXT *Context;
//
- // Set machine trap handler.
+ // Set Superviosr mode trap handler.
//
- Context = (RISCV_MACHINE_MODE_CONTEXT *)(UINTN)RiscVGetScratch ();
- Context->MachineModeTrapHandler = (EFI_PHYSICAL_ADDRESS)(UINTN)RiscVMachineModeTrapHandler;
- DEBUG((DEBUG_INFO, "RISC-V context at 0x%x, MachineModeTrapHandler = 0x%x\n", Context, Context->MachineModeTrapHandler));
+ csr_write(CSR_STVEC, _strap_handler);
+
return EFI_SUCCESS;
}
diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
new file mode 100644
index 0000000..05180da
--- /dev/null
+++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
@@ -0,0 +1,65 @@
+## @file
+# RISC-V Opensbi Library Instance.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made
+# available under the terms and conditions of the BSD License which
+# accompanies this distribution. The full text of the license may
+# be found at http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RiscVOpensbiLib
+ FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVOpensbiLib
+
+[Sources]
+ ../../opensbi/lib/sbi/riscv_asm.c
+ ../../opensbi/lib/sbi/riscv_atomic.c
+ ../../opensbi/lib/sbi/riscv_hardfp.S
+ ../../opensbi/lib/sbi/riscv_locks.c
+ ../../opensbi/lib/sbi/riscv_unpriv.c
+ ../../opensbi/lib/sbi/sbi_console.c
+ ../../opensbi/lib/sbi/sbi_ecall.c
+ ../../opensbi/lib/sbi/sbi_emulate_csr.c
+ ../../opensbi/lib/sbi/sbi_fifo.c
+ ../../opensbi/lib/sbi/sbi_hart.c
+ ../../opensbi/lib/sbi/sbi_illegal_insn.c
+ ../../opensbi/lib/sbi/sbi_init.c
+ ../../opensbi/lib/sbi/sbi_ipi.c
+ ../../opensbi/lib/sbi/sbi_misaligned_ldst.c
+ ../../opensbi/lib/sbi/sbi_scratch.c
+ ../../opensbi/lib/sbi/sbi_string.c
+ ../../opensbi/lib/sbi/sbi_system.c
+ ../../opensbi/lib/sbi/sbi_timer.c
+ ../../opensbi/lib/sbi/sbi_tlb.c
+ ../../opensbi/lib/sbi/sbi_trap.c
+ ../../opensbi/lib/utils/sys/clint.c
+ ../../opensbi/lib/utils/irqchip/plic.c
+ ../../opensbi/lib/utils/serial/sifive-uart.c
+ ../../opensbi/lib/utils/serial/uart8250.c
+ ../../opensbi/lib/utils/libfdt/fdt.c
+ ../../opensbi/lib/utils/libfdt/fdt_ro.c
+ ../../opensbi/lib/utils/libfdt/fdt_wip.c
+ ../../opensbi/lib/utils/libfdt/fdt_rw.c
+ ../../opensbi/lib/utils/libfdt/fdt_sw.c
+ ../../opensbi/lib/utils/libfdt/fdt_strerror.c
+ ../../opensbi/lib/utils/libfdt/fdt_empty_tree.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ RiscVCpuLib
+
diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s
index 61b02c3..22ff329 100644
--- a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s
+++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s
@@ -2,7 +2,7 @@
//
// RISC-V RiscVPlatformTemporaryMemInit.
//
-// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
@@ -26,4 +26,6 @@
// a1 Temporary memory size.
//
ASM_PFX(RiscVPlatformTemporaryMemInit):
+ li a0, FixedPcdGet32 (PcdRiscVSecPeiTempRamBase)
+ li a1, FixedPcdGet32 (PcdRiscVSecPeiTempRamSize)
ret
diff --git a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
index 06e4497..66e821b 100644
--- a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
@@ -1,7 +1,7 @@
## @file
# RISC-V Timer Library Instance.
#
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# This program and the accompanying materials are licensed and made
# available under the terms and conditions of the BSD License which
@@ -36,4 +36,5 @@
BaseLib
PcdLib
RiscVCpuLib
+ RiscVPlatformTimerLib
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [edk2-staging/RISC-V PATCH v1 14/14]: MdeModulePkg/DxeIplPeim: Abstract platform DXEIPL on RISC-V platform.
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
` (10 preceding siblings ...)
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 13/14]: RiscVPkg/Library: Add/Update/Remove Library instances for RISC-V platform Abner Chang
@ 2019-08-27 6:00 ` Abner Chang
2019-08-28 8:17 ` [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for " jonathan.cameron
12 siblings, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-27 6:00 UTC (permalink / raw)
To: devel; +Cc: abner.chang
Provide DxeIpl platform implementation-specifc library for RISC-V platform. Two libraries are provided in this commit,
* Defualt library which simply switch stack and transfer
control to DXE core.
* Switch stack, privilege mode and then transfer control to
DXE core through RISC-V opensbi.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 9 ++++++++-
MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 11 ++++-------
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index ea79536..b4c35e5 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -6,7 +6,7 @@
# needed to run the DXE Foundation.
#
# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -68,6 +68,9 @@
[Packages.ARM, Packages.AARCH64]
ArmPkg/ArmPkg.dec
+[Packages.RISCV64]
+ RiscVPkg/RiscVPkg.dec
+
[LibraryClasses]
PcdLib
MemoryAllocationLib
@@ -86,6 +89,10 @@
[LibraryClasses.ARM, LibraryClasses.AARCH64]
ArmLib
+[LibraryClasses.RISCV64]
+ RiscVPlatformDxeIplLib
+ RiscVOpensbiLib
+
[Ppis]
gEfiDxeIplPpiGuid ## PRODUCES
gEfiPeiDecompressPpiGuid ## PRODUCES
diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
index 2d5c7b9..934dfa5 100644
--- a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
+++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
@@ -1,7 +1,7 @@
/** @file
RISC-V specific functionality for DxeLoad.
- Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -13,6 +13,7 @@
**/
#include "DxeIpl.h"
+#include "Library/RiscVPlatformDxeIpl.h"
typedef
VOID*
@@ -70,10 +71,6 @@ HandOffToDxeCore (
//
// Transfer the control to the entry point of DxeCore.
//
- SwitchStack (
- (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
- HobList.Raw,
- NULL,
- TopOfStack
- );
+ RiscVPlatformHandOffToDxeCore (BaseOfStack, TopOfStack, DxeCoreEntryPoint, HobList);
}
+
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
` (11 preceding siblings ...)
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 14/14]: MdeModulePkg/DxeIplPeim: Abstract platform DXEIPL on " Abner Chang
@ 2019-08-28 8:17 ` jonathan.cameron
2019-08-28 8:43 ` Abner Chang
12 siblings, 1 reply; 19+ messages in thread
From: jonathan.cameron @ 2019-08-28 8:17 UTC (permalink / raw)
To: Abner Chang; +Cc: devel
Hi Abner,
Just noticed in passing that this series doesn't seem to have a 3/14?
Speaking personally it would be useful to have a cover letter with
a quick summary of the series content.
Thanks,
Jonathan
On Tue, 27 Aug 2019 14:00:19 +0800
Abner Chang <abner.chang@hpe.com> wrote:
> Elf64Convert.c
> - Relocation process to hadnle below opcodes,
> * PCRELHI20
> * PCRELLO12
> * ADD32
> * SUB32
>
> GenFvInternalLib.c
> - This atches jump instrcution at the position of first instrcution fetched by RISC-V processor after Zeroth Stage Boot Loader (ZSBL).
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> BaseTools/Source/C/GenFv/GenFvInternalLib.c | 311 ++++++++++++----------------
> BaseTools/Source/C/GenFw/Elf64Convert.c | 68 ++++++
> 2 files changed, 197 insertions(+), 182 deletions(-)
>
> diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> index 01da00c..92abb7c 100644
> --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> @@ -1956,157 +1956,6 @@ Returns:
> return EFI_UNSUPPORTED;
> }
>
> -EFI_STATUS
> -UpdateRiscvResetVectorIfNeeded (
> - MEMORY_FILE *FvImage,
> - FV_INFO *FvInfo,
> - EFI_FFS_FILE_HEADER *VtfFileImage
> - )
> -/*++
> -
> -Routine Description:
> - This parses the FV looking for SEC and patches that address into the
> - beginning of the FV header.
> -
> - For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> -
> -Arguments:
> - FvImage Memory file for the FV memory image/
> - FvInfo Information read from INF file.
> - VtfFileImage Instance of VTF file.
> -
> -Returns:
> -
> - EFI_SUCCESS Function Completed successfully.
> - EFI_ABORTED Error encountered.
> - EFI_INVALID_PARAMETER A required parameter was NULL.
> - EFI_NOT_FOUND PEI Core file not found.
> -
> ---*/
> -{
> - EFI_FFS_FILE_HEADER *PeiCoreFile;
> - EFI_FFS_FILE_HEADER *SecCoreFile;
> - EFI_STATUS Status;
> - EFI_FILE_SECTION_POINTER Pe32Section;
> - UINT32 EntryPoint;
> - UINT32 BaseOfCode;
> - UINT16 MachineType;
> - EFI_PHYSICAL_ADDRESS PeiCorePhysicalAddress;
> - EFI_PHYSICAL_ADDRESS SecCorePhysicalAddress;
> - EFI_PHYSICAL_ADDRESS TrapAddress;
> -
> - //
> - // Verify input parameters
> - //
> - if (FvImage == NULL || FvInfo == NULL) {
> - Error (NULL, 0, 3000, "Invalid", "FvImage or FvInfo is NULL");
> - return EFI_INVALID_PARAMETER;
> - }
> - //
> - // Initialize FV library
> - //
> - InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> -
> - //
> - // Find the Sec Core
> - //
> - Status = GetFileByType (EFI_FV_FILETYPE_SECURITY_CORE, 1, &SecCoreFile);
> - if (EFI_ERROR (Status) || SecCoreFile == NULL) {
> - //
> - // Maybe hardware does SEC job and we only have PEI Core?
> - //
> -
> - //
> - // Find the PEI Core. It may not exist if SEC loads DXE core directly
> - //
> - PeiCorePhysicalAddress = 0;
> - Status = GetFileByType (EFI_FV_FILETYPE_PEI_CORE, 1, &PeiCoreFile);
> - if (!EFI_ERROR(Status) && PeiCoreFile != NULL) {
> - //
> - // PEI Core found, now find PE32 or TE section
> - //
> - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_PE32, 1, &Pe32Section);
> - if (Status == EFI_NOT_FOUND) {
> - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_TE, 1, &Pe32Section);
> - }
> -
> - if (EFI_ERROR (Status)) {
> - Error (NULL, 0, 3000, "Invalid", "could not find either a PE32 or a TE section in PEI core file!");
> - return EFI_ABORTED;
> - }
> -
> - Status = GetPe32Info (
> - (VOID *) ((UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader)),
> - &EntryPoint,
> - &BaseOfCode,
> - &MachineType
> - );
> -
> - if (EFI_ERROR (Status)) {
> - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for the PEI core!");
> - return EFI_ABORTED;
> - }
> - //
> - // Physical address is FV base + offset of PE32 + offset of the entry point
> - //
> - PeiCorePhysicalAddress = FvInfo->BaseAddress;
> - PeiCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN) FvImage->FileImage;
> - PeiCorePhysicalAddress += EntryPoint;
> - DebugMsg (NULL, 0, 9, "PeiCore physical entry point address", "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
> - RiscvPatchVtf (VtfFileImage, (UINT32)PeiCorePhysicalAddress);
> - }
> - return EFI_SUCCESS;
> - }
> -
> - //
> - // Sec Core found, now find PE32 section
> - //
> - Status = GetSectionByType (SecCoreFile, EFI_SECTION_PE32, 1, &Pe32Section);
> - if (Status == EFI_NOT_FOUND) {
> - Status = GetSectionByType (SecCoreFile, EFI_SECTION_TE, 1, &Pe32Section);
> - }
> -
> - if (EFI_ERROR (Status)) {
> - Error (NULL, 0, 3000, "Invalid", "could not find a PE32 section in the SEC core file.");
> - return EFI_ABORTED;
> - }
> -
> - Status = GetPe32Info (
> - (VOID *) ((UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader)),
> - &EntryPoint,
> - &BaseOfCode,
> - &MachineType
> - );
> - if (EFI_ERROR (Status)) {
> - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for the SEC core.");
> - return EFI_ABORTED;
> - }
> -
> - if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) && (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> - //
> - // If SEC is not RISC-V we have nothing to do
> - //
> - return EFI_SUCCESS;
> - }
> -
> - //
> - // Physical address is FV base + offset of PE32 + offset of the entry point
> - //
> - SecCorePhysicalAddress = FvInfo->BaseAddress;
> - SecCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN) FvImage->FileImage;
> - SecCorePhysicalAddress += EntryPoint;
> - DebugMsg (NULL, 0, 0x14, "SecCore physical entry point address", "Address = 0x%llX", (unsigned long long) SecCorePhysicalAddress);
> - RiscvPatchVtf (VtfFileImage, (UINT32)SecCorePhysicalAddress);
> - //
> - // Update RISC-V trap handler.
> - //
> - TrapAddress = (UINTN) Pe32Section.Pe32Section + GetSectionHeaderLength(Pe32Section.CommonHeader) + EntryPoint;
> - TrapAddress -= 40;
> - RiscvPatchVtfTrapHandler (VtfFileImage, TrapAddress);
> -
> - DebugMsg (NULL, 0, 9, "Update Reset vector in FV Header", NULL);
> - return EFI_SUCCESS;
> -}
>
> EFI_STATUS
> FindCorePeSection(
> @@ -2581,6 +2430,106 @@ Returns:
> }
>
> EFI_STATUS
> +UpdateRiscvResetVectorIfNeeded (
> + MEMORY_FILE *FvImage,
> + FV_INFO *FvInfo
> + )
> +/*++
> +
> +Routine Description:
> + This parses the FV looking for SEC and patches that address into the
> + beginning of the FV header.
> +
> + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> +
> +Arguments:
> + FvImage Memory file for the FV memory image/
> + FvInfo Information read from INF file.
> +
> +Returns:
> +
> + EFI_SUCCESS Function Completed successfully.
> + EFI_ABORTED Error encountered.
> + EFI_INVALID_PARAMETER A required parameter was NULL.
> + EFI_NOT_FOUND PEI Core file not found.
> +
> +--*/
> +{
> + EFI_STATUS Status;
> + UINT16 MachineType;
> + EFI_FILE_SECTION_POINTER SecPe32;
> + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
> +
> + UINT32 bSecCore;
> + UINT32 tmp;
> +
> +
> + //
> + // Verify input parameters
> + //
> + if (FvImage == NULL || FvInfo == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> + //
> + // Initialize FV library
> + //
> + InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> +
> + //
> + // Find the Sec Core
> + //
> + Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
> + if(EFI_ERROR(Status)) {
> + printf("skip because Secutiry Core not found\n");
> + return EFI_SUCCESS;
> + }
> +
> + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
> +
> + Status = GetCoreMachineType(SecPe32, &MachineType);
> + if(EFI_ERROR(Status)) {
> + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type for SEC core.");
> + return EFI_ABORTED;
> + }
> +
> + if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) && (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because Machine type is not RiscV.");
> + return EFI_ABORTED;
> + }
> +
> + Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe32, &SecCoreEntryAddress);
> + if(EFI_ERROR(Status)) {
> + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point address for SEC Core.");
> + return EFI_ABORTED;
> + }
> +
> + VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned long long) SecCoreEntryAddress);
> + VerboseMsg("BaseAddress = 0x%llX", (unsigned long long) FvInfo->BaseAddress);
> + bSecCore = (SecCoreEntryAddress - FvInfo->BaseAddress);
> + VerboseMsg("offset = 0x%llX", bSecCore);
> +
> + if(bSecCore > 0x0fffff) {
> + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of start of the FV");
> + return EFI_ABORTED;
> + }
> +
> + tmp = bSecCore;
> + bSecCore = 0;
> + //J-type
> + bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
> + bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
> + bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
> + bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
> + bSecCore |= 0x6F; //JAL opcode
> +
> + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +
> +EFI_STATUS
> GetPe32Info (
> IN UINT8 *Pe32,
> OUT UINT32 *EntryPoint,
> @@ -3037,7 +2986,6 @@ Returns:
> FvHeader->Checksum = 0;
> FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
> }
> -
> //
> // Add files to FV
> //
> @@ -3069,39 +3017,22 @@ Returns:
> goto Finish;
> }
>
> - if (mRiscV) {
> + if (!mArm && !mRiscV) {
> //
> - // Update RISCV reset vector.
> + // Update reset vector (SALE_ENTRY for IPF)
> + // Now for IA32 and IA64 platform, the fv which has bsf file must have the
> + // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to update the
> + // reset vector. If the PEI Core is found, the VTF file will probably get
> + // corrupted by updating the entry point.
> //
> - DebugMsg (NULL, 0, INFO_LOG_LEVEL, "Update RISCV reset vector", NULL);
> - Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile, &mFvDataInfo, VtfFileImage);
> - if (EFI_ERROR (Status)) {
> - Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for RISC-V.");
> + if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) == FV_IMAGES_TOP_ADDRESS) {
> + Status = UpdateResetVector (&FvImageMemoryFile, &mFvDataInfo, VtfFileImage);
> + if (EFI_ERROR(Status)) {
> + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector.");
> goto Finish;
> - }
> - //
> - // Update Checksum for FvHeader
> - //
> - FvHeader->Checksum = 0;
> - FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
> - } else {
> - if (!mArm) {
> - //
> - // Update reset vector (SALE_ENTRY for IPF)
> - // Now for IA32 and IA64 platform, the fv which has bsf file must have the
> - // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to update the
> - // reset vector. If the PEI Core is found, the VTF file will probably get
> - // corrupted by updating the entry point.
> - //
> - if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) == FV_IMAGES_TOP_ADDRESS) {
> - Status = UpdateResetVector (&FvImageMemoryFile, &mFvDataInfo, VtfFileImage);
> - if (EFI_ERROR(Status)) {
> - Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector.");
> - goto Finish;
> - }
> - DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> - }
> }
> + DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> + }
> }
> }
>
> @@ -3119,6 +3050,22 @@ Returns:
> FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
> }
>
> + if (mRiscV) {
> + //
> + // Update RISCV reset vector.
> + //
> + Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile, &mFvDataInfo);
> + if (EFI_ERROR (Status)) {
> + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for RISC-V.");
> + goto Finish;
> + }
> + //
> + // Update Checksum for FvHeader
> + //
> + FvHeader->Checksum = 0;
> + FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
> + }
> +
> //
> // Update FV Alignment attribute to the largest alignment of all the FFS files in the FV
> //
> @@ -3853,7 +3800,7 @@ Returns:
> ImageContext.DestinationAddress = NewPe32BaseAddress;
> Status = PeCoffLoaderRelocateImage (&ImageContext);
> if (EFI_ERROR (Status)) {
> - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of %s", FileName);
> + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of %s Status=%d", FileName, Status);
> free ((VOID *) MemoryImagePointer);
> return Status;
> }
> diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
> index 4857485..77b4d53 100644
> --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> @@ -946,8 +946,60 @@ WriteSections64 (
> RiscvSymSecIndex = 0;
> break;
>
> + case R_RISCV_PCREL_HI20:
> + RiscvHi20Targ = Targ;
> + RiscvHi20Sym = SymShdr;
> + RiscvSymSecIndex = Sym->st_shndx;
> +
> + Value = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> + printf("PCREL_HI20 Sym:[%s] value:0x%x SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
> + break;
> + case R_RISCV_PCREL_LO12_I:
> + if (RiscvHi20Targ != NULL && RiscvHi20Sym != NULL && RiscvSymSecIndex != 0) {
> + int i;
> + Value2 = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> + if(Value & (RISCV_IMM_REACH/2)) {
> + Value |= ~(RISCV_IMM_REACH-1);
> + }
> + printf("PCREL_LO12_I Sym:[%s] value:0x%x SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
> + Value = Value - RiscvHi20Sym->sh_addr + mCoffSectionsOffset[RiscvSymSecIndex];
> + if(-2048 > (INT32)Value) {
> + i = (-Value / 4096);
> + //Error (NULL, 0, 3000, "Invalid", "WriteSections64(): PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> + printf("WriteSections64(): PCREL_LO12_I relocation out of range. Value:%d Value2:%d i=%d\n", Value, Value2, i);
> + Value2 -= i;
> + Value += 4096 * i;
> + if(-2048 > (INT32)Value) {
> + Value2 -= 1;
> + Value += 4096;
> + }
> + }
> + else if( 2047 < (INT32)Value) {
> + i = (Value / 4096);
> + //Error (NULL, 0, 3000, "Invalid", "WriteSections64(): PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> + printf("WriteSections64(): PCREL_LO12_I relocation out of range. Value:%d Value2:%d i=%d\n", Value, Value2, i);
> + Value2 += i;
> + Value -= 4096 * i;
> + if(2047 < (INT32)Value) {
> + Value2 += 1;
> + Value -= 4096;
> + }
> + }
> +
> + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
> + *(UINT32 *)RiscvHi20Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)RiscvHi20Targ, 0, 12));
> + printf("PCREL_LO12_I Sym:[%s] relocated value:0x%x(%d) value2:0x%x(%d) SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym), Value, Value, Value2, Value2, SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
> + }
> + RiscvHi20Sym = NULL;
> + RiscvHi20Targ = NULL;
> + RiscvSymSecIndex = 0;
> + break;
> +
> case R_RISCV_ADD64:
> case R_RISCV_SUB64:
> + case R_RISCV_ADD32:
> + case R_RISCV_SUB32:
> case R_RISCV_BRANCH:
> case R_RISCV_JAL:
> case R_RISCV_GPREL_I:
> @@ -1120,6 +1172,20 @@ WriteRelocations64 (
> EFI_IMAGE_REL_BASED_ABSOLUTE);
> break;
>
> + case R_RISCV_ADD32:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_ABSOLUTE);
> + break;
> +
> + case R_RISCV_SUB32:
> + CoffAddFixup(
> + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> + + (Rel->r_offset - SecShdr->sh_addr)),
> + EFI_IMAGE_REL_BASED_ABSOLUTE);
> + break;
> +
> case R_RISCV_BRANCH:
> CoffAddFixup(
> (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> @@ -1145,6 +1211,8 @@ WriteRelocations64 (
> case R_RISCV_SET8:
> case R_RISCV_SET16:
> case R_RISCV_SET32:
> + case R_RISCV_PCREL_HI20:
> + case R_RISCV_PCREL_LO12_I:
> break;
>
> default:
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform
2019-08-28 8:17 ` [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for " jonathan.cameron
@ 2019-08-28 8:43 ` Abner Chang
2019-08-28 8:59 ` Jonathan Cameron
0 siblings, 1 reply; 19+ messages in thread
From: Abner Chang @ 2019-08-28 8:43 UTC (permalink / raw)
To: Jonathan Cameron; +Cc: devel@edk2.groups.io
Thanks Jonathan, the cover letter and 3/14 patch were just sent.
Abner
> -----Original Message-----
> From: Jonathan Cameron [mailto:jonathan.cameron@huawei.com]
> Sent: Wednesday, August 28, 2019 4:18 PM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools:
> Update EDK2 build tool for RISC-V platform
>
> Hi Abner,
>
> Just noticed in passing that this series doesn't seem to have a 3/14?
>
> Speaking personally it would be useful to have a cover letter with a quick
> summary of the series content.
>
> Thanks,
>
> Jonathan
>
> On Tue, 27 Aug 2019 14:00:19 +0800
> Abner Chang <abner.chang@hpe.com> wrote:
>
> > Elf64Convert.c
> > - Relocation process to hadnle below opcodes,
> > * PCRELHI20
> > * PCRELLO12
> > * ADD32
> > * SUB32
> >
> > GenFvInternalLib.c
> > - This atches jump instrcution at the position of first instrcution fetched by
> RISC-V processor after Zeroth Stage Boot Loader (ZSBL).
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > ---
> > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 311 ++++++++++++------
> ----------
> > BaseTools/Source/C/GenFw/Elf64Convert.c | 68 ++++++
> > 2 files changed, 197 insertions(+), 182 deletions(-)
> >
> > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > index 01da00c..92abb7c 100644
> > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > @@ -1956,157 +1956,6 @@ Returns:
> > return EFI_UNSUPPORTED;
> > }
> >
> > -EFI_STATUS
> > -UpdateRiscvResetVectorIfNeeded (
> > - MEMORY_FILE *FvImage,
> > - FV_INFO *FvInfo,
> > - EFI_FFS_FILE_HEADER *VtfFileImage
> > - )
> > -/*++
> > -
> > -Routine Description:
> > - This parses the FV looking for SEC and patches that address into
> > the
> > - beginning of the FV header.
> > -
> > - For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > -
> > -Arguments:
> > - FvImage Memory file for the FV memory image/
> > - FvInfo Information read from INF file.
> > - VtfFileImage Instance of VTF file.
> > -
> > -Returns:
> > -
> > - EFI_SUCCESS Function Completed successfully.
> > - EFI_ABORTED Error encountered.
> > - EFI_INVALID_PARAMETER A required parameter was NULL.
> > - EFI_NOT_FOUND PEI Core file not found.
> > -
> > ---*/
> > -{
> > - EFI_FFS_FILE_HEADER *PeiCoreFile;
> > - EFI_FFS_FILE_HEADER *SecCoreFile;
> > - EFI_STATUS Status;
> > - EFI_FILE_SECTION_POINTER Pe32Section;
> > - UINT32 EntryPoint;
> > - UINT32 BaseOfCode;
> > - UINT16 MachineType;
> > - EFI_PHYSICAL_ADDRESS PeiCorePhysicalAddress;
> > - EFI_PHYSICAL_ADDRESS SecCorePhysicalAddress;
> > - EFI_PHYSICAL_ADDRESS TrapAddress;
> > -
> > - //
> > - // Verify input parameters
> > - //
> > - if (FvImage == NULL || FvInfo == NULL) {
> > - Error (NULL, 0, 3000, "Invalid", "FvImage or FvInfo is NULL");
> > - return EFI_INVALID_PARAMETER;
> > - }
> > - //
> > - // Initialize FV library
> > - //
> > - InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> > -
> > - //
> > - // Find the Sec Core
> > - //
> > - Status = GetFileByType (EFI_FV_FILETYPE_SECURITY_CORE, 1,
> > &SecCoreFile);
> > - if (EFI_ERROR (Status) || SecCoreFile == NULL) {
> > - //
> > - // Maybe hardware does SEC job and we only have PEI Core?
> > - //
> > -
> > - //
> > - // Find the PEI Core. It may not exist if SEC loads DXE core directly
> > - //
> > - PeiCorePhysicalAddress = 0;
> > - Status = GetFileByType (EFI_FV_FILETYPE_PEI_CORE, 1, &PeiCoreFile);
> > - if (!EFI_ERROR(Status) && PeiCoreFile != NULL) {
> > - //
> > - // PEI Core found, now find PE32 or TE section
> > - //
> > - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_PE32, 1,
> &Pe32Section);
> > - if (Status == EFI_NOT_FOUND) {
> > - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_TE, 1,
> &Pe32Section);
> > - }
> > -
> > - if (EFI_ERROR (Status)) {
> > - Error (NULL, 0, 3000, "Invalid", "could not find either a PE32 or a TE
> section in PEI core file!");
> > - return EFI_ABORTED;
> > - }
> > -
> > - Status = GetPe32Info (
> > - (VOID *) ((UINTN) Pe32Section.Pe32Section +
> GetSectionHeaderLength(Pe32Section.CommonHeader)),
> > - &EntryPoint,
> > - &BaseOfCode,
> > - &MachineType
> > - );
> > -
> > - if (EFI_ERROR (Status)) {
> > - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for
> the PEI core!");
> > - return EFI_ABORTED;
> > - }
> > - //
> > - // Physical address is FV base + offset of PE32 + offset of the entry
> point
> > - //
> > - PeiCorePhysicalAddress = FvInfo->BaseAddress;
> > - PeiCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section +
> GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN) FvImage-
> >FileImage;
> > - PeiCorePhysicalAddress += EntryPoint;
> > - DebugMsg (NULL, 0, 9, "PeiCore physical entry point address",
> "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
> > - RiscvPatchVtf (VtfFileImage, (UINT32)PeiCorePhysicalAddress);
> > - }
> > - return EFI_SUCCESS;
> > - }
> > -
> > - //
> > - // Sec Core found, now find PE32 section
> > - //
> > - Status = GetSectionByType (SecCoreFile, EFI_SECTION_PE32, 1,
> > &Pe32Section);
> > - if (Status == EFI_NOT_FOUND) {
> > - Status = GetSectionByType (SecCoreFile, EFI_SECTION_TE, 1,
> &Pe32Section);
> > - }
> > -
> > - if (EFI_ERROR (Status)) {
> > - Error (NULL, 0, 3000, "Invalid", "could not find a PE32 section in the SEC
> core file.");
> > - return EFI_ABORTED;
> > - }
> > -
> > - Status = GetPe32Info (
> > - (VOID *) ((UINTN) Pe32Section.Pe32Section +
> GetSectionHeaderLength(Pe32Section.CommonHeader)),
> > - &EntryPoint,
> > - &BaseOfCode,
> > - &MachineType
> > - );
> > - if (EFI_ERROR (Status)) {
> > - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for
> the SEC core.");
> > - return EFI_ABORTED;
> > - }
> > -
> > - if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) &&
> (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > - //
> > - // If SEC is not RISC-V we have nothing to do
> > - //
> > - return EFI_SUCCESS;
> > - }
> > -
> > - //
> > - // Physical address is FV base + offset of PE32 + offset of the
> > entry point
> > - //
> > - SecCorePhysicalAddress = FvInfo->BaseAddress;
> > - SecCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section +
> > GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN)
> > FvImage->FileImage;
> > - SecCorePhysicalAddress += EntryPoint;
> > - DebugMsg (NULL, 0, 0x14, "SecCore physical entry point address",
> > "Address = 0x%llX", (unsigned long long) SecCorePhysicalAddress);
> > - RiscvPatchVtf (VtfFileImage, (UINT32)SecCorePhysicalAddress);
> > - //
> > - // Update RISC-V trap handler.
> > - //
> > - TrapAddress = (UINTN) Pe32Section.Pe32Section +
> > GetSectionHeaderLength(Pe32Section.CommonHeader) + EntryPoint;
> > - TrapAddress -= 40;
> > - RiscvPatchVtfTrapHandler (VtfFileImage, TrapAddress);
> > -
> > - DebugMsg (NULL, 0, 9, "Update Reset vector in FV Header", NULL);
> > - return EFI_SUCCESS;
> > -}
> >
> > EFI_STATUS
> > FindCorePeSection(
> > @@ -2581,6 +2430,106 @@ Returns:
> > }
> >
> > EFI_STATUS
> > +UpdateRiscvResetVectorIfNeeded (
> > + MEMORY_FILE *FvImage,
> > + FV_INFO *FvInfo
> > + )
> > +/*++
> > +
> > +Routine Description:
> > + This parses the FV looking for SEC and patches that address into
> > +the
> > + beginning of the FV header.
> > +
> > + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > +
> > +Arguments:
> > + FvImage Memory file for the FV memory image/
> > + FvInfo Information read from INF file.
> > +
> > +Returns:
> > +
> > + EFI_SUCCESS Function Completed successfully.
> > + EFI_ABORTED Error encountered.
> > + EFI_INVALID_PARAMETER A required parameter was NULL.
> > + EFI_NOT_FOUND PEI Core file not found.
> > +
> > +--*/
> > +{
> > + EFI_STATUS Status;
> > + UINT16 MachineType;
> > + EFI_FILE_SECTION_POINTER SecPe32;
> > + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
> > +
> > + UINT32 bSecCore;
> > + UINT32 tmp;
> > +
> > +
> > + //
> > + // Verify input parameters
> > + //
> > + if (FvImage == NULL || FvInfo == NULL) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > + //
> > + // Initialize FV library
> > + //
> > + InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> > +
> > + //
> > + // Find the Sec Core
> > + //
> > + Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size,
> > + EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
> > + if(EFI_ERROR(Status)) {
> > + printf("skip because Secutiry Core not found\n");
> > + return EFI_SUCCESS;
> > + }
> > +
> > + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
> > +
> > + Status = GetCoreMachineType(SecPe32, &MachineType);
> > + if(EFI_ERROR(Status)) {
> > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type for
> SEC core.");
> > + return EFI_ABORTED;
> > + }
> > +
> > + if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) &&
> (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because
> Machine type is not RiscV.");
> > + return EFI_ABORTED;
> > + }
> > +
> > + Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo,
> > + SecPe32, &SecCoreEntryAddress);
> > + if(EFI_ERROR(Status)) {
> > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point
> address for SEC Core.");
> > + return EFI_ABORTED;
> > + }
> > +
> > + VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned long
> > + long) SecCoreEntryAddress); VerboseMsg("BaseAddress = 0x%llX",
> > + (unsigned long long) FvInfo->BaseAddress); bSecCore =
> > + (SecCoreEntryAddress - FvInfo->BaseAddress); VerboseMsg("offset =
> > + 0x%llX", bSecCore);
> > +
> > + if(bSecCore > 0x0fffff) {
> > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of
> start of the FV");
> > + return EFI_ABORTED;
> > + }
> > +
> > + tmp = bSecCore;
> > + bSecCore = 0;
> > + //J-type
> > + bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
> > + bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
> > + bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
> > + bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
> > + bSecCore |= 0x6F; //JAL opcode
> > +
> > + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +
> > +
> > +EFI_STATUS
> > GetPe32Info (
> > IN UINT8 *Pe32,
> > OUT UINT32 *EntryPoint,
> > @@ -3037,7 +2986,6 @@ Returns:
> > FvHeader->Checksum = 0;
> > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader,
> FvHeader->HeaderLength / sizeof (UINT16));
> > }
> > -
> > //
> > // Add files to FV
> > //
> > @@ -3069,39 +3017,22 @@ Returns:
> > goto Finish;
> > }
> >
> > - if (mRiscV) {
> > + if (!mArm && !mRiscV) {
> > //
> > - // Update RISCV reset vector.
> > + // Update reset vector (SALE_ENTRY for IPF)
> > + // Now for IA32 and IA64 platform, the fv which has bsf file must have
> the
> > + // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to update
> the
> > + // reset vector. If the PEI Core is found, the VTF file will probably get
> > + // corrupted by updating the entry point.
> > //
> > - DebugMsg (NULL, 0, INFO_LOG_LEVEL, "Update RISCV reset vector",
> NULL);
> > - Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile,
> &mFvDataInfo, VtfFileImage);
> > - if (EFI_ERROR (Status)) {
> > - Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for
> RISC-V.");
> > + if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) ==
> FV_IMAGES_TOP_ADDRESS) {
> > + Status = UpdateResetVector (&FvImageMemoryFile, &mFvDataInfo,
> VtfFileImage);
> > + if (EFI_ERROR(Status)) {
> > + Error (NULL, 0, 3000, "Invalid", "Could not update the
> > + reset vector.");
> > goto Finish;
> > - }
> > - //
> > - // Update Checksum for FvHeader
> > - //
> > - FvHeader->Checksum = 0;
> > - FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader,
> FvHeader->HeaderLength / sizeof (UINT16));
> > - } else {
> > - if (!mArm) {
> > - //
> > - // Update reset vector (SALE_ENTRY for IPF)
> > - // Now for IA32 and IA64 platform, the fv which has bsf file must have
> the
> > - // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to update
> the
> > - // reset vector. If the PEI Core is found, the VTF file will probably get
> > - // corrupted by updating the entry point.
> > - //
> > - if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) ==
> FV_IMAGES_TOP_ADDRESS) {
> > - Status = UpdateResetVector (&FvImageMemoryFile, &mFvDataInfo,
> VtfFileImage);
> > - if (EFI_ERROR(Status)) {
> > - Error (NULL, 0, 3000, "Invalid", "Could not update the reset
> vector.");
> > - goto Finish;
> > - }
> > - DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> > - }
> > }
> > + DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> > + }
> > }
> > }
> >
> > @@ -3119,6 +3050,22 @@ Returns:
> > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader,
> FvHeader->HeaderLength / sizeof (UINT16));
> > }
> >
> > + if (mRiscV) {
> > + //
> > + // Update RISCV reset vector.
> > + //
> > + Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile,
> &mFvDataInfo);
> > + if (EFI_ERROR (Status)) {
> > + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for
> RISC-V.");
> > + goto Finish;
> > + }
> > + //
> > + // Update Checksum for FvHeader
> > + //
> > + FvHeader->Checksum = 0;
> > + FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader,
> > + FvHeader->HeaderLength / sizeof (UINT16)); }
> > +
> > //
> > // Update FV Alignment attribute to the largest alignment of all the FFS
> files in the FV
> > //
> > @@ -3853,7 +3800,7 @@ Returns:
> > ImageContext.DestinationAddress = NewPe32BaseAddress;
> > Status = PeCoffLoaderRelocateImage (&ImageContext);
> > if (EFI_ERROR (Status)) {
> > - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of
> %s", FileName);
> > + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed
> > + on rebase of %s Status=%d", FileName, Status);
> > free ((VOID *) MemoryImagePointer);
> > return Status;
> > }
> > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > index 4857485..77b4d53 100644
> > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > @@ -946,8 +946,60 @@ WriteSections64 (
> > RiscvSymSecIndex = 0;
> > break;
> >
> > + case R_RISCV_PCREL_HI20:
> > + RiscvHi20Targ = Targ;
> > + RiscvHi20Sym = SymShdr;
> > + RiscvSymSecIndex = Sym->st_shndx;
> > +
> > + Value = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> > + printf("PCREL_HI20 Sym:[%s] value:0x%x SymShdr->sh_addr:0x%lx
> mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr->sh_addr,
> mCoffSectionsOffset[Sym->st_shndx]);
> > + break;
> > + case R_RISCV_PCREL_LO12_I:
> > + if (RiscvHi20Targ != NULL && RiscvHi20Sym != NULL &&
> RiscvSymSecIndex != 0) {
> > + int i;
> > + Value2 = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> > + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> > + if(Value & (RISCV_IMM_REACH/2)) {
> > + Value |= ~(RISCV_IMM_REACH-1);
> > + }
> > + printf("PCREL_LO12_I Sym:[%s] value:0x%x SymShdr-
> >sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym), Value,
> SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
> > + Value = Value - RiscvHi20Sym->sh_addr +
> mCoffSectionsOffset[RiscvSymSecIndex];
> > + if(-2048 > (INT32)Value) {
> > + i = (-Value / 4096);
> > + //Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> > + printf("WriteSections64(): PCREL_LO12_I relocation out of range.
> Value:%d Value2:%d i=%d\n", Value, Value2, i);
> > + Value2 -= i;
> > + Value += 4096 * i;
> > + if(-2048 > (INT32)Value) {
> > + Value2 -= 1;
> > + Value += 4096;
> > + }
> > + }
> > + else if( 2047 < (INT32)Value) {
> > + i = (Value / 4096);
> > + //Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> > + printf("WriteSections64(): PCREL_LO12_I relocation out of range.
> Value:%d Value2:%d i=%d\n", Value, Value2, i);
> > + Value2 += i;
> > + Value -= 4096 * i;
> > + if(2047 < (INT32)Value) {
> > + Value2 += 1;
> > + Value -= 4096;
> > + }
> > + }
> > +
> > + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) |
> (RV_X(*(UINT32*)Targ, 0, 20));
> > + *(UINT32 *)RiscvHi20Targ = (RV_X(Value2, 0, 20)<<12) |
> (RV_X(*(UINT32 *)RiscvHi20Targ, 0, 12));
> > + printf("PCREL_LO12_I Sym:[%s] relocated value:0x%x(%d)
> value2:0x%x(%d) SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n",
> GetSymName(Sym), Value, Value, Value2, Value2, SymShdr->sh_addr,
> mCoffSectionsOffset[Sym->st_shndx]);
> > + }
> > + RiscvHi20Sym = NULL;
> > + RiscvHi20Targ = NULL;
> > + RiscvSymSecIndex = 0;
> > + break;
> > +
> > case R_RISCV_ADD64:
> > case R_RISCV_SUB64:
> > + case R_RISCV_ADD32:
> > + case R_RISCV_SUB32:
> > case R_RISCV_BRANCH:
> > case R_RISCV_JAL:
> > case R_RISCV_GPREL_I:
> > @@ -1120,6 +1172,20 @@ WriteRelocations64 (
> > EFI_IMAGE_REL_BASED_ABSOLUTE);
> > break;
> >
> > + case R_RISCV_ADD32:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > + break;
> > +
> > + case R_RISCV_SUB32:
> > + CoffAddFixup(
> > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > + + (Rel->r_offset - SecShdr->sh_addr)),
> > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > + break;
> > +
> > case R_RISCV_BRANCH:
> > CoffAddFixup(
> > (UINT32) ((UINT64)
> > mCoffSectionsOffset[RelShdr->sh_info]
> > @@ -1145,6 +1211,8 @@ WriteRelocations64 (
> > case R_RISCV_SET8:
> > case R_RISCV_SET16:
> > case R_RISCV_SET32:
> > + case R_RISCV_PCREL_HI20:
> > + case R_RISCV_PCREL_LO12_I:
> > break;
> >
> > default:
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform
2019-08-28 8:43 ` Abner Chang
@ 2019-08-28 8:59 ` Jonathan Cameron
2019-08-28 9:08 ` Abner Chang
[not found] ` <15BF0B00F4581767.2982@groups.io>
0 siblings, 2 replies; 19+ messages in thread
From: Jonathan Cameron @ 2019-08-28 8:59 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist); +Cc: devel@edk2.groups.io
On Wed, 28 Aug 2019 08:43:10 +0000
"Chang, Abner (HPS SW/FW Technologist)" <abner.chang@hpe.com> wrote:
> Thanks Jonathan, the cover letter and 3/14 patch were just sent.
Great. So am I right in thinking these apply to:
https://github.com/tianocore/edk2-staging/tree/RISC-V ?
Any plans to rebase that tree as it seems to be a few years old now?
Thanks,
Jonathan
>
> Abner
>
> > -----Original Message-----
> > From: Jonathan Cameron [mailto:jonathan.cameron@huawei.com]
> > Sent: Wednesday, August 28, 2019 4:18 PM
> > To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> > Cc: devel@edk2.groups.io
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools:
> > Update EDK2 build tool for RISC-V platform
> >
> > Hi Abner,
> >
> > Just noticed in passing that this series doesn't seem to have a 3/14?
> >
> > Speaking personally it would be useful to have a cover letter with a quick
> > summary of the series content.
> >
> > Thanks,
> >
> > Jonathan
> >
> > On Tue, 27 Aug 2019 14:00:19 +0800
> > Abner Chang <abner.chang@hpe.com> wrote:
> >
> > > Elf64Convert.c
> > > - Relocation process to hadnle below opcodes,
> > > * PCRELHI20
> > > * PCRELLO12
> > > * ADD32
> > > * SUB32
> > >
> > > GenFvInternalLib.c
> > > - This atches jump instrcution at the position of first instrcution fetched by
> > RISC-V processor after Zeroth Stage Boot Loader (ZSBL).
> > >
> > > Contributed-under: TianoCore Contribution Agreement 1.0
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > ---
> > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 311 ++++++++++++------
> > ----------
> > > BaseTools/Source/C/GenFw/Elf64Convert.c | 68 ++++++
> > > 2 files changed, 197 insertions(+), 182 deletions(-)
> > >
> > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > index 01da00c..92abb7c 100644
> > > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > @@ -1956,157 +1956,6 @@ Returns:
> > > return EFI_UNSUPPORTED;
> > > }
> > >
> > > -EFI_STATUS
> > > -UpdateRiscvResetVectorIfNeeded (
> > > - MEMORY_FILE *FvImage,
> > > - FV_INFO *FvInfo,
> > > - EFI_FFS_FILE_HEADER *VtfFileImage
> > > - )
> > > -/*++
> > > -
> > > -Routine Description:
> > > - This parses the FV looking for SEC and patches that address into
> > > the
> > > - beginning of the FV header.
> > > -
> > > - For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > > -
> > > -Arguments:
> > > - FvImage Memory file for the FV memory image/
> > > - FvInfo Information read from INF file.
> > > - VtfFileImage Instance of VTF file.
> > > -
> > > -Returns:
> > > -
> > > - EFI_SUCCESS Function Completed successfully.
> > > - EFI_ABORTED Error encountered.
> > > - EFI_INVALID_PARAMETER A required parameter was NULL.
> > > - EFI_NOT_FOUND PEI Core file not found.
> > > -
> > > ---*/
> > > -{
> > > - EFI_FFS_FILE_HEADER *PeiCoreFile;
> > > - EFI_FFS_FILE_HEADER *SecCoreFile;
> > > - EFI_STATUS Status;
> > > - EFI_FILE_SECTION_POINTER Pe32Section;
> > > - UINT32 EntryPoint;
> > > - UINT32 BaseOfCode;
> > > - UINT16 MachineType;
> > > - EFI_PHYSICAL_ADDRESS PeiCorePhysicalAddress;
> > > - EFI_PHYSICAL_ADDRESS SecCorePhysicalAddress;
> > > - EFI_PHYSICAL_ADDRESS TrapAddress;
> > > -
> > > - //
> > > - // Verify input parameters
> > > - //
> > > - if (FvImage == NULL || FvInfo == NULL) {
> > > - Error (NULL, 0, 3000, "Invalid", "FvImage or FvInfo is NULL");
> > > - return EFI_INVALID_PARAMETER;
> > > - }
> > > - //
> > > - // Initialize FV library
> > > - //
> > > - InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> > > -
> > > - //
> > > - // Find the Sec Core
> > > - //
> > > - Status = GetFileByType (EFI_FV_FILETYPE_SECURITY_CORE, 1,
> > > &SecCoreFile);
> > > - if (EFI_ERROR (Status) || SecCoreFile == NULL) {
> > > - //
> > > - // Maybe hardware does SEC job and we only have PEI Core?
> > > - //
> > > -
> > > - //
> > > - // Find the PEI Core. It may not exist if SEC loads DXE core directly
> > > - //
> > > - PeiCorePhysicalAddress = 0;
> > > - Status = GetFileByType (EFI_FV_FILETYPE_PEI_CORE, 1, &PeiCoreFile);
> > > - if (!EFI_ERROR(Status) && PeiCoreFile != NULL) {
> > > - //
> > > - // PEI Core found, now find PE32 or TE section
> > > - //
> > > - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_PE32, 1,
> > &Pe32Section);
> > > - if (Status == EFI_NOT_FOUND) {
> > > - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_TE, 1,
> > &Pe32Section);
> > > - }
> > > -
> > > - if (EFI_ERROR (Status)) {
> > > - Error (NULL, 0, 3000, "Invalid", "could not find either a PE32 or a TE
> > section in PEI core file!");
> > > - return EFI_ABORTED;
> > > - }
> > > -
> > > - Status = GetPe32Info (
> > > - (VOID *) ((UINTN) Pe32Section.Pe32Section +
> > GetSectionHeaderLength(Pe32Section.CommonHeader)),
> > > - &EntryPoint,
> > > - &BaseOfCode,
> > > - &MachineType
> > > - );
> > > -
> > > - if (EFI_ERROR (Status)) {
> > > - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for
> > the PEI core!");
> > > - return EFI_ABORTED;
> > > - }
> > > - //
> > > - // Physical address is FV base + offset of PE32 + offset of the entry
> > point
> > > - //
> > > - PeiCorePhysicalAddress = FvInfo->BaseAddress;
> > > - PeiCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section +
> > GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN) FvImage-
> > >FileImage;
> > > - PeiCorePhysicalAddress += EntryPoint;
> > > - DebugMsg (NULL, 0, 9, "PeiCore physical entry point address",
> > "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
> > > - RiscvPatchVtf (VtfFileImage, (UINT32)PeiCorePhysicalAddress);
> > > - }
> > > - return EFI_SUCCESS;
> > > - }
> > > -
> > > - //
> > > - // Sec Core found, now find PE32 section
> > > - //
> > > - Status = GetSectionByType (SecCoreFile, EFI_SECTION_PE32, 1,
> > > &Pe32Section);
> > > - if (Status == EFI_NOT_FOUND) {
> > > - Status = GetSectionByType (SecCoreFile, EFI_SECTION_TE, 1,
> > &Pe32Section);
> > > - }
> > > -
> > > - if (EFI_ERROR (Status)) {
> > > - Error (NULL, 0, 3000, "Invalid", "could not find a PE32 section in the SEC
> > core file.");
> > > - return EFI_ABORTED;
> > > - }
> > > -
> > > - Status = GetPe32Info (
> > > - (VOID *) ((UINTN) Pe32Section.Pe32Section +
> > GetSectionHeaderLength(Pe32Section.CommonHeader)),
> > > - &EntryPoint,
> > > - &BaseOfCode,
> > > - &MachineType
> > > - );
> > > - if (EFI_ERROR (Status)) {
> > > - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for
> > the SEC core.");
> > > - return EFI_ABORTED;
> > > - }
> > > -
> > > - if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) &&
> > (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > > - //
> > > - // If SEC is not RISC-V we have nothing to do
> > > - //
> > > - return EFI_SUCCESS;
> > > - }
> > > -
> > > - //
> > > - // Physical address is FV base + offset of PE32 + offset of the
> > > entry point
> > > - //
> > > - SecCorePhysicalAddress = FvInfo->BaseAddress;
> > > - SecCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section +
> > > GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN)
> > > FvImage->FileImage;
> > > - SecCorePhysicalAddress += EntryPoint;
> > > - DebugMsg (NULL, 0, 0x14, "SecCore physical entry point address",
> > > "Address = 0x%llX", (unsigned long long) SecCorePhysicalAddress);
> > > - RiscvPatchVtf (VtfFileImage, (UINT32)SecCorePhysicalAddress);
> > > - //
> > > - // Update RISC-V trap handler.
> > > - //
> > > - TrapAddress = (UINTN) Pe32Section.Pe32Section +
> > > GetSectionHeaderLength(Pe32Section.CommonHeader) + EntryPoint;
> > > - TrapAddress -= 40;
> > > - RiscvPatchVtfTrapHandler (VtfFileImage, TrapAddress);
> > > -
> > > - DebugMsg (NULL, 0, 9, "Update Reset vector in FV Header", NULL);
> > > - return EFI_SUCCESS;
> > > -}
> > >
> > > EFI_STATUS
> > > FindCorePeSection(
> > > @@ -2581,6 +2430,106 @@ Returns:
> > > }
> > >
> > > EFI_STATUS
> > > +UpdateRiscvResetVectorIfNeeded (
> > > + MEMORY_FILE *FvImage,
> > > + FV_INFO *FvInfo
> > > + )
> > > +/*++
> > > +
> > > +Routine Description:
> > > + This parses the FV looking for SEC and patches that address into
> > > +the
> > > + beginning of the FV header.
> > > +
> > > + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > > +
> > > +Arguments:
> > > + FvImage Memory file for the FV memory image/
> > > + FvInfo Information read from INF file.
> > > +
> > > +Returns:
> > > +
> > > + EFI_SUCCESS Function Completed successfully.
> > > + EFI_ABORTED Error encountered.
> > > + EFI_INVALID_PARAMETER A required parameter was NULL.
> > > + EFI_NOT_FOUND PEI Core file not found.
> > > +
> > > +--*/
> > > +{
> > > + EFI_STATUS Status;
> > > + UINT16 MachineType;
> > > + EFI_FILE_SECTION_POINTER SecPe32;
> > > + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
> > > +
> > > + UINT32 bSecCore;
> > > + UINT32 tmp;
> > > +
> > > +
> > > + //
> > > + // Verify input parameters
> > > + //
> > > + if (FvImage == NULL || FvInfo == NULL) {
> > > + return EFI_INVALID_PARAMETER;
> > > + }
> > > + //
> > > + // Initialize FV library
> > > + //
> > > + InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> > > +
> > > + //
> > > + // Find the Sec Core
> > > + //
> > > + Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size,
> > > + EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
> > > + if(EFI_ERROR(Status)) {
> > > + printf("skip because Secutiry Core not found\n");
> > > + return EFI_SUCCESS;
> > > + }
> > > +
> > > + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
> > > +
> > > + Status = GetCoreMachineType(SecPe32, &MachineType);
> > > + if(EFI_ERROR(Status)) {
> > > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type for
> > SEC core.");
> > > + return EFI_ABORTED;
> > > + }
> > > +
> > > + if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) &&
> > (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > > + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because
> > Machine type is not RiscV.");
> > > + return EFI_ABORTED;
> > > + }
> > > +
> > > + Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo,
> > > + SecPe32, &SecCoreEntryAddress);
> > > + if(EFI_ERROR(Status)) {
> > > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point
> > address for SEC Core.");
> > > + return EFI_ABORTED;
> > > + }
> > > +
> > > + VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned long
> > > + long) SecCoreEntryAddress); VerboseMsg("BaseAddress = 0x%llX",
> > > + (unsigned long long) FvInfo->BaseAddress); bSecCore =
> > > + (SecCoreEntryAddress - FvInfo->BaseAddress); VerboseMsg("offset =
> > > + 0x%llX", bSecCore);
> > > +
> > > + if(bSecCore > 0x0fffff) {
> > > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of
> > start of the FV");
> > > + return EFI_ABORTED;
> > > + }
> > > +
> > > + tmp = bSecCore;
> > > + bSecCore = 0;
> > > + //J-type
> > > + bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
> > > + bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
> > > + bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
> > > + bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
> > > + bSecCore |= 0x6F; //JAL opcode
> > > +
> > > + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
> > > +
> > > + return EFI_SUCCESS;
> > > +}
> > > +
> > > +
> > > +
> > > +EFI_STATUS
> > > GetPe32Info (
> > > IN UINT8 *Pe32,
> > > OUT UINT32 *EntryPoint,
> > > @@ -3037,7 +2986,6 @@ Returns:
> > > FvHeader->Checksum = 0;
> > > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader,
> > FvHeader->HeaderLength / sizeof (UINT16));
> > > }
> > > -
> > > //
> > > // Add files to FV
> > > //
> > > @@ -3069,39 +3017,22 @@ Returns:
> > > goto Finish;
> > > }
> > >
> > > - if (mRiscV) {
> > > + if (!mArm && !mRiscV) {
> > > //
> > > - // Update RISCV reset vector.
> > > + // Update reset vector (SALE_ENTRY for IPF)
> > > + // Now for IA32 and IA64 platform, the fv which has bsf file must have
> > the
> > > + // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to update
> > the
> > > + // reset vector. If the PEI Core is found, the VTF file will probably get
> > > + // corrupted by updating the entry point.
> > > //
> > > - DebugMsg (NULL, 0, INFO_LOG_LEVEL, "Update RISCV reset vector",
> > NULL);
> > > - Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile,
> > &mFvDataInfo, VtfFileImage);
> > > - if (EFI_ERROR (Status)) {
> > > - Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for
> > RISC-V.");
> > > + if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) ==
> > FV_IMAGES_TOP_ADDRESS) {
> > > + Status = UpdateResetVector (&FvImageMemoryFile, &mFvDataInfo,
> > VtfFileImage);
> > > + if (EFI_ERROR(Status)) {
> > > + Error (NULL, 0, 3000, "Invalid", "Could not update the
> > > + reset vector.");
> > > goto Finish;
> > > - }
> > > - //
> > > - // Update Checksum for FvHeader
> > > - //
> > > - FvHeader->Checksum = 0;
> > > - FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader,
> > FvHeader->HeaderLength / sizeof (UINT16));
> > > - } else {
> > > - if (!mArm) {
> > > - //
> > > - // Update reset vector (SALE_ENTRY for IPF)
> > > - // Now for IA32 and IA64 platform, the fv which has bsf file must have
> > the
> > > - // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to update
> > the
> > > - // reset vector. If the PEI Core is found, the VTF file will probably get
> > > - // corrupted by updating the entry point.
> > > - //
> > > - if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) ==
> > FV_IMAGES_TOP_ADDRESS) {
> > > - Status = UpdateResetVector (&FvImageMemoryFile, &mFvDataInfo,
> > VtfFileImage);
> > > - if (EFI_ERROR(Status)) {
> > > - Error (NULL, 0, 3000, "Invalid", "Could not update the reset
> > vector.");
> > > - goto Finish;
> > > - }
> > > - DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> > > - }
> > > }
> > > + DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> > > + }
> > > }
> > > }
> > >
> > > @@ -3119,6 +3050,22 @@ Returns:
> > > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader,
> > FvHeader->HeaderLength / sizeof (UINT16));
> > > }
> > >
> > > + if (mRiscV) {
> > > + //
> > > + // Update RISCV reset vector.
> > > + //
> > > + Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile,
> > &mFvDataInfo);
> > > + if (EFI_ERROR (Status)) {
> > > + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for
> > RISC-V.");
> > > + goto Finish;
> > > + }
> > > + //
> > > + // Update Checksum for FvHeader
> > > + //
> > > + FvHeader->Checksum = 0;
> > > + FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader,
> > > + FvHeader->HeaderLength / sizeof (UINT16)); }
> > > +
> > > //
> > > // Update FV Alignment attribute to the largest alignment of all the FFS
> > files in the FV
> > > //
> > > @@ -3853,7 +3800,7 @@ Returns:
> > > ImageContext.DestinationAddress = NewPe32BaseAddress;
> > > Status = PeCoffLoaderRelocateImage (&ImageContext);
> > > if (EFI_ERROR (Status)) {
> > > - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of
> > %s", FileName);
> > > + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed
> > > + on rebase of %s Status=%d", FileName, Status);
> > > free ((VOID *) MemoryImagePointer);
> > > return Status;
> > > }
> > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > index 4857485..77b4d53 100644
> > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > @@ -946,8 +946,60 @@ WriteSections64 (
> > > RiscvSymSecIndex = 0;
> > > break;
> > >
> > > + case R_RISCV_PCREL_HI20:
> > > + RiscvHi20Targ = Targ;
> > > + RiscvHi20Sym = SymShdr;
> > > + RiscvSymSecIndex = Sym->st_shndx;
> > > +
> > > + Value = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> > > + printf("PCREL_HI20 Sym:[%s] value:0x%x SymShdr->sh_addr:0x%lx
> > mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr->sh_addr,
> > mCoffSectionsOffset[Sym->st_shndx]);
> > > + break;
> > > + case R_RISCV_PCREL_LO12_I:
> > > + if (RiscvHi20Targ != NULL && RiscvHi20Sym != NULL &&
> > RiscvSymSecIndex != 0) {
> > > + int i;
> > > + Value2 = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> > > + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> > > + if(Value & (RISCV_IMM_REACH/2)) {
> > > + Value |= ~(RISCV_IMM_REACH-1);
> > > + }
> > > + printf("PCREL_LO12_I Sym:[%s] value:0x%x SymShdr-
> > >sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym), Value,
> > SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
> > > + Value = Value - RiscvHi20Sym->sh_addr +
> > mCoffSectionsOffset[RiscvSymSecIndex];
> > > + if(-2048 > (INT32)Value) {
> > > + i = (-Value / 4096);
> > > + //Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> > PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> > > + printf("WriteSections64(): PCREL_LO12_I relocation out of range.
> > Value:%d Value2:%d i=%d\n", Value, Value2, i);
> > > + Value2 -= i;
> > > + Value += 4096 * i;
> > > + if(-2048 > (INT32)Value) {
> > > + Value2 -= 1;
> > > + Value += 4096;
> > > + }
> > > + }
> > > + else if( 2047 < (INT32)Value) {
> > > + i = (Value / 4096);
> > > + //Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> > PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> > > + printf("WriteSections64(): PCREL_LO12_I relocation out of range.
> > Value:%d Value2:%d i=%d\n", Value, Value2, i);
> > > + Value2 += i;
> > > + Value -= 4096 * i;
> > > + if(2047 < (INT32)Value) {
> > > + Value2 += 1;
> > > + Value -= 4096;
> > > + }
> > > + }
> > > +
> > > + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) |
> > (RV_X(*(UINT32*)Targ, 0, 20));
> > > + *(UINT32 *)RiscvHi20Targ = (RV_X(Value2, 0, 20)<<12) |
> > (RV_X(*(UINT32 *)RiscvHi20Targ, 0, 12));
> > > + printf("PCREL_LO12_I Sym:[%s] relocated value:0x%x(%d)
> > value2:0x%x(%d) SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n",
> > GetSymName(Sym), Value, Value, Value2, Value2, SymShdr->sh_addr,
> > mCoffSectionsOffset[Sym->st_shndx]);
> > > + }
> > > + RiscvHi20Sym = NULL;
> > > + RiscvHi20Targ = NULL;
> > > + RiscvSymSecIndex = 0;
> > > + break;
> > > +
> > > case R_RISCV_ADD64:
> > > case R_RISCV_SUB64:
> > > + case R_RISCV_ADD32:
> > > + case R_RISCV_SUB32:
> > > case R_RISCV_BRANCH:
> > > case R_RISCV_JAL:
> > > case R_RISCV_GPREL_I:
> > > @@ -1120,6 +1172,20 @@ WriteRelocations64 (
> > > EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > break;
> > >
> > > + case R_RISCV_ADD32:
> > > + CoffAddFixup(
> > > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > > + + (Rel->r_offset - SecShdr->sh_addr)),
> > > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > + break;
> > > +
> > > + case R_RISCV_SUB32:
> > > + CoffAddFixup(
> > > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > > + + (Rel->r_offset - SecShdr->sh_addr)),
> > > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > + break;
> > > +
> > > case R_RISCV_BRANCH:
> > > CoffAddFixup(
> > > (UINT32) ((UINT64)
> > > mCoffSectionsOffset[RelShdr->sh_info]
> > > @@ -1145,6 +1211,8 @@ WriteRelocations64 (
> > > case R_RISCV_SET8:
> > > case R_RISCV_SET16:
> > > case R_RISCV_SET32:
> > > + case R_RISCV_PCREL_HI20:
> > > + case R_RISCV_PCREL_LO12_I:
> > > break;
> > >
> > > default:
> >
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform
2019-08-28 8:59 ` Jonathan Cameron
@ 2019-08-28 9:08 ` Abner Chang
[not found] ` <15BF0B00F4581767.2982@groups.io>
1 sibling, 0 replies; 19+ messages in thread
From: Abner Chang @ 2019-08-28 9:08 UTC (permalink / raw)
To: Jonathan Cameron; +Cc: devel@edk2.groups.io
> -----Original Message-----
> From: Jonathan Cameron [mailto:jonathan.cameron@huawei.com]
> Sent: Wednesday, August 28, 2019 5:00 PM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools:
> Update EDK2 build tool for RISC-V platform
>
> On Wed, 28 Aug 2019 08:43:10 +0000
> "Chang, Abner (HPS SW/FW Technologist)" <abner.chang@hpe.com> wrote:
>
> > Thanks Jonathan, the cover letter and 3/14 patch were just sent.
>
> Great. So am I right in thinking these apply to:
> INVALID URI REMOVED
> 3A__github.com_tianocore_edk2-2Dstaging_tree_RISC-
> 2DV&d=DwICAg&c=C5b8zRQO1miGmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6
> qU3NYRO03nHp9P7Z5q59A3E&m=4xGwArhbyMMHxteOpv4UP8PJWPKah5H
> fR_X2Dl0H8vE&s=sCxw_Qm3DjjrX9vULVZYYw6jqhmQWygJP-B0Dltr6kc&e= ?
>
> Any plans to rebase that tree as it seems to be a few years old now?
Yes. we have plan to rebase it as you said this one is too old, will do it while edk2 devel review those patches ( includes edk2-platform/devel-rsicv patches)
Thanks
>
> Thanks,
>
> Jonathan
>
> >
> > Abner
> >
> > > -----Original Message-----
> > > From: Jonathan Cameron [mailto:jonathan.cameron@huawei.com]
> > > Sent: Wednesday, August 28, 2019 4:18 PM
> > > To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> > > Cc: devel@edk2.groups.io
> > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]:
> BaseTools:
> > > Update EDK2 build tool for RISC-V platform
> > >
> > > Hi Abner,
> > >
> > > Just noticed in passing that this series doesn't seem to have a 3/14?
> > >
> > > Speaking personally it would be useful to have a cover letter with a
> > > quick summary of the series content.
> > >
> > > Thanks,
> > >
> > > Jonathan
> > >
> > > On Tue, 27 Aug 2019 14:00:19 +0800
> > > Abner Chang <abner.chang@hpe.com> wrote:
> > >
> > > > Elf64Convert.c
> > > > - Relocation process to hadnle below opcodes,
> > > > * PCRELHI20
> > > > * PCRELLO12
> > > > * ADD32
> > > > * SUB32
> > > >
> > > > GenFvInternalLib.c
> > > > - This atches jump instrcution at the position of first
> > > > instrcution fetched by
> > > RISC-V processor after Zeroth Stage Boot Loader (ZSBL).
> > > >
> > > > Contributed-under: TianoCore Contribution Agreement 1.0
> > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > ---
> > > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 311
> > > > ++++++++++++------
> > > ----------
> > > > BaseTools/Source/C/GenFw/Elf64Convert.c | 68 ++++++
> > > > 2 files changed, 197 insertions(+), 182 deletions(-)
> > > >
> > > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > index 01da00c..92abb7c 100644
> > > > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > @@ -1956,157 +1956,6 @@ Returns:
> > > > return EFI_UNSUPPORTED;
> > > > }
> > > >
> > > > -EFI_STATUS
> > > > -UpdateRiscvResetVectorIfNeeded (
> > > > - MEMORY_FILE *FvImage,
> > > > - FV_INFO *FvInfo,
> > > > - EFI_FFS_FILE_HEADER *VtfFileImage
> > > > - )
> > > > -/*++
> > > > -
> > > > -Routine Description:
> > > > - This parses the FV looking for SEC and patches that address
> > > > into the
> > > > - beginning of the FV header.
> > > > -
> > > > - For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > > > -
> > > > -Arguments:
> > > > - FvImage Memory file for the FV memory image/
> > > > - FvInfo Information read from INF file.
> > > > - VtfFileImage Instance of VTF file.
> > > > -
> > > > -Returns:
> > > > -
> > > > - EFI_SUCCESS Function Completed successfully.
> > > > - EFI_ABORTED Error encountered.
> > > > - EFI_INVALID_PARAMETER A required parameter was NULL.
> > > > - EFI_NOT_FOUND PEI Core file not found.
> > > > -
> > > > ---*/
> > > > -{
> > > > - EFI_FFS_FILE_HEADER *PeiCoreFile;
> > > > - EFI_FFS_FILE_HEADER *SecCoreFile;
> > > > - EFI_STATUS Status;
> > > > - EFI_FILE_SECTION_POINTER Pe32Section;
> > > > - UINT32 EntryPoint;
> > > > - UINT32 BaseOfCode;
> > > > - UINT16 MachineType;
> > > > - EFI_PHYSICAL_ADDRESS PeiCorePhysicalAddress;
> > > > - EFI_PHYSICAL_ADDRESS SecCorePhysicalAddress;
> > > > - EFI_PHYSICAL_ADDRESS TrapAddress;
> > > > -
> > > > - //
> > > > - // Verify input parameters
> > > > - //
> > > > - if (FvImage == NULL || FvInfo == NULL) {
> > > > - Error (NULL, 0, 3000, "Invalid", "FvImage or FvInfo is NULL");
> > > > - return EFI_INVALID_PARAMETER;
> > > > - }
> > > > - //
> > > > - // Initialize FV library
> > > > - //
> > > > - InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> > > > -
> > > > - //
> > > > - // Find the Sec Core
> > > > - //
> > > > - Status = GetFileByType (EFI_FV_FILETYPE_SECURITY_CORE, 1,
> > > > &SecCoreFile);
> > > > - if (EFI_ERROR (Status) || SecCoreFile == NULL) {
> > > > - //
> > > > - // Maybe hardware does SEC job and we only have PEI Core?
> > > > - //
> > > > -
> > > > - //
> > > > - // Find the PEI Core. It may not exist if SEC loads DXE core directly
> > > > - //
> > > > - PeiCorePhysicalAddress = 0;
> > > > - Status = GetFileByType (EFI_FV_FILETYPE_PEI_CORE, 1,
> &PeiCoreFile);
> > > > - if (!EFI_ERROR(Status) && PeiCoreFile != NULL) {
> > > > - //
> > > > - // PEI Core found, now find PE32 or TE section
> > > > - //
> > > > - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_PE32, 1,
> > > &Pe32Section);
> > > > - if (Status == EFI_NOT_FOUND) {
> > > > - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_TE, 1,
> > > &Pe32Section);
> > > > - }
> > > > -
> > > > - if (EFI_ERROR (Status)) {
> > > > - Error (NULL, 0, 3000, "Invalid", "could not find either a PE32 or a TE
> > > section in PEI core file!");
> > > > - return EFI_ABORTED;
> > > > - }
> > > > -
> > > > - Status = GetPe32Info (
> > > > - (VOID *) ((UINTN) Pe32Section.Pe32Section +
> > > GetSectionHeaderLength(Pe32Section.CommonHeader)),
> > > > - &EntryPoint,
> > > > - &BaseOfCode,
> > > > - &MachineType
> > > > - );
> > > > -
> > > > - if (EFI_ERROR (Status)) {
> > > > - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point
> for
> > > the PEI core!");
> > > > - return EFI_ABORTED;
> > > > - }
> > > > - //
> > > > - // Physical address is FV base + offset of PE32 + offset of the entry
> > > point
> > > > - //
> > > > - PeiCorePhysicalAddress = FvInfo->BaseAddress;
> > > > - PeiCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section +
> > > GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN)
> FvImage-
> > > >FileImage;
> > > > - PeiCorePhysicalAddress += EntryPoint;
> > > > - DebugMsg (NULL, 0, 9, "PeiCore physical entry point address",
> > > "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
> > > > - RiscvPatchVtf (VtfFileImage, (UINT32)PeiCorePhysicalAddress);
> > > > - }
> > > > - return EFI_SUCCESS;
> > > > - }
> > > > -
> > > > - //
> > > > - // Sec Core found, now find PE32 section
> > > > - //
> > > > - Status = GetSectionByType (SecCoreFile, EFI_SECTION_PE32, 1,
> > > > &Pe32Section);
> > > > - if (Status == EFI_NOT_FOUND) {
> > > > - Status = GetSectionByType (SecCoreFile, EFI_SECTION_TE, 1,
> > > &Pe32Section);
> > > > - }
> > > > -
> > > > - if (EFI_ERROR (Status)) {
> > > > - Error (NULL, 0, 3000, "Invalid", "could not find a PE32 section in the
> SEC
> > > core file.");
> > > > - return EFI_ABORTED;
> > > > - }
> > > > -
> > > > - Status = GetPe32Info (
> > > > - (VOID *) ((UINTN) Pe32Section.Pe32Section +
> > > GetSectionHeaderLength(Pe32Section.CommonHeader)),
> > > > - &EntryPoint,
> > > > - &BaseOfCode,
> > > > - &MachineType
> > > > - );
> > > > - if (EFI_ERROR (Status)) {
> > > > - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point for
> > > the SEC core.");
> > > > - return EFI_ABORTED;
> > > > - }
> > > > -
> > > > - if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) &&
> > > (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > > > - //
> > > > - // If SEC is not RISC-V we have nothing to do
> > > > - //
> > > > - return EFI_SUCCESS;
> > > > - }
> > > > -
> > > > - //
> > > > - // Physical address is FV base + offset of PE32 + offset of the
> > > > entry point
> > > > - //
> > > > - SecCorePhysicalAddress = FvInfo->BaseAddress;
> > > > - SecCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section +
> > > > GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN)
> > > > FvImage->FileImage;
> > > > - SecCorePhysicalAddress += EntryPoint;
> > > > - DebugMsg (NULL, 0, 0x14, "SecCore physical entry point
> > > > address", "Address = 0x%llX", (unsigned long long)
> > > > SecCorePhysicalAddress);
> > > > - RiscvPatchVtf (VtfFileImage, (UINT32)SecCorePhysicalAddress);
> > > > - //
> > > > - // Update RISC-V trap handler.
> > > > - //
> > > > - TrapAddress = (UINTN) Pe32Section.Pe32Section +
> > > > GetSectionHeaderLength(Pe32Section.CommonHeader) + EntryPoint;
> > > > - TrapAddress -= 40;
> > > > - RiscvPatchVtfTrapHandler (VtfFileImage, TrapAddress);
> > > > -
> > > > - DebugMsg (NULL, 0, 9, "Update Reset vector in FV Header",
> > > > NULL);
> > > > - return EFI_SUCCESS;
> > > > -}
> > > >
> > > > EFI_STATUS
> > > > FindCorePeSection(
> > > > @@ -2581,6 +2430,106 @@ Returns:
> > > > }
> > > >
> > > > EFI_STATUS
> > > > +UpdateRiscvResetVectorIfNeeded (
> > > > + MEMORY_FILE *FvImage,
> > > > + FV_INFO *FvInfo
> > > > + )
> > > > +/*++
> > > > +
> > > > +Routine Description:
> > > > + This parses the FV looking for SEC and patches that address
> > > > +into the
> > > > + beginning of the FV header.
> > > > +
> > > > + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > > > +
> > > > +Arguments:
> > > > + FvImage Memory file for the FV memory image/
> > > > + FvInfo Information read from INF file.
> > > > +
> > > > +Returns:
> > > > +
> > > > + EFI_SUCCESS Function Completed successfully.
> > > > + EFI_ABORTED Error encountered.
> > > > + EFI_INVALID_PARAMETER A required parameter was NULL.
> > > > + EFI_NOT_FOUND PEI Core file not found.
> > > > +
> > > > +--*/
> > > > +{
> > > > + EFI_STATUS Status;
> > > > + UINT16 MachineType;
> > > > + EFI_FILE_SECTION_POINTER SecPe32;
> > > > + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
> > > > +
> > > > + UINT32 bSecCore;
> > > > + UINT32 tmp;
> > > > +
> > > > +
> > > > + //
> > > > + // Verify input parameters
> > > > + //
> > > > + if (FvImage == NULL || FvInfo == NULL) {
> > > > + return EFI_INVALID_PARAMETER; } // // Initialize FV
> > > > + library // InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> > > > +
> > > > + //
> > > > + // Find the Sec Core
> > > > + //
> > > > + Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size,
> > > > + EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
> > > > + if(EFI_ERROR(Status)) {
> > > > + printf("skip because Secutiry Core not found\n");
> > > > + return EFI_SUCCESS;
> > > > + }
> > > > +
> > > > + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
> > > > +
> > > > + Status = GetCoreMachineType(SecPe32, &MachineType);
> > > > + if(EFI_ERROR(Status)) {
> > > > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32
> > > > + machine type for
> > > SEC core.");
> > > > + return EFI_ABORTED;
> > > > + }
> > > > +
> > > > + if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) &&
> > > (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > > > + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core
> > > > + because
> > > Machine type is not RiscV.");
> > > > + return EFI_ABORTED;
> > > > + }
> > > > +
> > > > + Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo,
> > > > + SecPe32, &SecCoreEntryAddress);
> > > > + if(EFI_ERROR(Status)) {
> > > > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry
> > > > + point
> > > address for SEC Core.");
> > > > + return EFI_ABORTED;
> > > > + }
> > > > +
> > > > + VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned
> > > > + long
> > > > + long) SecCoreEntryAddress); VerboseMsg("BaseAddress = 0x%llX",
> > > > + (unsigned long long) FvInfo->BaseAddress); bSecCore =
> > > > + (SecCoreEntryAddress - FvInfo->BaseAddress); VerboseMsg("offset
> > > > + = 0x%llX", bSecCore);
> > > > +
> > > > + if(bSecCore > 0x0fffff) {
> > > > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be
> > > > + within 1MB of
> > > start of the FV");
> > > > + return EFI_ABORTED;
> > > > + }
> > > > +
> > > > + tmp = bSecCore;
> > > > + bSecCore = 0;
> > > > + //J-type
> > > > + bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
> > > > + bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
> > > > + bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
> > > > + bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
> > > > + bSecCore |= 0x6F; //JAL opcode
> > > > +
> > > > + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
> > > > +
> > > > + return EFI_SUCCESS;
> > > > +}
> > > > +
> > > > +
> > > > +
> > > > +EFI_STATUS
> > > > GetPe32Info (
> > > > IN UINT8 *Pe32,
> > > > OUT UINT32 *EntryPoint,
> > > > @@ -3037,7 +2986,6 @@ Returns:
> > > > FvHeader->Checksum = 0;
> > > > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> FvHeader,
> > > FvHeader->HeaderLength / sizeof (UINT16));
> > > > }
> > > > -
> > > > //
> > > > // Add files to FV
> > > > //
> > > > @@ -3069,39 +3017,22 @@ Returns:
> > > > goto Finish;
> > > > }
> > > >
> > > > - if (mRiscV) {
> > > > + if (!mArm && !mRiscV) {
> > > > //
> > > > - // Update RISCV reset vector.
> > > > + // Update reset vector (SALE_ENTRY for IPF)
> > > > + // Now for IA32 and IA64 platform, the fv which has bsf
> > > > + file must have
> > > the
> > > > + // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs
> > > > + to update
> > > the
> > > > + // reset vector. If the PEI Core is found, the VTF file will probably
> get
> > > > + // corrupted by updating the entry point.
> > > > //
> > > > - DebugMsg (NULL, 0, INFO_LOG_LEVEL, "Update RISCV reset
> vector",
> > > NULL);
> > > > - Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile,
> > > &mFvDataInfo, VtfFileImage);
> > > > - if (EFI_ERROR (Status)) {
> > > > - Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector
> for
> > > RISC-V.");
> > > > + if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) ==
> > > FV_IMAGES_TOP_ADDRESS) {
> > > > + Status = UpdateResetVector (&FvImageMemoryFile,
> > > > + &mFvDataInfo,
> > > VtfFileImage);
> > > > + if (EFI_ERROR(Status)) {
> > > > + Error (NULL, 0, 3000, "Invalid", "Could not update the
> > > > + reset vector.");
> > > > goto Finish;
> > > > - }
> > > > - //
> > > > - // Update Checksum for FvHeader
> > > > - //
> > > > - FvHeader->Checksum = 0;
> > > > - FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> FvHeader,
> > > FvHeader->HeaderLength / sizeof (UINT16));
> > > > - } else {
> > > > - if (!mArm) {
> > > > - //
> > > > - // Update reset vector (SALE_ENTRY for IPF)
> > > > - // Now for IA32 and IA64 platform, the fv which has bsf file must
> have
> > > the
> > > > - // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to
> update
> > > the
> > > > - // reset vector. If the PEI Core is found, the VTF file will probably
> get
> > > > - // corrupted by updating the entry point.
> > > > - //
> > > > - if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) ==
> > > FV_IMAGES_TOP_ADDRESS) {
> > > > - Status = UpdateResetVector (&FvImageMemoryFile,
> &mFvDataInfo,
> > > VtfFileImage);
> > > > - if (EFI_ERROR(Status)) {
> > > > - Error (NULL, 0, 3000, "Invalid", "Could not update the reset
> > > vector.");
> > > > - goto Finish;
> > > > - }
> > > > - DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> > > > - }
> > > > }
> > > > + DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> > > > + }
> > > > }
> > > > }
> > > >
> > > > @@ -3119,6 +3050,22 @@ Returns:
> > > > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> > > > FvHeader,
> > > FvHeader->HeaderLength / sizeof (UINT16));
> > > > }
> > > >
> > > > + if (mRiscV) {
> > > > + //
> > > > + // Update RISCV reset vector.
> > > > + //
> > > > + Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile,
> > > &mFvDataInfo);
> > > > + if (EFI_ERROR (Status)) {
> > > > + Error (NULL, 0, 3000, "Invalid", "Could not update the
> > > > + reset vector for
> > > RISC-V.");
> > > > + goto Finish;
> > > > + }
> > > > + //
> > > > + // Update Checksum for FvHeader
> > > > + //
> > > > + FvHeader->Checksum = 0;
> > > > + FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> > > > + FvHeader,
> > > > + FvHeader->HeaderLength / sizeof (UINT16)); }
> > > > +
> > > > //
> > > > // Update FV Alignment attribute to the largest alignment of
> > > > all the FFS
> > > files in the FV
> > > > //
> > > > @@ -3853,7 +3800,7 @@ Returns:
> > > > ImageContext.DestinationAddress = NewPe32BaseAddress;
> > > > Status = PeCoffLoaderRelocateImage (&ImageContext);
> > > > if (EFI_ERROR (Status)) {
> > > > - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on
> rebase of
> > > %s", FileName);
> > > > + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call
> > > > + failed on rebase of %s Status=%d", FileName, Status);
> > > > free ((VOID *) MemoryImagePointer);
> > > > return Status;
> > > > }
> > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > index 4857485..77b4d53 100644
> > > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > @@ -946,8 +946,60 @@ WriteSections64 (
> > > > RiscvSymSecIndex = 0;
> > > > break;
> > > >
> > > > + case R_RISCV_PCREL_HI20:
> > > > + RiscvHi20Targ = Targ;
> > > > + RiscvHi20Sym = SymShdr;
> > > > + RiscvSymSecIndex = Sym->st_shndx;
> > > > +
> > > > + Value = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> > > > + printf("PCREL_HI20 Sym:[%s] value:0x%x
> > > > + SymShdr->sh_addr:0x%lx
> > > mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr-
> >sh_addr,
> > > mCoffSectionsOffset[Sym->st_shndx]);
> > > > + break;
> > > > + case R_RISCV_PCREL_LO12_I:
> > > > + if (RiscvHi20Targ != NULL && RiscvHi20Sym != NULL &&
> > > RiscvSymSecIndex != 0) {
> > > > + int i;
> > > > + Value2 = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> > > > + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> > > > + if(Value & (RISCV_IMM_REACH/2)) {
> > > > + Value |= ~(RISCV_IMM_REACH-1);
> > > > + }
> > > > + printf("PCREL_LO12_I Sym:[%s] value:0x%x SymShdr-
> > > >sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym), Value,
> > > SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
> > > > + Value = Value - RiscvHi20Sym->sh_addr +
> > > mCoffSectionsOffset[RiscvSymSecIndex];
> > > > + if(-2048 > (INT32)Value) {
> > > > + i = (-Value / 4096);
> > > > + //Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> > > PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> > > > + printf("WriteSections64(): PCREL_LO12_I relocation out of
> range.
> > > Value:%d Value2:%d i=%d\n", Value, Value2, i);
> > > > + Value2 -= i;
> > > > + Value += 4096 * i;
> > > > + if(-2048 > (INT32)Value) {
> > > > + Value2 -= 1;
> > > > + Value += 4096;
> > > > + }
> > > > + }
> > > > + else if( 2047 < (INT32)Value) {
> > > > + i = (Value / 4096);
> > > > + //Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> > > PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> > > > + printf("WriteSections64(): PCREL_LO12_I relocation out of
> range.
> > > Value:%d Value2:%d i=%d\n", Value, Value2, i);
> > > > + Value2 += i;
> > > > + Value -= 4096 * i;
> > > > + if(2047 < (INT32)Value) {
> > > > + Value2 += 1;
> > > > + Value -= 4096;
> > > > + }
> > > > + }
> > > > +
> > > > + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) |
> > > (RV_X(*(UINT32*)Targ, 0, 20));
> > > > + *(UINT32 *)RiscvHi20Targ = (RV_X(Value2, 0,
> > > > + 20)<<12) |
> > > (RV_X(*(UINT32 *)RiscvHi20Targ, 0, 12));
> > > > + printf("PCREL_LO12_I Sym:[%s] relocated
> > > > + value:0x%x(%d)
> > > value2:0x%x(%d) SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n",
> > > GetSymName(Sym), Value, Value, Value2, Value2, SymShdr->sh_addr,
> > > mCoffSectionsOffset[Sym->st_shndx]);
> > > > + }
> > > > + RiscvHi20Sym = NULL;
> > > > + RiscvHi20Targ = NULL;
> > > > + RiscvSymSecIndex = 0;
> > > > + break;
> > > > +
> > > > case R_RISCV_ADD64:
> > > > case R_RISCV_SUB64:
> > > > + case R_RISCV_ADD32:
> > > > + case R_RISCV_SUB32:
> > > > case R_RISCV_BRANCH:
> > > > case R_RISCV_JAL:
> > > > case R_RISCV_GPREL_I:
> > > > @@ -1120,6 +1172,20 @@ WriteRelocations64 (
> > > > EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > > break;
> > > >
> > > > + case R_RISCV_ADD32:
> > > > + CoffAddFixup(
> > > > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > > > + + (Rel->r_offset - SecShdr->sh_addr)),
> > > > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > > + break;
> > > > +
> > > > + case R_RISCV_SUB32:
> > > > + CoffAddFixup(
> > > > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > > > + + (Rel->r_offset - SecShdr->sh_addr)),
> > > > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > > + break;
> > > > +
> > > > case R_RISCV_BRANCH:
> > > > CoffAddFixup(
> > > > (UINT32) ((UINT64)
> > > > mCoffSectionsOffset[RelShdr->sh_info]
> > > > @@ -1145,6 +1211,8 @@ WriteRelocations64 (
> > > > case R_RISCV_SET8:
> > > > case R_RISCV_SET16:
> > > > case R_RISCV_SET32:
> > > > + case R_RISCV_PCREL_HI20:
> > > > + case R_RISCV_PCREL_LO12_I:
> > > > break;
> > > >
> > > > default:
> > >
> >
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform
[not found] ` <15BF0B00F4581767.2982@groups.io>
@ 2019-09-04 11:18 ` Abner Chang
2019-09-04 14:32 ` Jonathan Cameron
0 siblings, 1 reply; 19+ messages in thread
From: Abner Chang @ 2019-09-04 11:18 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist),
Jonathan Cameron
Hi Jonathan, I created a new branch "RISC-V-V2" on edk2-staging which is based on most recent EDK2 master and sent the patches based on it.
This is easier for reviewers to review the changes for RISC-V EDK2 port. The original "RISC-V" branch has some stale implementation and may confuse people. This new branch on edk2-staging is much clear.
Thanks
Abner
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Wednesday, August 28, 2019 5:08 PM
> To: Jonathan Cameron <jonathan.cameron@huawei.com>
> Cc: devel@edk2.groups.io
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools:
> Update EDK2 build tool for RISC-V platform
>
> > -----Original Message-----
> > From: Jonathan Cameron [mailto:jonathan.cameron@huawei.com]
> > Sent: Wednesday, August 28, 2019 5:00 PM
> > To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> > Cc: devel@edk2.groups.io
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools:
> > Update EDK2 build tool for RISC-V platform
> >
> > On Wed, 28 Aug 2019 08:43:10 +0000
> > "Chang, Abner (HPS SW/FW Technologist)" <abner.chang@hpe.com>
> wrote:
> >
> > > Thanks Jonathan, the cover letter and 3/14 patch were just sent.
> >
> > Great. So am I right in thinking these apply to:
> > INVALID URI REMOVED
> > 3A__github.com_tianocore_edk2-2Dstaging_tree_RISC-
> >
> 2DV&d=DwICAg&c=C5b8zRQO1miGmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6
> >
> qU3NYRO03nHp9P7Z5q59A3E&m=4xGwArhbyMMHxteOpv4UP8PJWPKah5H
> > fR_X2Dl0H8vE&s=sCxw_Qm3DjjrX9vULVZYYw6jqhmQWygJP-
> B0Dltr6kc&e= ?
> >
> > Any plans to rebase that tree as it seems to be a few years old now?
> Yes. we have plan to rebase it as you said this one is too old, will do it while
> edk2 devel review those patches ( includes edk2-platform/devel-rsicv
> patches)
>
> Thanks
>
> >
> > Thanks,
> >
> > Jonathan
> >
> > >
> > > Abner
> > >
> > > > -----Original Message-----
> > > > From: Jonathan Cameron [mailto:jonathan.cameron@huawei.com]
> > > > Sent: Wednesday, August 28, 2019 4:18 PM
> > > > To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> > > > Cc: devel@edk2.groups.io
> > > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]:
> > BaseTools:
> > > > Update EDK2 build tool for RISC-V platform
> > > >
> > > > Hi Abner,
> > > >
> > > > Just noticed in passing that this series doesn't seem to have a 3/14?
> > > >
> > > > Speaking personally it would be useful to have a cover letter with
> > > > a quick summary of the series content.
> > > >
> > > > Thanks,
> > > >
> > > > Jonathan
> > > >
> > > > On Tue, 27 Aug 2019 14:00:19 +0800 Abner Chang
> > > > <abner.chang@hpe.com> wrote:
> > > >
> > > > > Elf64Convert.c
> > > > > - Relocation process to hadnle below opcodes,
> > > > > * PCRELHI20
> > > > > * PCRELLO12
> > > > > * ADD32
> > > > > * SUB32
> > > > >
> > > > > GenFvInternalLib.c
> > > > > - This atches jump instrcution at the position of first
> > > > > instrcution fetched by
> > > > RISC-V processor after Zeroth Stage Boot Loader (ZSBL).
> > > > >
> > > > > Contributed-under: TianoCore Contribution Agreement 1.0
> > > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > > ---
> > > > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 311
> > > > > ++++++++++++------
> > > > ----------
> > > > > BaseTools/Source/C/GenFw/Elf64Convert.c | 68 ++++++
> > > > > 2 files changed, 197 insertions(+), 182 deletions(-)
> > > > >
> > > > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > > index 01da00c..92abb7c 100644
> > > > > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > > @@ -1956,157 +1956,6 @@ Returns:
> > > > > return EFI_UNSUPPORTED;
> > > > > }
> > > > >
> > > > > -EFI_STATUS
> > > > > -UpdateRiscvResetVectorIfNeeded (
> > > > > - MEMORY_FILE *FvImage,
> > > > > - FV_INFO *FvInfo,
> > > > > - EFI_FFS_FILE_HEADER *VtfFileImage
> > > > > - )
> > > > > -/*++
> > > > > -
> > > > > -Routine Description:
> > > > > - This parses the FV looking for SEC and patches that address
> > > > > into the
> > > > > - beginning of the FV header.
> > > > > -
> > > > > - For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > > > > -
> > > > > -Arguments:
> > > > > - FvImage Memory file for the FV memory image/
> > > > > - FvInfo Information read from INF file.
> > > > > - VtfFileImage Instance of VTF file.
> > > > > -
> > > > > -Returns:
> > > > > -
> > > > > - EFI_SUCCESS Function Completed successfully.
> > > > > - EFI_ABORTED Error encountered.
> > > > > - EFI_INVALID_PARAMETER A required parameter was NULL.
> > > > > - EFI_NOT_FOUND PEI Core file not found.
> > > > > -
> > > > > ---*/
> > > > > -{
> > > > > - EFI_FFS_FILE_HEADER *PeiCoreFile;
> > > > > - EFI_FFS_FILE_HEADER *SecCoreFile;
> > > > > - EFI_STATUS Status;
> > > > > - EFI_FILE_SECTION_POINTER Pe32Section;
> > > > > - UINT32 EntryPoint;
> > > > > - UINT32 BaseOfCode;
> > > > > - UINT16 MachineType;
> > > > > - EFI_PHYSICAL_ADDRESS PeiCorePhysicalAddress;
> > > > > - EFI_PHYSICAL_ADDRESS SecCorePhysicalAddress;
> > > > > - EFI_PHYSICAL_ADDRESS TrapAddress;
> > > > > -
> > > > > - //
> > > > > - // Verify input parameters
> > > > > - //
> > > > > - if (FvImage == NULL || FvInfo == NULL) {
> > > > > - Error (NULL, 0, 3000, "Invalid", "FvImage or FvInfo is NULL");
> > > > > - return EFI_INVALID_PARAMETER;
> > > > > - }
> > > > > - //
> > > > > - // Initialize FV library
> > > > > - //
> > > > > - InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> > > > > -
> > > > > - //
> > > > > - // Find the Sec Core
> > > > > - //
> > > > > - Status = GetFileByType (EFI_FV_FILETYPE_SECURITY_CORE, 1,
> > > > > &SecCoreFile);
> > > > > - if (EFI_ERROR (Status) || SecCoreFile == NULL) {
> > > > > - //
> > > > > - // Maybe hardware does SEC job and we only have PEI Core?
> > > > > - //
> > > > > -
> > > > > - //
> > > > > - // Find the PEI Core. It may not exist if SEC loads DXE core directly
> > > > > - //
> > > > > - PeiCorePhysicalAddress = 0;
> > > > > - Status = GetFileByType (EFI_FV_FILETYPE_PEI_CORE, 1,
> > &PeiCoreFile);
> > > > > - if (!EFI_ERROR(Status) && PeiCoreFile != NULL) {
> > > > > - //
> > > > > - // PEI Core found, now find PE32 or TE section
> > > > > - //
> > > > > - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_PE32, 1,
> > > > &Pe32Section);
> > > > > - if (Status == EFI_NOT_FOUND) {
> > > > > - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_TE, 1,
> > > > &Pe32Section);
> > > > > - }
> > > > > -
> > > > > - if (EFI_ERROR (Status)) {
> > > > > - Error (NULL, 0, 3000, "Invalid", "could not find either a PE32 or a
> TE
> > > > section in PEI core file!");
> > > > > - return EFI_ABORTED;
> > > > > - }
> > > > > -
> > > > > - Status = GetPe32Info (
> > > > > - (VOID *) ((UINTN) Pe32Section.Pe32Section +
> > > > GetSectionHeaderLength(Pe32Section.CommonHeader)),
> > > > > - &EntryPoint,
> > > > > - &BaseOfCode,
> > > > > - &MachineType
> > > > > - );
> > > > > -
> > > > > - if (EFI_ERROR (Status)) {
> > > > > - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry
> point
> > for
> > > > the PEI core!");
> > > > > - return EFI_ABORTED;
> > > > > - }
> > > > > - //
> > > > > - // Physical address is FV base + offset of PE32 + offset of the entry
> > > > point
> > > > > - //
> > > > > - PeiCorePhysicalAddress = FvInfo->BaseAddress;
> > > > > - PeiCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section +
> > > > GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN)
> > FvImage-
> > > > >FileImage;
> > > > > - PeiCorePhysicalAddress += EntryPoint;
> > > > > - DebugMsg (NULL, 0, 9, "PeiCore physical entry point address",
> > > > "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
> > > > > - RiscvPatchVtf (VtfFileImage, (UINT32)PeiCorePhysicalAddress);
> > > > > - }
> > > > > - return EFI_SUCCESS;
> > > > > - }
> > > > > -
> > > > > - //
> > > > > - // Sec Core found, now find PE32 section
> > > > > - //
> > > > > - Status = GetSectionByType (SecCoreFile, EFI_SECTION_PE32, 1,
> > > > > &Pe32Section);
> > > > > - if (Status == EFI_NOT_FOUND) {
> > > > > - Status = GetSectionByType (SecCoreFile, EFI_SECTION_TE, 1,
> > > > &Pe32Section);
> > > > > - }
> > > > > -
> > > > > - if (EFI_ERROR (Status)) {
> > > > > - Error (NULL, 0, 3000, "Invalid", "could not find a PE32 section in the
> > SEC
> > > > core file.");
> > > > > - return EFI_ABORTED;
> > > > > - }
> > > > > -
> > > > > - Status = GetPe32Info (
> > > > > - (VOID *) ((UINTN) Pe32Section.Pe32Section +
> > > > GetSectionHeaderLength(Pe32Section.CommonHeader)),
> > > > > - &EntryPoint,
> > > > > - &BaseOfCode,
> > > > > - &MachineType
> > > > > - );
> > > > > - if (EFI_ERROR (Status)) {
> > > > > - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point
> for
> > > > the SEC core.");
> > > > > - return EFI_ABORTED;
> > > > > - }
> > > > > -
> > > > > - if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) &&
> > > > (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > > > > - //
> > > > > - // If SEC is not RISC-V we have nothing to do
> > > > > - //
> > > > > - return EFI_SUCCESS;
> > > > > - }
> > > > > -
> > > > > - //
> > > > > - // Physical address is FV base + offset of PE32 + offset of
> > > > > the entry point
> > > > > - //
> > > > > - SecCorePhysicalAddress = FvInfo->BaseAddress;
> > > > > - SecCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section +
> > > > > GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN)
> > > > > FvImage->FileImage;
> > > > > - SecCorePhysicalAddress += EntryPoint;
> > > > > - DebugMsg (NULL, 0, 0x14, "SecCore physical entry point
> > > > > address", "Address = 0x%llX", (unsigned long long)
> > > > > SecCorePhysicalAddress);
> > > > > - RiscvPatchVtf (VtfFileImage, (UINT32)SecCorePhysicalAddress);
> > > > > - //
> > > > > - // Update RISC-V trap handler.
> > > > > - //
> > > > > - TrapAddress = (UINTN) Pe32Section.Pe32Section +
> > > > > GetSectionHeaderLength(Pe32Section.CommonHeader) + EntryPoint;
> > > > > - TrapAddress -= 40;
> > > > > - RiscvPatchVtfTrapHandler (VtfFileImage, TrapAddress);
> > > > > -
> > > > > - DebugMsg (NULL, 0, 9, "Update Reset vector in FV Header",
> > > > > NULL);
> > > > > - return EFI_SUCCESS;
> > > > > -}
> > > > >
> > > > > EFI_STATUS
> > > > > FindCorePeSection(
> > > > > @@ -2581,6 +2430,106 @@ Returns:
> > > > > }
> > > > >
> > > > > EFI_STATUS
> > > > > +UpdateRiscvResetVectorIfNeeded (
> > > > > + MEMORY_FILE *FvImage,
> > > > > + FV_INFO *FvInfo
> > > > > + )
> > > > > +/*++
> > > > > +
> > > > > +Routine Description:
> > > > > + This parses the FV looking for SEC and patches that address
> > > > > +into the
> > > > > + beginning of the FV header.
> > > > > +
> > > > > + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > > > > +
> > > > > +Arguments:
> > > > > + FvImage Memory file for the FV memory image/
> > > > > + FvInfo Information read from INF file.
> > > > > +
> > > > > +Returns:
> > > > > +
> > > > > + EFI_SUCCESS Function Completed successfully.
> > > > > + EFI_ABORTED Error encountered.
> > > > > + EFI_INVALID_PARAMETER A required parameter was NULL.
> > > > > + EFI_NOT_FOUND PEI Core file not found.
> > > > > +
> > > > > +--*/
> > > > > +{
> > > > > + EFI_STATUS Status;
> > > > > + UINT16 MachineType;
> > > > > + EFI_FILE_SECTION_POINTER SecPe32;
> > > > > + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
> > > > > +
> > > > > + UINT32 bSecCore;
> > > > > + UINT32 tmp;
> > > > > +
> > > > > +
> > > > > + //
> > > > > + // Verify input parameters
> > > > > + //
> > > > > + if (FvImage == NULL || FvInfo == NULL) {
> > > > > + return EFI_INVALID_PARAMETER; } // // Initialize FV
> > > > > + library // InitializeFvLib (FvImage->FileImage,
> > > > > + FvInfo->Size);
> > > > > +
> > > > > + //
> > > > > + // Find the Sec Core
> > > > > + //
> > > > > + Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size,
> > > > > + EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
> > > > > + if(EFI_ERROR(Status)) {
> > > > > + printf("skip because Secutiry Core not found\n");
> > > > > + return EFI_SUCCESS;
> > > > > + }
> > > > > +
> > > > > + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
> > > > > +
> > > > > + Status = GetCoreMachineType(SecPe32, &MachineType);
> > > > > + if(EFI_ERROR(Status)) {
> > > > > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32
> > > > > + machine type for
> > > > SEC core.");
> > > > > + return EFI_ABORTED;
> > > > > + }
> > > > > +
> > > > > + if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) &&
> > > > (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > > > > + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core
> > > > > + because
> > > > Machine type is not RiscV.");
> > > > > + return EFI_ABORTED;
> > > > > + }
> > > > > +
> > > > > + Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo,
> > > > > + SecPe32, &SecCoreEntryAddress);
> > > > > + if(EFI_ERROR(Status)) {
> > > > > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32
> > > > > + entry point
> > > > address for SEC Core.");
> > > > > + return EFI_ABORTED;
> > > > > + }
> > > > > +
> > > > > + VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned
> > > > > + long
> > > > > + long) SecCoreEntryAddress); VerboseMsg("BaseAddress =
> > > > > + 0x%llX", (unsigned long long) FvInfo->BaseAddress); bSecCore
> > > > > + = (SecCoreEntryAddress - FvInfo->BaseAddress);
> > > > > + VerboseMsg("offset = 0x%llX", bSecCore);
> > > > > +
> > > > > + if(bSecCore > 0x0fffff) {
> > > > > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be
> > > > > + within 1MB of
> > > > start of the FV");
> > > > > + return EFI_ABORTED;
> > > > > + }
> > > > > +
> > > > > + tmp = bSecCore;
> > > > > + bSecCore = 0;
> > > > > + //J-type
> > > > > + bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
> > > > > + bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
> > > > > + bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
> > > > > + bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
> > > > > + bSecCore |= 0x6F; //JAL opcode
> > > > > +
> > > > > + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
> > > > > +
> > > > > + return EFI_SUCCESS;
> > > > > +}
> > > > > +
> > > > > +
> > > > > +
> > > > > +EFI_STATUS
> > > > > GetPe32Info (
> > > > > IN UINT8 *Pe32,
> > > > > OUT UINT32 *EntryPoint,
> > > > > @@ -3037,7 +2986,6 @@ Returns:
> > > > > FvHeader->Checksum = 0;
> > > > > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> > FvHeader,
> > > > FvHeader->HeaderLength / sizeof (UINT16));
> > > > > }
> > > > > -
> > > > > //
> > > > > // Add files to FV
> > > > > //
> > > > > @@ -3069,39 +3017,22 @@ Returns:
> > > > > goto Finish;
> > > > > }
> > > > >
> > > > > - if (mRiscV) {
> > > > > + if (!mArm && !mRiscV) {
> > > > > //
> > > > > - // Update RISCV reset vector.
> > > > > + // Update reset vector (SALE_ENTRY for IPF)
> > > > > + // Now for IA32 and IA64 platform, the fv which has bsf
> > > > > + file must have
> > > > the
> > > > > + // EndAddress of 0xFFFFFFFF. Thus, only this type fv
> > > > > + needs to update
> > > > the
> > > > > + // reset vector. If the PEI Core is found, the VTF file
> > > > > + will probably
> > get
> > > > > + // corrupted by updating the entry point.
> > > > > //
> > > > > - DebugMsg (NULL, 0, INFO_LOG_LEVEL, "Update RISCV reset
> > vector",
> > > > NULL);
> > > > > - Status = UpdateRiscvResetVectorIfNeeded
> (&FvImageMemoryFile,
> > > > &mFvDataInfo, VtfFileImage);
> > > > > - if (EFI_ERROR (Status)) {
> > > > > - Error (NULL, 0, 3000, "Invalid", "Could not update the reset
> vector
> > for
> > > > RISC-V.");
> > > > > + if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) ==
> > > > FV_IMAGES_TOP_ADDRESS) {
> > > > > + Status = UpdateResetVector (&FvImageMemoryFile,
> > > > > + &mFvDataInfo,
> > > > VtfFileImage);
> > > > > + if (EFI_ERROR(Status)) {
> > > > > + Error (NULL, 0, 3000, "Invalid", "Could not update
> > > > > + the reset vector.");
> > > > > goto Finish;
> > > > > - }
> > > > > - //
> > > > > - // Update Checksum for FvHeader
> > > > > - //
> > > > > - FvHeader->Checksum = 0;
> > > > > - FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> > FvHeader,
> > > > FvHeader->HeaderLength / sizeof (UINT16));
> > > > > - } else {
> > > > > - if (!mArm) {
> > > > > - //
> > > > > - // Update reset vector (SALE_ENTRY for IPF)
> > > > > - // Now for IA32 and IA64 platform, the fv which has bsf file must
> > have
> > > > the
> > > > > - // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to
> > update
> > > > the
> > > > > - // reset vector. If the PEI Core is found, the VTF file will probably
> > get
> > > > > - // corrupted by updating the entry point.
> > > > > - //
> > > > > - if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) ==
> > > > FV_IMAGES_TOP_ADDRESS) {
> > > > > - Status = UpdateResetVector (&FvImageMemoryFile,
> > &mFvDataInfo,
> > > > VtfFileImage);
> > > > > - if (EFI_ERROR(Status)) {
> > > > > - Error (NULL, 0, 3000, "Invalid", "Could not update the reset
> > > > vector.");
> > > > > - goto Finish;
> > > > > - }
> > > > > - DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> > > > > - }
> > > > > }
> > > > > + DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> > > > > + }
> > > > > }
> > > > > }
> > > > >
> > > > > @@ -3119,6 +3050,22 @@ Returns:
> > > > > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> > > > > FvHeader,
> > > > FvHeader->HeaderLength / sizeof (UINT16));
> > > > > }
> > > > >
> > > > > + if (mRiscV) {
> > > > > + //
> > > > > + // Update RISCV reset vector.
> > > > > + //
> > > > > + Status = UpdateRiscvResetVectorIfNeeded
> > > > > + (&FvImageMemoryFile,
> > > > &mFvDataInfo);
> > > > > + if (EFI_ERROR (Status)) {
> > > > > + Error (NULL, 0, 3000, "Invalid", "Could not update the
> > > > > + reset vector for
> > > > RISC-V.");
> > > > > + goto Finish;
> > > > > + }
> > > > > + //
> > > > > + // Update Checksum for FvHeader
> > > > > + //
> > > > > + FvHeader->Checksum = 0;
> > > > > + FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> > > > > + FvHeader,
> > > > > + FvHeader->HeaderLength / sizeof (UINT16)); }
> > > > > +
> > > > > //
> > > > > // Update FV Alignment attribute to the largest alignment of
> > > > > all the FFS
> > > > files in the FV
> > > > > //
> > > > > @@ -3853,7 +3800,7 @@ Returns:
> > > > > ImageContext.DestinationAddress = NewPe32BaseAddress;
> > > > > Status = PeCoffLoaderRelocateImage
> (&ImageContext);
> > > > > if (EFI_ERROR (Status)) {
> > > > > - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on
> > rebase of
> > > > %s", FileName);
> > > > > + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call
> > > > > + failed on rebase of %s Status=%d", FileName, Status);
> > > > > free ((VOID *) MemoryImagePointer);
> > > > > return Status;
> > > > > }
> > > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > > b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > > index 4857485..77b4d53 100644
> > > > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > > @@ -946,8 +946,60 @@ WriteSections64 (
> > > > > RiscvSymSecIndex = 0;
> > > > > break;
> > > > >
> > > > > + case R_RISCV_PCREL_HI20:
> > > > > + RiscvHi20Targ = Targ;
> > > > > + RiscvHi20Sym = SymShdr;
> > > > > + RiscvSymSecIndex = Sym->st_shndx;
> > > > > +
> > > > > + Value = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> > > > > + printf("PCREL_HI20 Sym:[%s] value:0x%x
> > > > > + SymShdr->sh_addr:0x%lx
> > > > mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr-
> > >sh_addr,
> > > > mCoffSectionsOffset[Sym->st_shndx]);
> > > > > + break;
> > > > > + case R_RISCV_PCREL_LO12_I:
> > > > > + if (RiscvHi20Targ != NULL && RiscvHi20Sym != NULL
> > > > > + &&
> > > > RiscvSymSecIndex != 0) {
> > > > > + int i;
> > > > > + Value2 = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> > > > > + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> > > > > + if(Value & (RISCV_IMM_REACH/2)) {
> > > > > + Value |= ~(RISCV_IMM_REACH-1);
> > > > > + }
> > > > > + printf("PCREL_LO12_I Sym:[%s] value:0x%x SymShdr-
> > > > >sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym),
> Value,
> > > > SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
> > > > > + Value = Value - RiscvHi20Sym->sh_addr +
> > > > mCoffSectionsOffset[RiscvSymSecIndex];
> > > > > + if(-2048 > (INT32)Value) {
> > > > > + i = (-Value / 4096);
> > > > > + //Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> > > > PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> > > > > + printf("WriteSections64(): PCREL_LO12_I
> > > > > + relocation out of
> > range.
> > > > Value:%d Value2:%d i=%d\n", Value, Value2, i);
> > > > > + Value2 -= i;
> > > > > + Value += 4096 * i;
> > > > > + if(-2048 > (INT32)Value) {
> > > > > + Value2 -= 1;
> > > > > + Value += 4096;
> > > > > + }
> > > > > + }
> > > > > + else if( 2047 < (INT32)Value) {
> > > > > + i = (Value / 4096);
> > > > > + //Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> > > > PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> > > > > + printf("WriteSections64(): PCREL_LO12_I
> > > > > + relocation out of
> > range.
> > > > Value:%d Value2:%d i=%d\n", Value, Value2, i);
> > > > > + Value2 += i;
> > > > > + Value -= 4096 * i;
> > > > > + if(2047 < (INT32)Value) {
> > > > > + Value2 += 1;
> > > > > + Value -= 4096;
> > > > > + }
> > > > > + }
> > > > > +
> > > > > + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) |
> > > > (RV_X(*(UINT32*)Targ, 0, 20));
> > > > > + *(UINT32 *)RiscvHi20Targ = (RV_X(Value2, 0,
> > > > > + 20)<<12) |
> > > > (RV_X(*(UINT32 *)RiscvHi20Targ, 0, 12));
> > > > > + printf("PCREL_LO12_I Sym:[%s] relocated
> > > > > + value:0x%x(%d)
> > > > value2:0x%x(%d) SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n",
> > > > GetSymName(Sym), Value, Value, Value2, Value2, SymShdr->sh_addr,
> > > > mCoffSectionsOffset[Sym->st_shndx]);
> > > > > + }
> > > > > + RiscvHi20Sym = NULL;
> > > > > + RiscvHi20Targ = NULL;
> > > > > + RiscvSymSecIndex = 0;
> > > > > + break;
> > > > > +
> > > > > case R_RISCV_ADD64:
> > > > > case R_RISCV_SUB64:
> > > > > + case R_RISCV_ADD32:
> > > > > + case R_RISCV_SUB32:
> > > > > case R_RISCV_BRANCH:
> > > > > case R_RISCV_JAL:
> > > > > case R_RISCV_GPREL_I:
> > > > > @@ -1120,6 +1172,20 @@ WriteRelocations64 (
> > > > > EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > > > break;
> > > > >
> > > > > + case R_RISCV_ADD32:
> > > > > + CoffAddFixup(
> > > > > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > > > > + + (Rel->r_offset - SecShdr->sh_addr)),
> > > > > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > > > + break;
> > > > > +
> > > > > + case R_RISCV_SUB32:
> > > > > + CoffAddFixup(
> > > > > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > > > > + + (Rel->r_offset - SecShdr->sh_addr)),
> > > > > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > > > + break;
> > > > > +
> > > > > case R_RISCV_BRANCH:
> > > > > CoffAddFixup(
> > > > > (UINT32) ((UINT64)
> > > > > mCoffSectionsOffset[RelShdr->sh_info]
> > > > > @@ -1145,6 +1211,8 @@ WriteRelocations64 (
> > > > > case R_RISCV_SET8:
> > > > > case R_RISCV_SET16:
> > > > > case R_RISCV_SET32:
> > > > > + case R_RISCV_PCREL_HI20:
> > > > > + case R_RISCV_PCREL_LO12_I:
> > > > > break;
> > > > >
> > > > > default:
> > > >
> > >
> >
>
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform
2019-09-04 11:18 ` Abner Chang
@ 2019-09-04 14:32 ` Jonathan Cameron
0 siblings, 0 replies; 19+ messages in thread
From: Jonathan Cameron @ 2019-09-04 14:32 UTC (permalink / raw)
To: Abner Chang; +Cc: devel
On Wed, 4 Sep 2019 11:18:40 +0000
Abner Chang <abner.chang@hpe.com> wrote:
> Hi Jonathan, I created a new branch "RISC-V-V2" on edk2-staging which is based on most recent EDK2 master and sent the patches based on it.
> This is easier for reviewers to review the changes for RISC-V EDK2 port. The original "RISC-V" branch has some stale implementation and may confuse people. This new branch on edk2-staging is much clear.
Much nicer indeed. Thanks!
Jonathan
>
> Thanks
> Abner
>
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Abner Chang
> > Sent: Wednesday, August 28, 2019 5:08 PM
> > To: Jonathan Cameron <jonathan.cameron@huawei.com>
> > Cc: devel@edk2.groups.io
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools:
> > Update EDK2 build tool for RISC-V platform
> >
> > > -----Original Message-----
> > > From: Jonathan Cameron [mailto:jonathan.cameron@huawei.com]
> > > Sent: Wednesday, August 28, 2019 5:00 PM
> > > To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> > > Cc: devel@edk2.groups.io
> > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools:
> > > Update EDK2 build tool for RISC-V platform
> > >
> > > On Wed, 28 Aug 2019 08:43:10 +0000
> > > "Chang, Abner (HPS SW/FW Technologist)" <abner.chang@hpe.com>
> > wrote:
> > >
> > > > Thanks Jonathan, the cover letter and 3/14 patch were just sent.
> > >
> > > Great. So am I right in thinking these apply to:
> > > INVALID URI REMOVED
> > > 3A__github.com_tianocore_edk2-2Dstaging_tree_RISC-
> > >
> > 2DV&d=DwICAg&c=C5b8zRQO1miGmBeVZ2LFWg&r=_SN6FZBN4Vgi4Ulkskz6
> > >
> > qU3NYRO03nHp9P7Z5q59A3E&m=4xGwArhbyMMHxteOpv4UP8PJWPKah5H
> > > fR_X2Dl0H8vE&s=sCxw_Qm3DjjrX9vULVZYYw6jqhmQWygJP-
> > B0Dltr6kc&e= ?
> > >
> > > Any plans to rebase that tree as it seems to be a few years old now?
> > Yes. we have plan to rebase it as you said this one is too old, will do it while
> > edk2 devel review those patches ( includes edk2-platform/devel-rsicv
> > patches)
> >
> > Thanks
> >
> > >
> > > Thanks,
> > >
> > > Jonathan
> > >
> > > >
> > > > Abner
> > > >
> > > > > -----Original Message-----
> > > > > From: Jonathan Cameron [mailto:jonathan.cameron@huawei.com]
> > > > > Sent: Wednesday, August 28, 2019 4:18 PM
> > > > > To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> > > > > Cc: devel@edk2.groups.io
> > > > > Subject: Re: [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]:
> > > BaseTools:
> > > > > Update EDK2 build tool for RISC-V platform
> > > > >
> > > > > Hi Abner,
> > > > >
> > > > > Just noticed in passing that this series doesn't seem to have a 3/14?
> > > > >
> > > > > Speaking personally it would be useful to have a cover letter with
> > > > > a quick summary of the series content.
> > > > >
> > > > > Thanks,
> > > > >
> > > > > Jonathan
> > > > >
> > > > > On Tue, 27 Aug 2019 14:00:19 +0800 Abner Chang
> > > > > <abner.chang@hpe.com> wrote:
> > > > >
> > > > > > Elf64Convert.c
> > > > > > - Relocation process to hadnle below opcodes,
> > > > > > * PCRELHI20
> > > > > > * PCRELLO12
> > > > > > * ADD32
> > > > > > * SUB32
> > > > > >
> > > > > > GenFvInternalLib.c
> > > > > > - This atches jump instrcution at the position of first
> > > > > > instrcution fetched by
> > > > > RISC-V processor after Zeroth Stage Boot Loader (ZSBL).
> > > > > >
> > > > > > Contributed-under: TianoCore Contribution Agreement 1.0
> > > > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > > > ---
> > > > > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 311
> > > > > > ++++++++++++------
> > > > > ----------
> > > > > > BaseTools/Source/C/GenFw/Elf64Convert.c | 68 ++++++
> > > > > > 2 files changed, 197 insertions(+), 182 deletions(-)
> > > > > >
> > > > > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > > > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > > > index 01da00c..92abb7c 100644
> > > > > > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > > > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> > > > > > @@ -1956,157 +1956,6 @@ Returns:
> > > > > > return EFI_UNSUPPORTED;
> > > > > > }
> > > > > >
> > > > > > -EFI_STATUS
> > > > > > -UpdateRiscvResetVectorIfNeeded (
> > > > > > - MEMORY_FILE *FvImage,
> > > > > > - FV_INFO *FvInfo,
> > > > > > - EFI_FFS_FILE_HEADER *VtfFileImage
> > > > > > - )
> > > > > > -/*++
> > > > > > -
> > > > > > -Routine Description:
> > > > > > - This parses the FV looking for SEC and patches that address
> > > > > > into the
> > > > > > - beginning of the FV header.
> > > > > > -
> > > > > > - For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > > > > > -
> > > > > > -Arguments:
> > > > > > - FvImage Memory file for the FV memory image/
> > > > > > - FvInfo Information read from INF file.
> > > > > > - VtfFileImage Instance of VTF file.
> > > > > > -
> > > > > > -Returns:
> > > > > > -
> > > > > > - EFI_SUCCESS Function Completed successfully.
> > > > > > - EFI_ABORTED Error encountered.
> > > > > > - EFI_INVALID_PARAMETER A required parameter was NULL.
> > > > > > - EFI_NOT_FOUND PEI Core file not found.
> > > > > > -
> > > > > > ---*/
> > > > > > -{
> > > > > > - EFI_FFS_FILE_HEADER *PeiCoreFile;
> > > > > > - EFI_FFS_FILE_HEADER *SecCoreFile;
> > > > > > - EFI_STATUS Status;
> > > > > > - EFI_FILE_SECTION_POINTER Pe32Section;
> > > > > > - UINT32 EntryPoint;
> > > > > > - UINT32 BaseOfCode;
> > > > > > - UINT16 MachineType;
> > > > > > - EFI_PHYSICAL_ADDRESS PeiCorePhysicalAddress;
> > > > > > - EFI_PHYSICAL_ADDRESS SecCorePhysicalAddress;
> > > > > > - EFI_PHYSICAL_ADDRESS TrapAddress;
> > > > > > -
> > > > > > - //
> > > > > > - // Verify input parameters
> > > > > > - //
> > > > > > - if (FvImage == NULL || FvInfo == NULL) {
> > > > > > - Error (NULL, 0, 3000, "Invalid", "FvImage or FvInfo is NULL");
> > > > > > - return EFI_INVALID_PARAMETER;
> > > > > > - }
> > > > > > - //
> > > > > > - // Initialize FV library
> > > > > > - //
> > > > > > - InitializeFvLib (FvImage->FileImage, FvInfo->Size);
> > > > > > -
> > > > > > - //
> > > > > > - // Find the Sec Core
> > > > > > - //
> > > > > > - Status = GetFileByType (EFI_FV_FILETYPE_SECURITY_CORE, 1,
> > > > > > &SecCoreFile);
> > > > > > - if (EFI_ERROR (Status) || SecCoreFile == NULL) {
> > > > > > - //
> > > > > > - // Maybe hardware does SEC job and we only have PEI Core?
> > > > > > - //
> > > > > > -
> > > > > > - //
> > > > > > - // Find the PEI Core. It may not exist if SEC loads DXE core directly
> > > > > > - //
> > > > > > - PeiCorePhysicalAddress = 0;
> > > > > > - Status = GetFileByType (EFI_FV_FILETYPE_PEI_CORE, 1,
> > > &PeiCoreFile);
> > > > > > - if (!EFI_ERROR(Status) && PeiCoreFile != NULL) {
> > > > > > - //
> > > > > > - // PEI Core found, now find PE32 or TE section
> > > > > > - //
> > > > > > - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_PE32, 1,
> > > > > &Pe32Section);
> > > > > > - if (Status == EFI_NOT_FOUND) {
> > > > > > - Status = GetSectionByType (PeiCoreFile, EFI_SECTION_TE, 1,
> > > > > &Pe32Section);
> > > > > > - }
> > > > > > -
> > > > > > - if (EFI_ERROR (Status)) {
> > > > > > - Error (NULL, 0, 3000, "Invalid", "could not find either a PE32 or a
> > TE
> > > > > section in PEI core file!");
> > > > > > - return EFI_ABORTED;
> > > > > > - }
> > > > > > -
> > > > > > - Status = GetPe32Info (
> > > > > > - (VOID *) ((UINTN) Pe32Section.Pe32Section +
> > > > > GetSectionHeaderLength(Pe32Section.CommonHeader)),
> > > > > > - &EntryPoint,
> > > > > > - &BaseOfCode,
> > > > > > - &MachineType
> > > > > > - );
> > > > > > -
> > > > > > - if (EFI_ERROR (Status)) {
> > > > > > - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry
> > point
> > > for
> > > > > the PEI core!");
> > > > > > - return EFI_ABORTED;
> > > > > > - }
> > > > > > - //
> > > > > > - // Physical address is FV base + offset of PE32 + offset of the entry
> > > > > point
> > > > > > - //
> > > > > > - PeiCorePhysicalAddress = FvInfo->BaseAddress;
> > > > > > - PeiCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section +
> > > > > GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN)
> > > FvImage-
> > > > > >FileImage;
> > > > > > - PeiCorePhysicalAddress += EntryPoint;
> > > > > > - DebugMsg (NULL, 0, 9, "PeiCore physical entry point address",
> > > > > "Address = 0x%llX", (unsigned long long) PeiCorePhysicalAddress);
> > > > > > - RiscvPatchVtf (VtfFileImage, (UINT32)PeiCorePhysicalAddress);
> > > > > > - }
> > > > > > - return EFI_SUCCESS;
> > > > > > - }
> > > > > > -
> > > > > > - //
> > > > > > - // Sec Core found, now find PE32 section
> > > > > > - //
> > > > > > - Status = GetSectionByType (SecCoreFile, EFI_SECTION_PE32, 1,
> > > > > > &Pe32Section);
> > > > > > - if (Status == EFI_NOT_FOUND) {
> > > > > > - Status = GetSectionByType (SecCoreFile, EFI_SECTION_TE, 1,
> > > > > &Pe32Section);
> > > > > > - }
> > > > > > -
> > > > > > - if (EFI_ERROR (Status)) {
> > > > > > - Error (NULL, 0, 3000, "Invalid", "could not find a PE32 section in the
> > > SEC
> > > > > core file.");
> > > > > > - return EFI_ABORTED;
> > > > > > - }
> > > > > > -
> > > > > > - Status = GetPe32Info (
> > > > > > - (VOID *) ((UINTN) Pe32Section.Pe32Section +
> > > > > GetSectionHeaderLength(Pe32Section.CommonHeader)),
> > > > > > - &EntryPoint,
> > > > > > - &BaseOfCode,
> > > > > > - &MachineType
> > > > > > - );
> > > > > > - if (EFI_ERROR (Status)) {
> > > > > > - Error (NULL, 0, 3000, "Invalid", "could not get the PE32 entry point
> > for
> > > > > the SEC core.");
> > > > > > - return EFI_ABORTED;
> > > > > > - }
> > > > > > -
> > > > > > - if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) &&
> > > > > (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > > > > > - //
> > > > > > - // If SEC is not RISC-V we have nothing to do
> > > > > > - //
> > > > > > - return EFI_SUCCESS;
> > > > > > - }
> > > > > > -
> > > > > > - //
> > > > > > - // Physical address is FV base + offset of PE32 + offset of
> > > > > > the entry point
> > > > > > - //
> > > > > > - SecCorePhysicalAddress = FvInfo->BaseAddress;
> > > > > > - SecCorePhysicalAddress += (UINTN) Pe32Section.Pe32Section +
> > > > > > GetSectionHeaderLength(Pe32Section.CommonHeader) - (UINTN)
> > > > > > FvImage->FileImage;
> > > > > > - SecCorePhysicalAddress += EntryPoint;
> > > > > > - DebugMsg (NULL, 0, 0x14, "SecCore physical entry point
> > > > > > address", "Address = 0x%llX", (unsigned long long)
> > > > > > SecCorePhysicalAddress);
> > > > > > - RiscvPatchVtf (VtfFileImage, (UINT32)SecCorePhysicalAddress);
> > > > > > - //
> > > > > > - // Update RISC-V trap handler.
> > > > > > - //
> > > > > > - TrapAddress = (UINTN) Pe32Section.Pe32Section +
> > > > > > GetSectionHeaderLength(Pe32Section.CommonHeader) + EntryPoint;
> > > > > > - TrapAddress -= 40;
> > > > > > - RiscvPatchVtfTrapHandler (VtfFileImage, TrapAddress);
> > > > > > -
> > > > > > - DebugMsg (NULL, 0, 9, "Update Reset vector in FV Header",
> > > > > > NULL);
> > > > > > - return EFI_SUCCESS;
> > > > > > -}
> > > > > >
> > > > > > EFI_STATUS
> > > > > > FindCorePeSection(
> > > > > > @@ -2581,6 +2430,106 @@ Returns:
> > > > > > }
> > > > > >
> > > > > > EFI_STATUS
> > > > > > +UpdateRiscvResetVectorIfNeeded (
> > > > > > + MEMORY_FILE *FvImage,
> > > > > > + FV_INFO *FvInfo
> > > > > > + )
> > > > > > +/*++
> > > > > > +
> > > > > > +Routine Description:
> > > > > > + This parses the FV looking for SEC and patches that address
> > > > > > +into the
> > > > > > + beginning of the FV header.
> > > > > > +
> > > > > > + For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
> > > > > > +
> > > > > > +Arguments:
> > > > > > + FvImage Memory file for the FV memory image/
> > > > > > + FvInfo Information read from INF file.
> > > > > > +
> > > > > > +Returns:
> > > > > > +
> > > > > > + EFI_SUCCESS Function Completed successfully.
> > > > > > + EFI_ABORTED Error encountered.
> > > > > > + EFI_INVALID_PARAMETER A required parameter was NULL.
> > > > > > + EFI_NOT_FOUND PEI Core file not found.
> > > > > > +
> > > > > > +--*/
> > > > > > +{
> > > > > > + EFI_STATUS Status;
> > > > > > + UINT16 MachineType;
> > > > > > + EFI_FILE_SECTION_POINTER SecPe32;
> > > > > > + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
> > > > > > +
> > > > > > + UINT32 bSecCore;
> > > > > > + UINT32 tmp;
> > > > > > +
> > > > > > +
> > > > > > + //
> > > > > > + // Verify input parameters
> > > > > > + //
> > > > > > + if (FvImage == NULL || FvInfo == NULL) {
> > > > > > + return EFI_INVALID_PARAMETER; } // // Initialize FV
> > > > > > + library // InitializeFvLib (FvImage->FileImage,
> > > > > > + FvInfo->Size);
> > > > > > +
> > > > > > + //
> > > > > > + // Find the Sec Core
> > > > > > + //
> > > > > > + Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size,
> > > > > > + EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
> > > > > > + if(EFI_ERROR(Status)) {
> > > > > > + printf("skip because Secutiry Core not found\n");
> > > > > > + return EFI_SUCCESS;
> > > > > > + }
> > > > > > +
> > > > > > + DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
> > > > > > +
> > > > > > + Status = GetCoreMachineType(SecPe32, &MachineType);
> > > > > > + if(EFI_ERROR(Status)) {
> > > > > > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32
> > > > > > + machine type for
> > > > > SEC core.");
> > > > > > + return EFI_ABORTED;
> > > > > > + }
> > > > > > +
> > > > > > + if ((MachineType != EFI_IMAGE_MACHINE_RISCV32) &&
> > > > > (MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
> > > > > > + Error(NULL, 0, 3000, "Invalid", "Could not update SEC core
> > > > > > + because
> > > > > Machine type is not RiscV.");
> > > > > > + return EFI_ABORTED;
> > > > > > + }
> > > > > > +
> > > > > > + Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo,
> > > > > > + SecPe32, &SecCoreEntryAddress);
> > > > > > + if(EFI_ERROR(Status)) {
> > > > > > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32
> > > > > > + entry point
> > > > > address for SEC Core.");
> > > > > > + return EFI_ABORTED;
> > > > > > + }
> > > > > > +
> > > > > > + VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned
> > > > > > + long
> > > > > > + long) SecCoreEntryAddress); VerboseMsg("BaseAddress =
> > > > > > + 0x%llX", (unsigned long long) FvInfo->BaseAddress); bSecCore
> > > > > > + = (SecCoreEntryAddress - FvInfo->BaseAddress);
> > > > > > + VerboseMsg("offset = 0x%llX", bSecCore);
> > > > > > +
> > > > > > + if(bSecCore > 0x0fffff) {
> > > > > > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be
> > > > > > + within 1MB of
> > > > > start of the FV");
> > > > > > + return EFI_ABORTED;
> > > > > > + }
> > > > > > +
> > > > > > + tmp = bSecCore;
> > > > > > + bSecCore = 0;
> > > > > > + //J-type
> > > > > > + bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
> > > > > > + bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
> > > > > > + bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
> > > > > > + bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
> > > > > > + bSecCore |= 0x6F; //JAL opcode
> > > > > > +
> > > > > > + memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
> > > > > > +
> > > > > > + return EFI_SUCCESS;
> > > > > > +}
> > > > > > +
> > > > > > +
> > > > > > +
> > > > > > +EFI_STATUS
> > > > > > GetPe32Info (
> > > > > > IN UINT8 *Pe32,
> > > > > > OUT UINT32 *EntryPoint,
> > > > > > @@ -3037,7 +2986,6 @@ Returns:
> > > > > > FvHeader->Checksum = 0;
> > > > > > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> > > FvHeader,
> > > > > FvHeader->HeaderLength / sizeof (UINT16));
> > > > > > }
> > > > > > -
> > > > > > //
> > > > > > // Add files to FV
> > > > > > //
> > > > > > @@ -3069,39 +3017,22 @@ Returns:
> > > > > > goto Finish;
> > > > > > }
> > > > > >
> > > > > > - if (mRiscV) {
> > > > > > + if (!mArm && !mRiscV) {
> > > > > > //
> > > > > > - // Update RISCV reset vector.
> > > > > > + // Update reset vector (SALE_ENTRY for IPF)
> > > > > > + // Now for IA32 and IA64 platform, the fv which has bsf
> > > > > > + file must have
> > > > > the
> > > > > > + // EndAddress of 0xFFFFFFFF. Thus, only this type fv
> > > > > > + needs to update
> > > > > the
> > > > > > + // reset vector. If the PEI Core is found, the VTF file
> > > > > > + will probably
> > > get
> > > > > > + // corrupted by updating the entry point.
> > > > > > //
> > > > > > - DebugMsg (NULL, 0, INFO_LOG_LEVEL, "Update RISCV reset
> > > vector",
> > > > > NULL);
> > > > > > - Status = UpdateRiscvResetVectorIfNeeded
> > (&FvImageMemoryFile,
> > > > > &mFvDataInfo, VtfFileImage);
> > > > > > - if (EFI_ERROR (Status)) {
> > > > > > - Error (NULL, 0, 3000, "Invalid", "Could not update the reset
> > vector
> > > for
> > > > > RISC-V.");
> > > > > > + if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) ==
> > > > > FV_IMAGES_TOP_ADDRESS) {
> > > > > > + Status = UpdateResetVector (&FvImageMemoryFile,
> > > > > > + &mFvDataInfo,
> > > > > VtfFileImage);
> > > > > > + if (EFI_ERROR(Status)) {
> > > > > > + Error (NULL, 0, 3000, "Invalid", "Could not update
> > > > > > + the reset vector.");
> > > > > > goto Finish;
> > > > > > - }
> > > > > > - //
> > > > > > - // Update Checksum for FvHeader
> > > > > > - //
> > > > > > - FvHeader->Checksum = 0;
> > > > > > - FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> > > FvHeader,
> > > > > FvHeader->HeaderLength / sizeof (UINT16));
> > > > > > - } else {
> > > > > > - if (!mArm) {
> > > > > > - //
> > > > > > - // Update reset vector (SALE_ENTRY for IPF)
> > > > > > - // Now for IA32 and IA64 platform, the fv which has bsf file must
> > > have
> > > > > the
> > > > > > - // EndAddress of 0xFFFFFFFF. Thus, only this type fv needs to
> > > update
> > > > > the
> > > > > > - // reset vector. If the PEI Core is found, the VTF file will probably
> > > get
> > > > > > - // corrupted by updating the entry point.
> > > > > > - //
> > > > > > - if ((mFvDataInfo.BaseAddress + mFvDataInfo.Size) ==
> > > > > FV_IMAGES_TOP_ADDRESS) {
> > > > > > - Status = UpdateResetVector (&FvImageMemoryFile,
> > > &mFvDataInfo,
> > > > > VtfFileImage);
> > > > > > - if (EFI_ERROR(Status)) {
> > > > > > - Error (NULL, 0, 3000, "Invalid", "Could not update the reset
> > > > > vector.");
> > > > > > - goto Finish;
> > > > > > - }
> > > > > > - DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> > > > > > - }
> > > > > > }
> > > > > > + DebugMsg (NULL, 0, 9, "Update Reset vector in VTF file", NULL);
> > > > > > + }
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > @@ -3119,6 +3050,22 @@ Returns:
> > > > > > FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> > > > > > FvHeader,
> > > > > FvHeader->HeaderLength / sizeof (UINT16));
> > > > > > }
> > > > > >
> > > > > > + if (mRiscV) {
> > > > > > + //
> > > > > > + // Update RISCV reset vector.
> > > > > > + //
> > > > > > + Status = UpdateRiscvResetVectorIfNeeded
> > > > > > + (&FvImageMemoryFile,
> > > > > &mFvDataInfo);
> > > > > > + if (EFI_ERROR (Status)) {
> > > > > > + Error (NULL, 0, 3000, "Invalid", "Could not update the
> > > > > > + reset vector for
> > > > > RISC-V.");
> > > > > > + goto Finish;
> > > > > > + }
> > > > > > + //
> > > > > > + // Update Checksum for FvHeader
> > > > > > + //
> > > > > > + FvHeader->Checksum = 0;
> > > > > > + FvHeader->Checksum = CalculateChecksum16 ((UINT16 *)
> > > > > > + FvHeader,
> > > > > > + FvHeader->HeaderLength / sizeof (UINT16)); }
> > > > > > +
> > > > > > //
> > > > > > // Update FV Alignment attribute to the largest alignment of
> > > > > > all the FFS
> > > > > files in the FV
> > > > > > //
> > > > > > @@ -3853,7 +3800,7 @@ Returns:
> > > > > > ImageContext.DestinationAddress = NewPe32BaseAddress;
> > > > > > Status = PeCoffLoaderRelocateImage
> > (&ImageContext);
> > > > > > if (EFI_ERROR (Status)) {
> > > > > > - Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on
> > > rebase of
> > > > > %s", FileName);
> > > > > > + Error (NULL, 0, 3000, "Invalid", "RelocateImage() call
> > > > > > + failed on rebase of %s Status=%d", FileName, Status);
> > > > > > free ((VOID *) MemoryImagePointer);
> > > > > > return Status;
> > > > > > }
> > > > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > > > b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > > > index 4857485..77b4d53 100644
> > > > > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> > > > > > @@ -946,8 +946,60 @@ WriteSections64 (
> > > > > > RiscvSymSecIndex = 0;
> > > > > > break;
> > > > > >
> > > > > > + case R_RISCV_PCREL_HI20:
> > > > > > + RiscvHi20Targ = Targ;
> > > > > > + RiscvHi20Sym = SymShdr;
> > > > > > + RiscvSymSecIndex = Sym->st_shndx;
> > > > > > +
> > > > > > + Value = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> > > > > > + printf("PCREL_HI20 Sym:[%s] value:0x%x
> > > > > > + SymShdr->sh_addr:0x%lx
> > > > > mCoffSectionOffset:%x \n", GetSymName(Sym), Value, SymShdr-
> > > >sh_addr,
> > > > > mCoffSectionsOffset[Sym->st_shndx]);
> > > > > > + break;
> > > > > > + case R_RISCV_PCREL_LO12_I:
> > > > > > + if (RiscvHi20Targ != NULL && RiscvHi20Sym != NULL
> > > > > > + &&
> > > > > RiscvSymSecIndex != 0) {
> > > > > > + int i;
> > > > > > + Value2 = (UINT32)(RV_X(*(UINT32 *)RiscvHi20Targ, 12, 20));
> > > > > > + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> > > > > > + if(Value & (RISCV_IMM_REACH/2)) {
> > > > > > + Value |= ~(RISCV_IMM_REACH-1);
> > > > > > + }
> > > > > > + printf("PCREL_LO12_I Sym:[%s] value:0x%x SymShdr-
> > > > > >sh_addr:0x%lx mCoffSectionOffset:%x \n", GetSymName(Sym),
> > Value,
> > > > > SymShdr->sh_addr, mCoffSectionsOffset[Sym->st_shndx]);
> > > > > > + Value = Value - RiscvHi20Sym->sh_addr +
> > > > > mCoffSectionsOffset[RiscvSymSecIndex];
> > > > > > + if(-2048 > (INT32)Value) {
> > > > > > + i = (-Value / 4096);
> > > > > > + //Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> > > > > PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> > > > > > + printf("WriteSections64(): PCREL_LO12_I
> > > > > > + relocation out of
> > > range.
> > > > > Value:%d Value2:%d i=%d\n", Value, Value2, i);
> > > > > > + Value2 -= i;
> > > > > > + Value += 4096 * i;
> > > > > > + if(-2048 > (INT32)Value) {
> > > > > > + Value2 -= 1;
> > > > > > + Value += 4096;
> > > > > > + }
> > > > > > + }
> > > > > > + else if( 2047 < (INT32)Value) {
> > > > > > + i = (Value / 4096);
> > > > > > + //Error (NULL, 0, 3000, "Invalid", "WriteSections64():
> > > > > PCREL_LO12_I relocation out of range. %d i=%d", Value, i);
> > > > > > + printf("WriteSections64(): PCREL_LO12_I
> > > > > > + relocation out of
> > > range.
> > > > > Value:%d Value2:%d i=%d\n", Value, Value2, i);
> > > > > > + Value2 += i;
> > > > > > + Value -= 4096 * i;
> > > > > > + if(2047 < (INT32)Value) {
> > > > > > + Value2 += 1;
> > > > > > + Value -= 4096;
> > > > > > + }
> > > > > > + }
> > > > > > +
> > > > > > + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) |
> > > > > (RV_X(*(UINT32*)Targ, 0, 20));
> > > > > > + *(UINT32 *)RiscvHi20Targ = (RV_X(Value2, 0,
> > > > > > + 20)<<12) |
> > > > > (RV_X(*(UINT32 *)RiscvHi20Targ, 0, 12));
> > > > > > + printf("PCREL_LO12_I Sym:[%s] relocated
> > > > > > + value:0x%x(%d)
> > > > > value2:0x%x(%d) SymShdr->sh_addr:0x%lx mCoffSectionOffset:%x \n",
> > > > > GetSymName(Sym), Value, Value, Value2, Value2, SymShdr->sh_addr,
> > > > > mCoffSectionsOffset[Sym->st_shndx]);
> > > > > > + }
> > > > > > + RiscvHi20Sym = NULL;
> > > > > > + RiscvHi20Targ = NULL;
> > > > > > + RiscvSymSecIndex = 0;
> > > > > > + break;
> > > > > > +
> > > > > > case R_RISCV_ADD64:
> > > > > > case R_RISCV_SUB64:
> > > > > > + case R_RISCV_ADD32:
> > > > > > + case R_RISCV_SUB32:
> > > > > > case R_RISCV_BRANCH:
> > > > > > case R_RISCV_JAL:
> > > > > > case R_RISCV_GPREL_I:
> > > > > > @@ -1120,6 +1172,20 @@ WriteRelocations64 (
> > > > > > EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > > > > break;
> > > > > >
> > > > > > + case R_RISCV_ADD32:
> > > > > > + CoffAddFixup(
> > > > > > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > > > > > + + (Rel->r_offset - SecShdr->sh_addr)),
> > > > > > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > > > > + break;
> > > > > > +
> > > > > > + case R_RISCV_SUB32:
> > > > > > + CoffAddFixup(
> > > > > > + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
> > > > > > + + (Rel->r_offset - SecShdr->sh_addr)),
> > > > > > + EFI_IMAGE_REL_BASED_ABSOLUTE);
> > > > > > + break;
> > > > > > +
> > > > > > case R_RISCV_BRANCH:
> > > > > > CoffAddFixup(
> > > > > > (UINT32) ((UINT64)
> > > > > > mCoffSectionsOffset[RelShdr->sh_info]
> > > > > > @@ -1145,6 +1211,8 @@ WriteRelocations64 (
> > > > > > case R_RISCV_SET8:
> > > > > > case R_RISCV_SET16:
> > > > > > case R_RISCV_SET32:
> > > > > > + case R_RISCV_PCREL_HI20:
> > > > > > + case R_RISCV_PCREL_LO12_I:
> > > > > > break;
> > > > > >
> > > > > > default:
> > > > >
> > > >
> > >
> >
> >
> >
>
>
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2019-09-04 14:33 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-08-27 6:00 [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for RISC-V platform Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 2/14]: BaseTools/Conf: Update build flags for RISC-V RV64 Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 4/14]: MdePkg/Include: Update SmBios header file Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 5/14]: RiscVPkg/Include: Add/Update header files of RISC-V CPU package Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 6/14]: RiscVPkg/opesbi: Add opensbi-HOWTO.txt Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 7/14]: RiscVPkg/RealTimeClockRuntimeDxe: Add RISC-V RTC Runtime Driver Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 8/14]: RiscVPkg/Universal: Remove stale moudles Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 9/14]: RiscVPkg/CpuDxe: Use RISC-V platform level timer library Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 10/14]: RiscVPkg/SmbiosDxe: RISC-V platform generic SMBIOS DXE driver Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 11/14]: RiscVPkg: Updates for supporting RISC-V OpenSBI Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 12/14]: RiscVVirtPkg: Remove RISC-V virtual package Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 13/14]: RiscVPkg/Library: Add/Update/Remove Library instances for RISC-V platform Abner Chang
2019-08-27 6:00 ` [edk2-staging/RISC-V PATCH v1 14/14]: MdeModulePkg/DxeIplPeim: Abstract platform DXEIPL on " Abner Chang
2019-08-28 8:17 ` [edk2-devel] [edk2-staging/RISC-V PATCH v1 1/14]: BaseTools: Update EDK2 build tool for " jonathan.cameron
2019-08-28 8:43 ` Abner Chang
2019-08-28 8:59 ` Jonathan Cameron
2019-08-28 9:08 ` Abner Chang
[not found] ` <15BF0B00F4581767.2982@groups.io>
2019-09-04 11:18 ` Abner Chang
2019-09-04 14:32 ` Jonathan Cameron
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