[edk2-staging/RISC-V-V2 PATCH v1 09/22]: MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.

["Abner Chang" <abner.chang@hpe.com>]

Implement RISC-V CPU related functions in BaseCpuLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
 MdePkg/Library/BaseCpuLib/BaseCpuLib.inf |  4 ++++
 MdePkg/Library/BaseCpuLib/RiscV/Cpu.s    | 25 +++++++++++++++++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.s

diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index a7cb381..20ee774 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -7,6 +7,7 @@
 #  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
 #  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 #  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -59,6 +60,9 @@
   AArch64/CpuFlushTlb.asm | MSFT
   AArch64/CpuSleep.asm    | MSFT
 
+[Sources.RISCV64]
+  RiscV/Cpu.s
+
 [Packages]
   MdePkg/MdePkg.dec
 
diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.s b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.s
new file mode 100644
index 0000000..9a1bf0f
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.s
@@ -0,0 +1,25 @@
+//------------------------------------------------------------------------------
+//
+// CpuSleep for RISC-V
+//
+// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+.data
+.align 3
+.section .text
+
+.global ASM_PFX(_CpuSleep)
+
+ASM_PFX(_CpuSleep):
+    wfi
+    ret
+
+
-- 
2.7.4