From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0150651a61=abner.chang@hpe.com) Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:49 -0700 Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBfPI020087 for ; Wed, 4 Sep 2019 11:13:48 GMT Received: from g2t2354.austin.hpe.com (g2t2354.austin.hpe.com [15.233.44.27]) by mx0a-002e3701.pphosted.com with ESMTP id 2ut9h9h7y2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:48 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2354.austin.hpe.com (Postfix) with ESMTP id BA5FEAE for ; Wed, 4 Sep 2019 11:13:47 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id D19F839; Wed, 4 Sep 2019 11:13:46 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-staging/RISC-V-V2 PATCH v1 18/22]: RiscVPkg/Library: Add/Update/Remove Library instances for RISC-V platform Date: Wed, 4 Sep 2019 18:43:13 +0800 Message-Id: <1567593797-26216-19-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-09-04_03:2019-09-03,2019-09-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 suspectscore=4 adultscore=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1906280000 definitions=main-1909040113 RiscVCpuLib: Add RISC-V CPU Library. - This library provides CSR assembly functions to read/write RISC-V specific Control and Status registers. RiscVDxeIplHandoffLib RiscVDxeIplHandoffOpenSbiLib - Provide DxeIpl platform implementation-specifc library for RISC-V platform. Two libraries are provided in this commit, * Defualt library which simply switch stack and transfer control to DXE core. * Switch stack, privilege mode and then transfer control to DXE core through RISC-V opensbi. RiscvOpensbiLib - EDK2 RISC-V OpenSBI library which pull in external source files under RiscVPkg/opensbi to the build process. PeiServicesTablePointerLibOpenSbi - Library instance of PEI Service Table for RISC-V platform based on OpenSBI. RiscVPlatformTempMemoryInitLibNull - NULL lib to return temporary memory information. RiscVDxeIplHandoffOpenSbiLib - This is the instance of platform level DXE IPL library based on RISC-V OpenSBI implementation. RiscVExceptionLib - Initial RISC-V Supervisor Mode trap handler RiscVTimerLib - Add RiscVTimerLib library. - Due to RISC-V timer CSR is platform implementation specific, RISC-V timer library invokes platform level timer library mputo access to timer CSRs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- .../PeiServicesTablePointerLibOpenSbi.inf | 45 +++++ .../PeiServicesTablePointerLibOpenSbi.uni | Bin 0 -> 2462 bytes .../PeiServicesTablePointerOpenSbi.c | 127 +++++++++++++ RiscVPkg/Library/RiscVCpuLib/Cpu.s | 121 +++++++++++++ RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 46 +++++ .../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 47 +++++ .../RiscVDxeIplHandoffLib.inf | 39 ++++ .../RiscVDxeIplHandoffOpenSbiLib.c | 108 +++++++++++ .../RiscVDxeIplHandoffOpenSbiLib.inf | 39 ++++ .../RiscVExceptionLib/CpuExceptionHandler.s | 94 ++++++++++ .../CpuExceptionHandlerDxeLib.inf | 47 +++++ .../RiscVExceptionLib/CpuExceptionHandlerLib.c | 187 +++++++++++++++++++ .../RiscVExceptionLib/CpuExceptionHandlerLib.uni | Bin 0 -> 1516 bytes .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 65 +++++++ .../RiscVPlatformTempMemoryInitLibNull.inf | 42 +++++ .../Riscv64/TempMemInit.s | 31 ++++ .../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 40 ++++ RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 201 +++++++++++++++++++++ RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h | 26 +++ 19 files changed, 1305 insertions(+) create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.s create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf create mode 100644 RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf new file mode 100644 index 0000000..c49377b --- /dev/null +++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf @@ -0,0 +1,45 @@ +## @file +# Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext. +# +# PEI Services Table Pointer Library implementation that retrieves a pointer to the +# PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiServicesTablePointerLibOpenSbi + MODULE_UNI_FILE = PeiServicesTablePointerLibOpenSbi.uni + FILE_GUID = B4054E46-FE75-4290-B442-4836B1265D8F + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE + + CONSTRUCTOR = PeiServicesTablePointerLibOpenSbiConstructor + +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + PeiServicesTablePointerOpenSbi.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[Pcd] + +[LibraryClasses] + DebugLib + RiscVCpuLib + RiscVOpensbiLib diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni new file mode 100644 index 0000000000000000000000000000000000000000..e7a0c4702e4b6db9a4dd433d212f34195baf6290 GIT binary patch literal 2462 zcmchZ+iwy<6vof9iT}fdzNl$IebX2tSZaw{2&Gn^8tx@>%d)igpI3k18J2}wZDXn- zyR$QMF5i6TGW_^nvXTX!C;WoFv4M?jY<+uZ4_Ga&$6z&^+QL$6Gj@>(HbXjC!>a5B zJ7z7h3-qx_#tkE4$yYUR)#2PHj3*R@C1C`#@7O#M|S4eg?NCb_zNEEO(p}8+vGBMyc1&6MQ`aR zyNO>#U``Zu<{>T&23`z7ganzZW7`-0aSzhW)u}U+&3U##4s_HMtl4HGeF1oybJ*_fY7G*2)C12_Z z;=V(MWPTNw){3(M>oG#YtQx(JX`7b-yKV0Y9cM)O8W|9xbc0uAT1q5ddZ$tjMs6ja z`00x1Cd9LJjr#>F9gz3vG27mYSUKm(^IRu6BsW!?O}f!L-evp9TwO}}sj=lg@6KIz`n!ukGa4YjDvZpX76Y zgSR}VbhpHtL~D9>)>#v)C-QfOr8+iFuvVpGl{tIdDZ^F^1i$<3c)iHhk{lU&-Y6IL zuqC7g(EYF5YY3JZ*`+QJ=sv1`^@QvujQuz3{2KGU?K`62T-}{7Wt;9z-Jgwhgm2>P zcD}Oey`S6tU*4U6cW3@NO6p%nL{Yt}?J?Z$$nox;Akp*gmiI+ + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Caches a pointer PEI Services Table. + + Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer + in a CPU specific manner as specified in the CPU binding section of the Platform Initialization + Pre-EFI Initialization Core Interface Specification. + + If PeiServicesTablePointer is NULL, then ASSERT(). + + @param PeiServicesTablePointer The address of PeiServices pointer. +**/ +VOID +EFIAPI +SetPeiServicesTablePointer ( + IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer + ) +{ + struct sbi_platform *ThisSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + + ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr()); + FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context; + FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer; + + DEBUG ((EFI_D_ERROR, "[OpenSBI]: Set PEI Service 0x%x at Firmware Context at 0x%x\n", + PeiServicesTablePointer, + ThisSbiPlatform->firmware_context + )); +} + +/** + Retrieves the cached value of the PEI Services Table pointer. + + Returns the cached value of the PEI Services Table pointer in a CPU specific manner + as specified in the CPU binding section of the Platform Initialization Pre-EFI + Initialization Core Interface Specification. + + If the cached PEI Services Table pointer is NULL, then ASSERT(). + + @return The pointer to PeiServices. + +**/ +CONST EFI_PEI_SERVICES ** +EFIAPI +GetPeiServicesTablePointer ( + VOID + ) +{ + struct sbi_platform *ThisSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + + ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr()); + FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context; + return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable; +} + +/** + The constructor function caches the pointer to PEI services. + + The constructor function caches the pointer to PEI services. + It will always return EFI_SUCCESS. + + @param FileHandle The handle of FFS header the loaded driver. + @param PeiServices The pointer to the PEI services. + + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +PeiServicesTablePointerLibOpenSbiConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + SetPeiServicesTablePointer (PeiServices); + return EFI_SUCCESS; +} + +/** + Perform CPU specific actions required to migrate the PEI Services Table + pointer from temporary RAM to permanent RAM. + + For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes + immediately preceding the Interrupt Descriptor Table (IDT) in memory. + For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes + immediately preceding the Interrupt Descriptor Table (IDT) in memory. + For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in + a dedicated CPU register. This means that there is no memory storage + associated with storing the PEI Services Table pointer, so no additional + migration actions are required for Itanium or ARM CPUs. + +**/ +VOID +EFIAPI +MigratePeiServicesTablePointer ( + VOID + ) +{ + // + // PEI Services Table pointer is cached in the global variable. No additional + // migration actions are required. + // + return; +} diff --git a/RiscVPkg/Library/RiscVCpuLib/Cpu.s b/RiscVPkg/Library/RiscVCpuLib/Cpu.s new file mode 100644 index 0000000..ccd7e87 --- /dev/null +++ b/RiscVPkg/Library/RiscVCpuLib/Cpu.s @@ -0,0 +1,121 @@ +//------------------------------------------------------------------------------ +// +// RISC-V CPU functions. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +//------------------------------------------------------------------------------ +#include +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVSetScratch) +.global ASM_PFX(RiscVGetScratch) +.global ASM_PFX(RiscVGetMachineTrapCause) +.global ASM_PFX(RiscVReadMachineIE) +.global ASM_PFX(RiscVReadMachineIP) +.global ASM_PFX(RiscVReadMachineStatus) +.global ASM_PFX(RiscVWriteMachineStatus) +.global ASM_PFX(RiscVReadMachineTvec) +.global ASM_PFX(RiscVReadMisa) +.global ASM_PFX(RiscVReadMVendorId) +.global ASM_PFX(RiscVReadMArchId) +.global ASM_PFX(RiscVReadMImplId) +// +// Set machine mode scratch. +// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_PFX (RiscVSetScratch): + csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0 + ret + +// +// Get machine mode scratch. +// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT. +// +ASM_PFX (RiscVGetScratch): + csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0 + ret + +// +// Get machine trap cause CSR. +// +ASM_PFX (RiscVGetMachineTrapCause): + csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0 + ret + +// +// Get machine interrupt enable +// +ASM_PFX (RiscVReadMachineIE): + csrr a0, RISCV_CSR_MACHINE_MIE + ret + +// +// Get machine interrupt pending +// +ASM_PFX (RiscVReadMachineIP): + csrr a0, RISCV_CSR_MACHINE_MIP + ret + +// +// Get machine status +// +ASM_PFX(RiscVReadMachineStatus): + csrr a0, RISCV_CSR_MACHINE_MSTATUS + ret + +// +// Set machine status +// +ASM_PFX(RiscVWriteMachineStatus): + csrw RISCV_CSR_MACHINE_MSTATUS, a0 + ret + +// +// Get machine trap vector +// +ASM_PFX(RiscVReadMachineTvec): + csrr a0, RISCV_CSR_MACHINE_MTVEC + ret + +// +// Read machine ISA +// +ASM_PFX(RiscVReadMisa): + csrr a0, RISCV_CSR_MACHINE_MISA + ret + +// +// Read machine vendor ID +// +ASM_PFX(RiscVReadMVendorId): + csrr a0, RISCV_CSR_MACHINE_MVENDORID + ret + +// +// Read machine architecture ID +// +ASM_PFX(RiscVReadMArchId): + csrr a0, RISCV_CSR_MACHINE_MARCHID + ret + +// +// Read machine implementation ID +// +ASM_PFX(RiscVReadMImplId): + csrr a0, RISCV_CSR_MACHINE_MIMPID + ret + diff --git a/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf new file mode 100644 index 0000000..2d8a32d --- /dev/null +++ b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf @@ -0,0 +1,46 @@ +## @file +# Memory Status Code Library for UEFI drivers +# +# Lib to provide memory journal status code reporting Routines +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
+# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = RiscVCpuLib + FILE_GUID = 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RiscVCpuLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV32 RISCV64 +# + +[Sources] + +[Sources.RISCV32] + Cpu.s + +[Sources.RISCV64] + Cpu.s + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + + diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c new file mode 100644 index 0000000..309cb19 --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c @@ -0,0 +1,47 @@ +/** @file + RISC-V platform level DXE core hand off library + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +/** + RISC-V platform DXE IPL to DXE core handoff process. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ + +VOID +RiscVPlatformHandOffToDxeCore ( + IN VOID *BaseOfStack, + IN VOID *TopOfStack, + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ) +{ + + // + // Transfer the control to the entry point of DxeCore. + // + SwitchStack ( + (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint, + HobList.Raw, + NULL, + TopOfStack + ); +} diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf new file mode 100644 index 0000000..62599ac --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf @@ -0,0 +1,39 @@ +## @file +# Instance of RISC-V DXE IPL to DXE core handoff platform library +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = RiscVPlatformDxeIplLib + FILE_GUID = 2A77EE71-9F55-43F9-8773-7854A5B56086 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE + +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + RiscVDxeIplHandoffLib.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + DebugLib + RiscVCpuLib + RiscVOpensbiLib + +[Pcd] diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c new file mode 100644 index 0000000..37b4d32 --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c @@ -0,0 +1,108 @@ +/** @file + RISC-V DXE IPL to DXE core handoff platform library using OpenSBI + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/** + RISC-V platform DXE IPL to DXE OpenSBI mdoe switch handler. + This function is executed in RISC-V Supervisor mode. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ +VOID +RiscVDxeIplHandoffOpenSbiHandler ( + IN UINTN HardId, + IN OPENSBI_SWITCH_MODE_CONTEXT *ThisSwitchContext + ) +{ + DEBUG ((EFI_D_INFO, "[OpenSBI]: OpenSBI mode switch DXE IPL Handoff handler entry\n")); + + SwitchStack ( + (SWITCH_STACK_ENTRY_POINT)(UINTN)ThisSwitchContext->DxeCoreEntryPoint, + ThisSwitchContext->HobList.Raw, + NULL, + ThisSwitchContext->TopOfStack + ); + + // + // Shold never came back. + // + __builtin_unreachable(); +} + + +/** + RISC-V platform DXE IPL to DXE core handoff process. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ +VOID +RiscVPlatformHandOffToDxeCore ( + IN VOID *BaseOfStack, + IN VOID *TopOfStack, + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ) +{ + struct sbi_scratch *ThisScratch; + OPENSBI_SWITCH_MODE_CONTEXT OpenSbiSwitchModeContext; + + DEBUG ((EFI_D_INFO, "[OpenSBI]: DXE IPL to DXE Core using OpenSBI\n")); + // + // Setup next address in OpenSBI scratch + // + OpenSbiSwitchModeContext.BaseOfStack = BaseOfStack; + OpenSbiSwitchModeContext.TopOfStack = TopOfStack; + OpenSbiSwitchModeContext.HobList = HobList; + OpenSbiSwitchModeContext.DxeCoreEntryPoint = DxeCoreEntryPoint; + ThisScratch = sbi_scratch_thishart_ptr (); + ThisScratch->next_arg1 = (unsigned long)(UINTN)&OpenSbiSwitchModeContext; + ThisScratch->next_addr = (unsigned long)(UINTN)RiscVDxeIplHandoffOpenSbiHandler; + ThisScratch->next_mode = PRV_S; + + DEBUG ((EFI_D_INFO, " Base address of satck: 0x%x\n", BaseOfStack)); + DEBUG ((EFI_D_INFO, " Top address of satck: 0x%x\n", TopOfStack)); + DEBUG ((EFI_D_INFO, " HOB list address: 0x%x\n", &HobList)); + DEBUG ((EFI_D_INFO, " DXE core entry pointer: 0x%x\n", DxeCoreEntryPoint)); + DEBUG ((EFI_D_INFO, " OpenSBI Switch mode arg1: 0x%x\n", (UINTN)&OpenSbiSwitchModeContext)); + DEBUG ((EFI_D_INFO, " OpenSBI Switch mode handler address: 0x%x\n", (UINTN)RiscVDxeIplHandoffOpenSbiHandler)); + DEBUG ((EFI_D_INFO, " OpenSBI Switch mode to privilege 0x%x\n", PRV_S)); + sbi_init (ThisScratch); +} diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf new file mode 100644 index 0000000..3ddfe41 --- /dev/null +++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf @@ -0,0 +1,39 @@ +## @file +# Instance of RISC-V DXE IPL to DXE core handoff platform library using OpenSBI +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = RiscVPlatformDxeIplLib + FILE_GUID = 906A4BB9-8DE2-4CE0-A609-23818A8FF514 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE + +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + RiscVDxeIplHandoffOpenSbiLib.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + DebugLib + RiscVCpuLib + RiscVOpensbiLib + +[Pcd] diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s new file mode 100644 index 0000000..a987c9b --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandler.s @@ -0,0 +1,94 @@ +/** @file + RISC-V Processor supervisor mode trap handler + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include + + .align 3 + .section .entry, "ax", %progbits + .globl _strap_handler +_strap_handler: + addi sp, sp, -34*8 + /* Save all general regisers except SP and T0 */ + sd ra, 1*8(sp) + sd gp, 2*8(sp) + sd tp, 3*8(sp) + sd t1, 4*8(sp) + sd t2, 5*8(sp) + sd s0, 6*8(sp) + sd s1, 7*8(sp) + sd a0, 8*8(sp) + sd a1, 9*8(sp) + sd a2, 10*8(sp) + sd a3, 11*8(sp) + sd a4, 12*8(sp) + sd a5, 13*8(sp) + sd a6, 14*8(sp) + sd a7, 15*8(sp) + sd s2, 16*8(sp) + sd s3, 17*8(sp) + sd s4, 18*8(sp) + sd s5, 19*8(sp) + sd s6, 20*8(sp) + sd s7, 21*8(sp) + sd s8, 22*8(sp) + sd s9, 23*8(sp) + sd s10, 24*8(sp) + sd s11, 25*8(sp) + sd t3, 26*8(sp) + sd t4, 27*8(sp) + sd t5, 28*8(sp) + sd t6, 29*8(sp) + + /* Call C routine */ + call RiscVSupervisorModeTrapHandler + + /* Restore all general regisers except SP and T0 */ + ld ra, 1*8(sp) + ld gp, 2*8(sp) + ld tp, 3*8(sp) + ld t1, 4*8(sp) + ld t2, 5*8(sp) + ld s0, 6*8(sp) + ld s1, 7*8(sp) + ld a0, 8*8(sp) + ld a1, 9*8(sp) + ld a2, 10*8(sp) + ld a3, 11*8(sp) + ld a4, 12*8(sp) + ld a5, 13*8(sp) + ld a6, 14*8(sp) + ld a7, 15*8(sp) + ld s2, 16*8(sp) + ld s3, 17*8(sp) + ld s4, 18*8(sp) + ld s5, 19*8(sp) + ld s6, 20*8(sp) + ld s7, 21*8(sp) + ld s8, 22*8(sp) + ld s9, 23*8(sp) + ld s10, 24*8(sp) + ld s11, 25*8(sp) + ld t3, 26*8(sp) + ld t4, 27*8(sp) + ld t5, 28*8(sp) + ld t6, 29*8(sp) + addi sp, sp, 34*8 + sret \ No newline at end of file diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf new file mode 100644 index 0000000..04bdd6a --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf @@ -0,0 +1,47 @@ +## @file +# RISC-V CPU Exception Handler Library +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CpuExceptionHandlerLib + MODULE_UNI_FILE = CpuExceptionHandlerLib.uni + FILE_GUID = 16309FCF-E900-459C-B071-052118394D11 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = CpuExceptionHandlerLib + CONSTRUCTOR = CpuExceptionHandlerLibConstructor + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources.RISCV64] + CpuExceptionHandler.s + +[Sources.common] + CpuExceptionHandlerLib.c + +[LibraryClasses] + UefiBootServicesTableLib + BaseLib + DebugLib + RiscVCpuLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c new file mode 100644 index 0000000..7be18af --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c @@ -0,0 +1,187 @@ +/** @file + RISC-V Exception Handler library implementition. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include +#include +#include +#include +#include +#include +#include + + +extern void _strap_handler(void); +EFI_CPU_INTERRUPT_HANDLER gInterruptHandlers[2]; +/** + Initializes all CPU exceptions entries and provides the default exception handlers. + + Caller should try to get an array of interrupt and/or exception vectors that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS CPU Exception Entries have been successfully initialized + with default exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + return EFI_SUCCESS; +} + +/** + Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers. + + Caller should try to get an array of interrupt and/or exception vectors that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS All CPU interrupt/exception entries have been successfully initialized + with default interrupt/exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuInterruptHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + return EFI_SUCCESS; +} + +/** + Registers a function to be called from the processor interrupt handler. + + This function registers and enables the handler specified by InterruptHandler for a processor + interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the + handler for the processor interrupt or exception type specified by InterruptType is uninstalled. + The installed handler is called once for each processor interrupt or exception. + NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned. + + @param[in] InterruptType Defines which interrupt or exception to hook. + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. If this parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported, + or this function is not supported. +**/ +EFI_STATUS +EFIAPI +RegisterCpuInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + + DEBUG ((DEBUG_INFO, "RegisterCpuInterruptHandler: Type:%x Handler: %x\n", InterruptType, InterruptHandler)); + gInterruptHandlers[InterruptType] = InterruptHandler; + return EFI_SUCCESS; +} +/** + Machine mode trap handler. + +**/ +VOID +RiscVSupervisorModeTrapHandler ( + VOID + ) +{ + EFI_SYSTEM_CONTEXT RiscVSystemContext; + + // + // Check scasue register. + // + if(gInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL) { + gInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, (CONST EFI_SYSTEM_CONTEXT)RiscVSystemContext); + } +} + +/** + Initializes all CPU exceptions entries with optional extra initializations. + + By default, this method should include all functionalities implemented by + InitializeCpuExceptionHandlers(), plus extra initialization works, if any. + This could be done by calling InitializeCpuExceptionHandlers() directly + in this method besides the extra works. + + InitData is optional and its use and content are processor arch dependent. + The typical usage of it is to convey resources which have to be reserved + elsewhere and are necessary for the extra initializations of exception. + + @param[in] VectorInfo Pointer to reserved vector list. + @param[in] InitData Pointer to data optional for extra initializations + of exception. + + @retval EFI_SUCCESS The exceptions have been successfully + initialized. + @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid + content. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlersEx ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + ) +{ + return InitializeCpuExceptionHandlers (VectorInfo); +} + +/** + The constructor function to initial interrupt handlers in + RISCV_MACHINE_MODE_CONTEXT. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The destructor completed successfully. + @retval Other value The destructor did not complete successfully. + +**/ +EFI_STATUS +EFIAPI +CpuExceptionHandlerLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + // + // Set Superviosr mode trap handler. + // + csr_write(CSR_STVEC, _strap_handler); + + return EFI_SUCCESS; +} diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni new file mode 100644 index 0000000000000000000000000000000000000000..ef38a57603a7a20e05391e4b47cbd0e3764107a9 GIT binary patch literal 1516 zcmc(fUvCmY6vfZ8iQi#EU(~dqKKNja5$LMK+9edMJ~jMnyAcWj+RB$#e`khe5%s|* zLw4@Wojd2Ad*%*5zSmS!!uNzJ#;qaiJ0Wsc!I(SW;7orJtIYFNN&%DPW3Gg}d1F6KLg$COC# ztvPo?e1fOH;hr;_fL7wWKA)ZtJq-NK%(w-Ht~}S!8H!rHT`ncp`=G^;@%L(T*cj1jM7^AA$=ccv;92DLy;xPV zzr-JJ$eh0sv(M>QU80t2q6VAuvyB2~wA#_townj8UWR^j54ty&RD25~D_v#2;C^a* z+Ar}8h#cu?Z>I{%HD9Snm%dG5)24eey<@EFBkLAQx;t&Vcw6*Wk69Y@?dcSo;jlW)!`1ObM}pzg^Y>LiRuJqr}$f-8Y2tYJFLvz zKIiNb>lkN^QE!QL_Al5E?3lUVYr4r2t4Q^Ei&LVv(4tK@Ip;BY7rGTT3I8AQ-@-nB z2iu;BZzt+^0a6A=542PlFtT1&wvJj|`26j6z#aMxTygJxMt7Y%;Rq}$w71Itsh0m$$4~Ue B=s5rY literal 0 HcmV?d00001 diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf new file mode 100644 index 0000000..05180da --- /dev/null +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf @@ -0,0 +1,65 @@ +## @file +# RISC-V Opensbi Library Instance. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# This program and the accompanying materials are licensed and made +# available under the terms and conditions of the BSD License which +# accompanies this distribution. The full text of the license may +# be found at http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = RiscVOpensbiLib + FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RiscVOpensbiLib + +[Sources] + ../../opensbi/lib/sbi/riscv_asm.c + ../../opensbi/lib/sbi/riscv_atomic.c + ../../opensbi/lib/sbi/riscv_hardfp.S + ../../opensbi/lib/sbi/riscv_locks.c + ../../opensbi/lib/sbi/riscv_unpriv.c + ../../opensbi/lib/sbi/sbi_console.c + ../../opensbi/lib/sbi/sbi_ecall.c + ../../opensbi/lib/sbi/sbi_emulate_csr.c + ../../opensbi/lib/sbi/sbi_fifo.c + ../../opensbi/lib/sbi/sbi_hart.c + ../../opensbi/lib/sbi/sbi_illegal_insn.c + ../../opensbi/lib/sbi/sbi_init.c + ../../opensbi/lib/sbi/sbi_ipi.c + ../../opensbi/lib/sbi/sbi_misaligned_ldst.c + ../../opensbi/lib/sbi/sbi_scratch.c + ../../opensbi/lib/sbi/sbi_string.c + ../../opensbi/lib/sbi/sbi_system.c + ../../opensbi/lib/sbi/sbi_timer.c + ../../opensbi/lib/sbi/sbi_tlb.c + ../../opensbi/lib/sbi/sbi_trap.c + ../../opensbi/lib/utils/sys/clint.c + ../../opensbi/lib/utils/irqchip/plic.c + ../../opensbi/lib/utils/serial/sifive-uart.c + ../../opensbi/lib/utils/serial/uart8250.c + ../../opensbi/lib/utils/libfdt/fdt.c + ../../opensbi/lib/utils/libfdt/fdt_ro.c + ../../opensbi/lib/utils/libfdt/fdt_wip.c + ../../opensbi/lib/utils/libfdt/fdt_rw.c + ../../opensbi/lib/utils/libfdt/fdt_sw.c + ../../opensbi/lib/utils/libfdt/fdt_strerror.c + ../../opensbi/lib/utils/libfdt/fdt_empty_tree.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + RiscVCpuLib + diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf new file mode 100644 index 0000000..193452f --- /dev/null +++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf @@ -0,0 +1,42 @@ +## @file +# RISC-V platform temporary memory library. +# +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = RiscVPlatformTempMemoryInitLibNull + FILE_GUID = 67294857-C0F8-4ACB-8237-D91FE506B710 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = RiscVPlatformTempMemoryInitLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV32 RISCV64 +# + +[Sources] + +[Sources.RISCV32] + +[Sources.RISCV64] + Riscv64/TempMemInit.s + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + + diff --git a/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s new file mode 100644 index 0000000..22ff329 --- /dev/null +++ b/RiscVPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.s @@ -0,0 +1,31 @@ +//------------------------------------------------------------------------------ +// +// RISC-V RiscVPlatformTemporaryMemInit. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +//------------------------------------------------------------------------------ +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVPlatformTemporaryMemInit) + +// +// @retval a0 Temporary memory base. +// a1 Temporary memory size. +// +ASM_PFX(RiscVPlatformTemporaryMemInit): + li a0, FixedPcdGet32 (PcdRiscVSecPeiTempRamBase) + li a1, FixedPcdGet32 (PcdRiscVSecPeiTempRamSize) + ret diff --git a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf new file mode 100644 index 0000000..66e821b --- /dev/null +++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf @@ -0,0 +1,40 @@ +## @file +# RISC-V Timer Library Instance. +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# This program and the accompanying materials are licensed and made +# available under the terms and conditions of the BSD License which +# accompanies this distribution. The full text of the license may +# be found at http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = BaseRiscVTimerLib + FILE_GUID = FB648CF5-91BE-4737-9023-FD807AC6D96D + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = TimerLib + +[Sources] + RiscVTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[Pcd] + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz + +[LibraryClasses] + BaseLib + PcdLib + RiscVCpuLib + RiscVPlatformTimerLib + diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c new file mode 100644 index 0000000..5dd4a4e --- /dev/null +++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c @@ -0,0 +1,201 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials are + licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &= (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks = RiscVReadMachineTimer () + Delay; + Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz) + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz) + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter. The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)RiscVReadMachineTimer (); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter starts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end with + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartValue + is less than EndValue, then the performance counter counts up. If StartValue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a StartValue + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with before + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue != NULL) { + *StartValue = 0; + } + + if (EndValue != NULL) { + *EndValue = 32 - 1; + } + + return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance counter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time = --------- x 1,000,000,000 + // Frequency + // + NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)); + + return NanoSeconds; +} diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h new file mode 100644 index 0000000..1704bbb --- /dev/null +++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.h @@ -0,0 +1,26 @@ +/** @file + RISC-V timer library definitions. + + Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + + +#ifndef _RISCV_TIMER_LIB_INTERNAL_H_ +#define _RISCV_TIMER_LIB_INTERNAL_H_ + +#include +#include +#include +#include + +#include + +#endif // _RISCV_TIMER_LIB_INTERNAL_H_ -- 2.7.4