From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=0150651a61=abner.chang@hpe.com) Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Wed, 04 Sep 2019 04:13:27 -0700 Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x84BBmj4010658 for ; Wed, 4 Sep 2019 11:13:26 GMT Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com with ESMTP id 2usgabm53m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 04 Sep 2019 11:13:26 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2352.austin.hpe.com (Postfix) with ESMTP id 02E0AB0 for ; Wed, 4 Sep 2019 11:13:26 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id D78FB36; Wed, 4 Sep 2019 11:13:24 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-staging/RISC-V-V2 PATCH v1 02/22]: RiscVPkg/Include: Add header files of RISC-V CPU package Date: Wed, 4 Sep 2019 18:42:57 +0800 Message-Id: <1567593797-26216-3-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> References: <1567593797-26216-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-09-04_03:2019-09-03,2019-09-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 malwarescore=0 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1906280000 definitions=main-1909040113 RISC-V package library definitions. RiscV.h -Add RiscV.h which conform with RISC-V Privilege Spec v1.10. sbi.h sbi_bits.h sbi_types.h - Add definitions for RISC-V OpenSBI EDK2 port. RealTimeClockLib.h - Header file of platform level Real Time Clock library. SbiFirmwareContext.h - Header file of RISC-V OpenSBI Firmware Context of UEFI EDK2 implementation. RiscVPlatformTempMemoryInitLib.h - Header file of temporary memory functions. RiscVPlatformDxeIplLib - Header file for supporting platform level DXE IPL on RISC-V platform. ProcessorSpecificDataHob.h - Header file of RISC-V processor specific information data hob. This information is built up by platform and consumed by RISC-V generic SMBIOS DXE driver for building up SMBIOS records. SmbiosPrcessorSpecificData.h - Header file of RISC-V processor specific information for SMBIOS type 44 record. RiscVCpuLib.h - Add defitions of generic CSR functions Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Abner Chang --- RiscVPkg/Include/Library/RealTimeClockLib.h | 136 +++++++++++++++++ RiscVPkg/Include/Library/RiscVCpuLib.h | 74 +++++++++ RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 47 ++++++ .../Library/RiscVPlatformTempMemoryInitLib.h | 23 +++ RiscVPkg/Include/ProcessorSpecificDataHob.h | 99 ++++++++++++ RiscVPkg/Include/RiscV.h | 168 +++++++++++++++++++++ RiscVPkg/Include/SmbiosProcessorSpecificData.h | 64 ++++++++ RiscVPkg/Include/sbi/SbiFirmwareContext.h | 44 ++++++ RiscVPkg/Include/sbi/sbi.h | 103 +++++++++++++ RiscVPkg/Include/sbi/sbi_bits.h | 23 +++ RiscVPkg/Include/sbi/sbi_types.h | 24 +++ 11 files changed, 805 insertions(+) create mode 100644 RiscVPkg/Include/Library/RealTimeClockLib.h create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h create mode 100644 RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h create mode 100644 RiscVPkg/Include/ProcessorSpecificDataHob.h create mode 100644 RiscVPkg/Include/RiscV.h create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h create mode 100644 RiscVPkg/Include/sbi/sbi.h create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h create mode 100644 RiscVPkg/Include/sbi/sbi_types.h diff --git a/RiscVPkg/Include/Library/RealTimeClockLib.h b/RiscVPkg/Include/Library/RealTimeClockLib.h new file mode 100644 index 0000000..2815b44 --- /dev/null +++ b/RiscVPkg/Include/Library/RealTimeClockLib.h @@ -0,0 +1,136 @@ +/** @file + Implement EFI RealTimeClock runtime services via RISC-V platform Lib. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __REAL_TIME_CLOCK_LIB__ +#define __REAL_TIME_CLOCK_LIB__ + + +/** + Returns the current time and date information, and the time-keeping capabilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot of the current time. + @param Capabilities An optional pointer to a buffer to receive the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ); + + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error. + +**/ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ); + + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enabled or disabled. + @param Pending Indicates if the alarm signal is pending and requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ); + + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wakeup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If + Enable is FALSE, then the wakeup alarm was disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ); + + + +/** + This is the declaration of an EFI image entry point. This can be the entry point to an application + written to this specification, an EFI boot service driver, or an EFI runtime driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +LibRtcVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +#endif + diff --git a/RiscVPkg/Include/Library/RiscVCpuLib.h b/RiscVPkg/Include/Library/RiscVCpuLib.h new file mode 100644 index 0000000..7a8e75a --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVCpuLib.h @@ -0,0 +1,74 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __RISCV_CPU_LIB_H__ +#define __RISCV_CPU_LIB_H__ + +#include "RiscV.h" + +/** + RISCV_TRAP_HANDLER +**/ +typedef +VOID +(EFIAPI *RISCV_TRAP_HANDLER)( + VOID + ); + +VOID +RiscVSetScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext); + +UINT32 +RiscVGetScratch (VOID); + +UINT32 +RiscVGetTrapCause (VOID); + +UINT64 +RiscVReadMachineTimer (VOID); + +VOID +RiscVSetMachineTimerCmp (UINT64); + +UINT64 +RiscVReadMachineTimerCmp(VOID); + +UINT64 +RiscVReadMachineIE(VOID); + +UINT64 +RiscVReadMachineIP(VOID); + +UINT64 +RiscVReadMachineStatus(VOID); + +VOID +RiscVWriteMachineStatus(UINT64); + +UINT64 +RiscVReadMachineTvec(VOID); + +UINT64 +RiscVReadMisa (VOID); + +UINT64 +RiscVReadMVendorId (VOID); + +UINT64 +RiscVReadMArchId (VOID); + +UINT64 +RiscVReadMImplId (VOID); + +#endif diff --git a/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h new file mode 100644 index 0000000..69ad310 --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h @@ -0,0 +1,47 @@ +/** @file + Header file of RISC-V platform DXE IPL + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP.All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __RISC_V_PLATFORM_DXEIPL_H__ +#define __RISC_V_PLATFORM_DXEIPL_H__ + +typedef struct { + VOID *TopOfStack; + VOID *BaseOfStack; + EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint; + EFI_PEI_HOB_POINTERS HobList; +} OPENSBI_SWITCH_MODE_CONTEXT; + +/** + RISC-V platform DXE IPL to DXE core handoff process. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ + +VOID +RiscVPlatformHandOffToDxeCore ( + IN VOID *BaseOfStack, + IN VOID *TopOfStack, + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ); +#endif + diff --git a/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h b/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h new file mode 100644 index 0000000..0ed3a6e --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h @@ -0,0 +1,23 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __RISCV_PLATFORM_TEMP_MEM_LIB_H__ +#define __RISCV_PLATFORM_TEMP_MEM_LIB_H__ + +#include "RiscV.h" + +VOID EFIAPI RiscVPlatformTemporaryMemInit (VOID); +UINT32 EFIAPI RiscVPlatformTemporaryMemSize(VOID); +UINT32 EFIAPI RiscVPlatformTemporaryMemBase(VOID); +#endif diff --git a/RiscVPkg/Include/ProcessorSpecificDataHob.h b/RiscVPkg/Include/ProcessorSpecificDataHob.h new file mode 100644 index 0000000..4512277 --- /dev/null +++ b/RiscVPkg/Include/ProcessorSpecificDataHob.h @@ -0,0 +1,99 @@ +/** @file + Definition of Processor Specific Data HOB. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef __RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H__ +#define __RISC_V_PROCESSOR_SPECIFIC_DATA_HOB_H__ + +#include + +#define TO_BE_FILLED 0 +#define TO_BE_FILLED_BY_VENDOR 0 +#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0 +#define TO_BE_FILLED_BY_CODE 0 + +#pragma pack(1) + +/// +/// RISC-V processor specific data HOB +/// +typedef struct { + EFI_GUID ParentPrcessorGuid; + UINTN ParentProcessorUid; + EFI_GUID CoreGuid; + VOID *Context; // The additional information of this core which + // built in PEI phase and carried to DXE phase. + // The content is pocessor or platform specific. + SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData; +} RISC_V_PROCESSOR_SPECIFIC_DATA_HOB; + +/// +/// RISC-V SMBIOS type 4 (Processor) GUID data HOB +/// +typedef struct { + EFI_GUID PrcessorGuid; + UINTN ProcessorUid; + SMBIOS_TABLE_TYPE4 SmbiosType4Processor; +} RISC_V_PROCESSOR_TYPE4_DATA_HOB; + +#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF + +#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02 + #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03 + +#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3 +#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5 +#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7 +#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION) + +#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8 +#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION) + #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION) +/// +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB +/// +typedef struct { + EFI_GUID PrcessorGuid; + UINTN ProcessorUid; + SMBIOS_TABLE_TYPE7 SmbiosType7Cache; +} RISC_V_PROCESSOR_TYPE7_DATA_HOB; + +/// +/// RISC-V SMBIOS type 7 (Cache) GUID data HOB +/// +typedef struct { + RISC_V_PROCESSOR_TYPE4_DATA_HOB *Processor; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCache; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1DataCache; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2Cache; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L3Cache; +} RISC_V_PROCESSOR_SMBIOS_DATA_HOB; + +#pragma pack() + +#endif diff --git a/RiscVPkg/Include/RiscV.h b/RiscVPkg/Include/RiscV.h new file mode 100644 index 0000000..f894429 --- /dev/null +++ b/RiscVPkg/Include/RiscV.h @@ -0,0 +1,168 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __RISCV_H__ +#define __RISCV_H__ + +#if defined(MDE_CPU_RISCV32) +#define RISC_V_XLEN_BITS 32 +#elif defined (MDE_CPU_RISCV64) +#define RISC_V_XLEN_BITS 64 +#elif defined (MDE_CPU_RISCV128) +#define RISC_V_XLEN_BITS 128 +#else +#endif + +#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0) +#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1) +#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2) +#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3) +#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4) +#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5) +#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6) +#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7) +#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8) +#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9) +#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10) +#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11) +#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12) +#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13) +#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14) +#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15) +#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16) +#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17) +#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18) +#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19) +#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20) +#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21) +#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22) +#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23) +#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24) +#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25) + +// +// RISC-V CSR definitions. +// +// +// Machine information +// +#define RISCV_CSR_MACHINE_MVENDORID 0xF11 +#define RISCV_CSR_MACHINE_MARCHID 0xF12 +#define RISCV_CSR_MACHINE_MIMPID 0xF13 +#define RISCV_CSR_MACHINE_HARRID 0xF14 +// +// Machine Trap Setup. +// +#define RISCV_CSR_MACHINE_MSTATUS 0x300 +#define RISCV_CSR_MACHINE_MISA 0x301 +#define RISCV_CSR_MACHINE_MEDELEG 0x302 +#define RISCV_CSR_MACHINE_MIDELEG 0x303 +#define RISCV_CSR_MACHINE_MIE 0x304 +#define RISCV_CSR_MACHINE_MTVEC 0x305 + +#define RISCV_TIMER_COMPARE_BITS 32 +// +// Machine Timer and Counter. +// +//#define RISCV_CSR_MACHINE_MTIME 0x701 +//#define RISCV_CSR_MACHINE_MTIMEH 0x741 +// +// Machine Trap Handling. +// +#define RISCV_CSR_MACHINE_MSCRATCH 0x340 +#define RISCV_CSR_MACHINE_MEPC 0x341 +#define RISCV_CSR_MACHINE_MCAUSE 0x342 + #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f + #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1) +#define RISCV_CSR_MACHINE_MBADADDR 0x343 +#define RISCV_CSR_MACHINE_MIP 0x344 + +// +// Machine Protection and Translation. +// +#define RISCV_CSR_MACHINE_MBASE 0x380 +#define RISCV_CSR_MACHINE_MBOUND 0x381 +#define RISCV_CSR_MACHINE_MIBASE 0x382 +#define RISCV_CSR_MACHINE_MIBOUND 0x383 +#define RISCV_CSR_MACHINE_MDBASE 0x384 +#define RISCV_CSR_MACHINE_MDBOUND 0x385 +// +// Machine Read-Write Shadow of Hypervisor Read-Only Registers +// +#define RISCV_CSR_HTIMEW 0xB01 +#define RISCV_CSR_HTIMEHW 0xB81 +// +// Machine Host-Target Interface (Non-Standard Berkeley Extension) +// +#define RISCV_CSR_MTOHOST 0x780 +#define RISCV_CSR_MFROMHOST 0x781 + +// +// Structure for 128-bit value +// +typedef struct { + UINT64 Value64_L; + UINT64 Value64_H; +} RISCV_UINT128; + +#define RISCV_MACHINE_CONTEXT_SIZE 0x1000 +typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _EXCEPTION_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander; + EFI_PHYSICAL_ADDRESS InstAccessFaultHander; + EFI_PHYSICAL_ADDRESS IllegalInstHander; + EFI_PHYSICAL_ADDRESS BreakpointHander; + EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS LoadAccessFaultHander; + EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander; + EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander; +} EXCEPTION_HANDLER_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _INTERRUPT_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS SoftwareIntHandler; + EFI_PHYSICAL_ADDRESS TimerIntHandler; +} INTERRUPT_HANDLER_CONTEXT; + +/// +/// Interrupt handlers in context. +/// +typedef struct _TRAP_HANDLER_CONTEXT { + EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext; + INTERRUPT_HANDLER_CONTEXT IntHandlerContext; +} TRAP_HANDLER_CONTEXT; + +/// +/// Machine mode context used for saveing hart-local context. +/// +typedef struct _RISCV_MACHINE_MODE_CONTEXT { + EFI_PHYSICAL_ADDRESS PeiService; /// PEI service. + EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap handler. + EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap handler. + EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap handler. + EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handler. + TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine mode. +} RISCV_MACHINE_MODE_CONTEXT; + +#endif diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Include/SmbiosProcessorSpecificData.h new file mode 100644 index 0000000..8669b37 --- /dev/null +++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h @@ -0,0 +1,64 @@ +/** @file + Industry Standard Definitions of RISC-V Processor Specific data defined in + below link for complaiant with SMBIOS Table Specification v3.3.0. + https://github.com/riscv/riscv-smbios + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef __SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H__ +#define __SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H__ + +#include + +#include + +#pragma pack(1) + +typedef enum{ + RegisterUnsupported = 0x00, + RegisterLen32 = 0x01, + RegisterLen64 = 0x02, + RegisterLen128 = 0x03 +} RISC_V_REGISTER_LENGTH; + +#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100 + +#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0) +#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2) +#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3) +#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7) + +/// +/// RISC-V processor specific data for SMBIOS type 44 +/// +typedef struct { + UINT16 Revision; + UINT8 Length; + RISCV_UINT128 HartId; + UINT8 BootHartId; + RISCV_UINT128 MachineVendorId; + RISCV_UINT128 MachineArchId; + RISCV_UINT128 MachineImplId; + UINT32 InstSetSupported; + UINT8 PrivilegeModeSupported; + RISCV_UINT128 MModeExcepDelegation; + RISCV_UINT128 MModeInterruptDelegation; + UINT8 HartXlen; + UINT8 MachineModeXlen; + UINT8 Reserved; + UINT8 SupervisorModeXlen; + UINT8 UserModeXlen; +} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA; + +#pragma pack() +#endif + diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h b/RiscVPkg/Include/sbi/SbiFirmwareContext.h new file mode 100644 index 0000000..eedaa44 --- /dev/null +++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h @@ -0,0 +1,44 @@ +/** @file + RISC-V OpesbSBI Platform Firmware context definition + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef __SBI_FIRMWARE_CONTEXT_H__ +#define __SBI_FIRMWARE_CONTEXT_H__ + +#include + +#define RISC_V_MAX_HART_SUPPORTED 16 + +// +// keep the structure member in 64-bit alignment. +// +#pragma pack(push) +#pragma pack(8) + +typedef struct { + UINT64 IsaExtensionSupported; // The ISA extension this core supported. + RISCV_UINT128 MachineVendorId; // Machine vendor ID + RISCV_UINT128 MachineArchId; // Machine Architecture ID + RISCV_UINT128 MachineImplId; // Machine Implementation ID +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC; + +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7) + +typedef struct { + VOID *PeiServiceTable; // PEI Service table + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED]; +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT; + +#pragma pack(pop) +#endif + diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h new file mode 100644 index 0000000..537973b --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi.h @@ -0,0 +1,103 @@ +/** @file + SBI inline function calls. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SBI_H__ +#define __SBI_H__ + +#include +#include + +#define SBI_SET_TIMER 0 +#define SBI_CONSOLE_PUTCHAR 1 +#define SBI_CONSOLE_GETCHAR 2 +#define SBI_CLEAR_IPI 3 +#define SBI_SEND_IPI 4 +#define SBI_REMOTE_FENCE_I 5 +#define SBI_REMOTE_SFENCE_VMA 6 +#define SBI_REMOTE_SFENCE_VMA_ASID 7 +#define SBI_SHUTDOWN 8 + + +#define SBI_CALL(which, arg0, arg1, arg2) ({ \ + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \ + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \ + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \ + register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \ + asm volatile ("ecall" \ + : "+r" (a0) \ + : "r" (a1), "r" (a2), "r" (a7) \ + : "memory"); \ + a0; \ +}) + +#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0) +#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0) +#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0) + +static inline void sbi_console_putchar(int ch) +{ + SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch); +} + +static inline int sbi_console_getchar(void) +{ + return SBI_CALL_0(SBI_CONSOLE_GETCHAR); +} + +static inline void sbi_set_timer(uint64_t stime_value) +{ +#if __riscv_xlen == 32 + SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32); +#else + SBI_CALL_1(SBI_SET_TIMER, stime_value); +#endif +} + +static inline void sbi_shutdown(void) +{ + SBI_CALL_0(SBI_SHUTDOWN); +} + +static inline void sbi_clear_ipi(void) +{ + SBI_CALL_0(SBI_CLEAR_IPI); +} + +static inline void sbi_send_ipi(const unsigned long *hart_mask) +{ + SBI_CALL_1(SBI_SEND_IPI, hart_mask); +} + +static inline void sbi_remote_fence_i(const unsigned long *hart_mask) +{ + SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask); +} + +static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask, + unsigned long start, + unsigned long size) +{ + SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask); +} + +static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, + unsigned long start, + unsigned long size, + unsigned long asid) +{ + SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask); +} + +#endif \ No newline at end of file diff --git a/RiscVPkg/Include/sbi/sbi_bits.h b/RiscVPkg/Include/sbi/sbi_bits.h new file mode 100644 index 0000000..4116ee6 --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi_bits.h @@ -0,0 +1,23 @@ +/** @file + RISC-V OpesbSBI header file reference. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef __EDK2_SBI_BITS_H__ +#define __EDK2_SBI_BITS_H__ + +#undef MAX +#undef MIN + +#include "../opensbi/include/sbi/sbi_bits.h" + +#endif \ No newline at end of file diff --git a/RiscVPkg/Include/sbi/sbi_types.h b/RiscVPkg/Include/sbi/sbi_types.h new file mode 100644 index 0000000..fe877f2 --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi_types.h @@ -0,0 +1,24 @@ +/** @file + RISC-V OpesbSBI header file reference. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#ifndef __EDK2_SBI_TYPES_H__ +#define __EDK2_SBI_TYPES_H__ + +#undef TRUE +#undef FALSE +#undef NULL + +#include "../opensbi/include/sbi/sbi_types.h" + +#endif -- 2.7.4