From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com
Subject: [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
Date: Mon, 23 Sep 2019 08:31:36 +0800 [thread overview]
Message-ID: <1569198715-31552-12-git-send-email-abner.chang@hpe.com> (raw)
In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com>
Support RISC-V image relocation.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
.../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 1 +
.../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 142 +++++++++++++++++++++
5 files changed, 152 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
index 07bb62f..97e0ff4 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
@@ -1,6 +1,6 @@
/** @file
Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but
- only supports relocating IA32, x64, IPF, and EBC images.
+ only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
Caution: This file requires additional review when modified.
This library will have external input - PE/COFF image.
@@ -17,6 +17,7 @@
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
index 395c140..b190494 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
@@ -3,6 +3,7 @@
# The IPF version library supports loading IPF and EBC PE/COFF image.
# The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
# The X64 version library support loading IA32, X64 and EBC PE/COFF images.
+# The RISC-V version library support loading RISC-V images.
#
# Caution: This module requires additional review when modified.
# This library will have external input - PE/COFF image.
@@ -11,6 +12,7 @@
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -41,6 +43,9 @@
[Sources.ARM]
Arm/PeCoffLoaderEx.c
+[Sources.RISCV64]
+ RiscV/PeCoffLoaderEx.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
index b0ea702..8616ca3 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
@@ -4,6 +4,7 @@
// The IPF version library supports loading IPF and EBC PE/COFF image.
// The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
// The X64 version library support loading IA32, X64 and EBC PE/COFF images.
+// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COFF images.
//
// Caution: This module requires additional review when modified.
// This library will have external input - PE/COFF image.
@@ -12,6 +13,7 @@
//
// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
index b74277f..9c33703 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
@@ -2,6 +2,7 @@
Declaration of internal functions in PE/COFF Lib.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
new file mode 100644
index 0000000..8eb37f9
--- /dev/null
+++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
@@ -0,0 +1,142 @@
+/** @file
+ PE/Coff loader for RISC-V PE image
+
+ Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "BasePeCoffLibInternals.h"
+#include <Library/BaseLib.h>
+
+//
+// RISC-V definition.
+//
+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
+#define RISCV_IMM_BITS 12
+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
+#define RISCV_CONST_HIGH_PART(VALUE) \
+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
+
+/**
+ Performs an RISC-V specific relocation fixup and is a no-op on
+ other instruction sets.
+ RISC-V splits 32-bit fixup into 20bit and 12-bit with two relocation
+ types. We have to know the lower 12-bit fixup first then we can deal
+ carry over on high 20-bit fixup. So we log the high 20-bit in
+ FixupData.
+
+ @param Reloc The pointer to the relocation record.
+ @param Fixup The pointer to the address to fix up.
+ @param FixupData The pointer to a buffer to log the fixups.
+ @param Adjust The offset to adjust the fixup.
+
+ @return Status code.
+
+**/
+RETURN_STATUS
+PeCoffLoaderRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ UINT32 Value;
+ UINT32 Value2;
+ UINT32 *RiscVHi20Fixup;
+
+ switch ((*Reloc) >> 12) {
+ case EFI_IMAGE_REL_BASED_RISCV_HI20:
+ *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup;
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
+ RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
+ if (RiscVHi20Fixup != NULL) {
+
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\
+ (RV_X (*(UINT32 *)Fixup, 0, 20));
+ }
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
+ RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
+ if (RiscVHi20Fixup != NULL) {
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ Value2 = *(UINT32 *)Fixup & 0x01fff07f;
+ Value &= RISCV_IMM_REACH - 1;
+ *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
+ }
+ break;
+
+ default:
+ return RETURN_UNSUPPORTED;
+
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Returns TRUE if the machine type of PE/COFF image is supported. Supported
+ does not mean the image can be executed it means the PE/COFF loader supports
+ loading and relocating of the image type. It's up to the caller to support
+ the entry point.
+
+ @param Machine Machine type from the PE Header.
+
+ @return TRUE if this PE/COFF loader can load the image
+
+**/
+BOOLEAN
+PeCoffLoaderImageFormatSupported (
+ IN UINT16 Machine
+ )
+{
+ if ((Machine == IMAGE_FILE_MACHINE_RISCV32) || (Machine == IMAGE_FILE_MACHINE_RISCV64)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Performs an Itanium-based specific re-relocation fixup and is a no-op on other
+ instruction sets. This is used to re-relocated the image into the EFI virtual
+ space for runtime calls.
+
+ @param Reloc The pointer to the relocation record.
+ @param Fixup The pointer to the address to fix up.
+ @param FixupData The pointer to a buffer to log the fixups.
+ @param Adjust The offset to adjust the fixup.
+
+ @return Status code.
+
+**/
+RETURN_STATUS
+PeHotRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ return RETURN_UNSUPPORTED;
+}
--
2.7.4
next prev parent reply other threads:[~2019-09-23 1:02 UTC|newest]
Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-23 0:31 [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 01/29] RiscVPkg: RISC-V processor package Abner Chang
2019-09-26 22:26 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 02/29] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
2019-09-26 22:29 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 03/29] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
2019-09-26 22:41 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
2019-09-26 22:44 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
2019-09-26 22:45 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
2019-09-26 22:46 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
2019-09-26 22:56 ` [edk2-devel] " Leif Lindholm
2019-10-14 16:47 ` Abner Chang
2019-10-14 18:23 ` Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
2019-10-01 8:44 ` [edk2-devel] " Philippe Mathieu-Daudé
2019-09-23 0:31 ` Abner Chang
2019-09-26 23:30 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
2019-09-26 23:39 ` [edk2-devel] " Leif Lindholm
2019-10-01 8:49 ` Philippe Mathieu-Daudé
2019-10-01 9:07 ` Leif Lindholm
2019-10-02 1:30 ` Abner Chang
2019-10-02 9:13 ` Leif Lindholm
2019-10-02 16:14 ` Abner Chang
2019-10-02 16:27 ` Andrew Fish
2019-10-02 16:35 ` Leif Lindholm
2019-10-03 0:52 ` Abner Chang
2019-10-03 8:38 ` Leif Lindholm
2019-10-03 11:34 ` Abner Chang
2019-09-23 0:31 ` Abner Chang [this message]
2019-09-26 23:46 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Leif Lindholm
2019-10-15 4:02 ` Abner Chang
2019-10-15 10:31 ` Leif Lindholm
2019-10-15 10:56 ` Abner Chang
[not found] ` <15CDB6324F411B37.30896@groups.io>
2019-10-15 4:26 ` Abner Chang
2019-10-15 10:41 ` Leif Lindholm
2019-10-15 10:59 ` Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
2019-09-26 23:47 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2019-09-27 0:19 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
2019-09-30 22:51 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
2019-09-30 22:51 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 15/29] RiscVPkg/Library: RISC-V CPU library Abner Chang
2019-09-30 18:31 ` [edk2-devel] " Leif Lindholm
2019-10-15 2:32 ` Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 16/29] RiscVPkg/Library: Add RISC-V exception library Abner Chang
2019-09-30 19:15 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 17/29] RiscVPkg/Library: Add RISC-V timer library Abner Chang
2019-09-30 19:46 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 18/29] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
2019-09-30 20:03 ` [edk2-devel] " Leif Lindholm
2019-10-15 1:21 ` Abner Chang
2019-10-15 8:35 ` Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 19/29] RiscVPkg/Library: RISC-V platform level DxeIPL libraries Abner Chang
2019-09-30 20:15 ` [edk2-devel] " Leif Lindholm
2019-09-30 20:44 ` Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
2019-09-30 20:31 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 21/29] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
2019-09-30 20:54 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 22/29] RiscVPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
2019-09-30 20:56 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 23/29] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
2019-09-30 21:11 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 24/29] BaseTools: BaseTools changes for RISC-V platform Abner Chang
2019-09-26 22:09 ` [edk2-devel] " Leif Lindholm
2019-10-15 6:18 ` Abner Chang
2019-10-15 10:56 ` Leif Lindholm
2019-10-15 11:13 ` Abner Chang
2019-10-16 5:06 ` Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
2019-09-26 20:50 ` [edk2-devel] " Leif Lindholm
2019-10-15 6:31 ` Abner Chang
2019-10-15 11:00 ` Leif Lindholm
2019-10-15 11:03 ` Abner Chang
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 26/29] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
2019-09-30 22:39 ` [edk2-devel] " Leif Lindholm
2019-10-14 11:27 ` Abner Chang
2019-10-14 11:56 ` Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 27/29] edk2-staging/RISC-V-V2: Add submodule Abner Chang
2019-09-26 22:24 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe Abner Chang
2019-09-30 22:48 ` [edk2-devel] " Leif Lindholm
2019-09-23 0:31 ` [edk2-staging/RISC-V-V2 PATCH v2 29/29] edk2-staging: Update Maintainers.txt Abner Chang
2019-09-30 22:50 ` [edk2-devel] " Leif Lindholm
[not found] ` <15C6EB9824DD2A88.29693@groups.io>
2019-09-24 1:52 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 04/29] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
[not found] ` <15C6EB994C26E5C4.2053@groups.io>
2019-09-24 1:52 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 05/29] MdePkg/Include: RISC-V definitions Abner Chang
[not found] ` <15C6EB9950232DB5.29693@groups.io>
2019-09-24 1:53 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 07/29] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
[not found] ` <15C6EB9A049FF8A4.24160@groups.io>
2019-09-24 1:54 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 09/29] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
[not found] ` <15C6EB9B3E887BEB.29693@groups.io>
2019-09-24 1:55 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 13/29] MdeModulePkg/Logo Abner Chang
[not found] ` <15C6EB9A40C408A0.24160@groups.io>
2019-09-24 1:56 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 10/29] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
[not found] ` <15C6EB9B872A5B83.24160@groups.io>
2019-09-24 1:57 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 14/29] NetworkPkg Abner Chang
[not found] ` <15C6EB99CBC780B5.2053@groups.io>
2019-09-24 1:57 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
[not found] ` <15C6EB9A9BD83853.2053@groups.io>
2019-09-24 1:58 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 11/29] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
[not found] ` <15C6EB9AEB7BB057.24160@groups.io>
2019-09-24 1:58 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
[not found] ` <15C6EB99608359A3.24160@groups.io>
2019-09-24 1:59 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
[not found] ` <15C6EB9D6C0EC3B0.29693@groups.io>
2019-09-24 2:00 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 20/29] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
[not found] ` <15C6EB98AD6CCCEB.24160@groups.io>
2019-09-24 2:01 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 06/29] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
[not found] ` <15C6EB9F04387439.29693@groups.io>
2019-09-24 2:02 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 25/29] BaseTools/Scripts Abner Chang
2019-09-26 22:22 ` [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 00/29] RISC-V EDK2 Port on Leif Lindholm
2019-10-15 6:39 ` Abner Chang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1569198715-31552-12-git-send-email-abner.chang@hpe.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox