From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=01695bccdc=abner.chang@hpe.com) Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:02:50 -0700 Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N1147J006848 for ; Mon, 23 Sep 2019 01:02:49 GMT Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5emfmb5k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:02:49 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 0FFBF54 for ; Mon, 23 Sep 2019 01:02:49 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 290C049; Mon, 23 Sep 2019 01:02:47 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-staging/RISC-V-V2 PATCH v2 12/29] MdePkg/BaseSynchronizationLib: RISC-V cache related code. Date: Mon, 23 Sep 2019 08:31:38 +0800 Message-Id: <1569198715-31552-14-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-09-22_09:2019-09-20,2019-09-22 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=1 malwarescore=0 bulkscore=0 phishscore=0 adultscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=647 spamscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1909230006 Support RISC-V cache related functions. Signed-off-by: Abner Chang --- .../BaseSynchronizationLib.inf | 6 + .../RiscV64/Synchronization.c | 183 +++++++++++++++++++++ .../RiscV64/SynchronizationAsm.S | 78 +++++++++ 3 files changed, 267 insertions(+) create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 446bc19..c16ef9d 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -3,6 +3,7 @@ # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -78,6 +79,11 @@ AArch64/Synchronization.S | GCC AArch64/Synchronization.asm | MSFT +[Sources.RISCV64] + Synchronization.c + RiscV64/Synchronization.c | GCC + RiscV64/SynchronizationAsm.S + [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c new file mode 100644 index 0000000..e210b74 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.c @@ -0,0 +1,183 @@ +/** @file + Implementation of synchronization functions on RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +UINT32 +SyncCompareExchange32 ( + IN volatile UINT32 *Value, + IN UINT32 CompareValue, + IN UINT32 ExchangeValue +); + +UINT64 +SyncCompareExchange64 ( + IN volatile UINT64 *Value, + IN UINT64 CompareValue, + IN UINT64 ExchangeValue +); + +UINT32 +SyncSyncIncrement32 ( + IN volatile UINT32 *Value + ); + +UINT32 +SyncSyncDecrement32 ( + IN volatile UINT32 *Value + ); + +/** + Performs an atomic compare exchange operation on a 16-bit + unsigned integer. + + Performs an atomic compare exchange operation on the 16-bit + unsigned integer specified by Value. If Value is equal to + CompareValue, then Value is set to ExchangeValue and + CompareValue is returned. If Value is not equal to + CompareValue, then Value is returned. The compare exchange + operation must be performed using MP safe mechanisms. + + @param Value A pointer to the 16-bit value for the + compare exchange operation. + @param CompareValue 16-bit value used in compare operation. + @param ExchangeValue 16-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT16 +EFIAPI +InternalSyncCompareExchange16 ( + IN volatile UINT16 *Value, + IN UINT16 CompareValue, + IN UINT16 ExchangeValue + ) +{ + DEBUG((DEBUG_ERROR, "%a:RISC-V does not support 16-bit AMO operation\n", __FUNCTION__)); + ASSERT (FALSE); + return 0; +} + +/** + Performs an atomic compare exchange operation on a 32-bit + unsigned integer. + + Performs an atomic compare exchange operation on the 32-bit + unsigned integer specified by Value. If Value is equal to + CompareValue, then Value is set to ExchangeValue and + CompareValue is returned. If Value is not equal to + CompareValue, then Value is returned. The compare exchange + operation must be performed using MP safe mechanisms. + + @param Value A pointer to the 32-bit value for the + compare exchange operation. + @param CompareValue 32-bit value used in compare operation. + @param ExchangeValue 32-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT32 +EFIAPI +InternalSyncCompareExchange32 ( + IN volatile UINT32 *Value, + IN UINT32 CompareValue, + IN UINT32 ExchangeValue + ) +{ + + if (((UINTN)Value % sizeof (UINT32)) != 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncCompareExchange32(Value, CompareValue, ExchangeValue); +} + +/** + Performs an atomic compare exchange operation on a 64-bit unsigned integer. + + Performs an atomic compare exchange operation on the 64-bit unsigned integer specified + by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and + CompareValue is returned. If Value is not equal to CompareValue, then Value is returned. + The compare exchange operation must be performed using MP safe mechanisms. + + @param Value A pointer to the 64-bit value for the compare exchange + operation. + @param CompareValue 64-bit value used in compare operation. + @param ExchangeValue 64-bit value used in exchange operation. + + @return The original *Value before exchange. + +**/ +UINT64 +EFIAPI +InternalSyncCompareExchange64 ( + IN volatile UINT64 *Value, + IN UINT64 CompareValue, + IN UINT64 ExchangeValue + ) +{ + if (((UINTN)Value % sizeof (UINT64)) != 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncCompareExchange64 (Value, CompareValue, ExchangeValue); +} + +/** + Performs an atomic increment of an 32-bit unsigned integer. + + Performs an atomic increment of the 32-bit unsigned integer specified by + Value and returns the incremented value. The increment operation must be + performed using MP safe mechanisms. The state of the return value is not + guaranteed to be MP safe. + + @param Value A pointer to the 32-bit value to increment. + + @return The incremented value. + +**/ +UINT32 +EFIAPI +InternalSyncIncrement ( + IN volatile UINT32 *Value + ) +{ + if (((UINTN)Value % sizeof (UINT32)) != 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncSyncIncrement32 (Value); +} + +/** + Performs an atomic decrement of an 32-bit unsigned integer. + + Performs an atomic decrement of the 32-bit unsigned integer specified by + Value and returns the decrement value. The decrement operation must be + performed using MP safe mechanisms. The state of the return value is not + guaranteed to be MP safe. + + @param Value A pointer to the 32-bit value to decrement. + + @return The decrement value. + +**/ +UINT32 +EFIAPI +InternalSyncDecrement ( + IN volatile UINT32 *Value + ) +{ + if (((UINTN)Value % sizeof (UINT32)) != 0) { + DEBUG((DEBUG_ERROR, "%a:Value pointer must aligned at natural address.\n", __FUNCTION__)); + ASSERT (FALSE); + } + return SyncSyncDecrement32 (Value); +} diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S new file mode 100644 index 0000000..943e274 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S @@ -0,0 +1,78 @@ +//------------------------------------------------------------------------------ +// +// RISC-V synchronization functions. +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------------ +#include + +.data + +.text +.align 3 + +.global ASM_PFX(SyncCompareExchange32) +.global ASM_PFX(SyncCompareExchange64) +.global ASM_PFX(SyncSyncIncrement32) +.global ASM_PFX(SyncSyncDecrement32) + +// +// ompare and xchange a 32-bit value. +// +// @param a0 : Pointer to 32-bit value. +// @param a1 : Compare value. +// @param a2 : Exchange value. +// +ASM_PFX (SyncCompareExchange32): + lr.w a3, (a0) // Load the value from a0 and make + // the reservation of address. + bne a3, a1, exit + sc.w a3, a2, (a0) // Write the value back to the address. + mv a3, a1 +exit: + mv a0, a3 + ret + +.global ASM_PFX(SyncCompareExchange64) + +// +// Compare and xchange a 64-bit value. +// +// @param a0 : Pointer to 64-bit value. +// @param a1 : Compare value. +// @param a2 : Exchange value. +// +ASM_PFX (SyncCompareExchange64): + lr.d a3, (a0) // Load the value from a0 and make + // the reservation of address. + bne a3, a1, exit + sc.d a3, a2, (a0) // Write the value back to the address. + mv a3, a1 +exit2: + mv a0, a3 + ret + +// +// Performs an atomic increment of an 32-bit unsigned integer. +// +// @param a0 : Pointer to 32-bit value. +// +ASM_PFX (SyncSyncIncrement32): + li a1, 1 + amoadd.w a2, a1, (a0) + mv a0, a2 + ret + +// +// Performs an atomic decrement of an 32-bit unsigned integer. +// +// @param a0 : Pointer to 32-bit value. +// +ASM_PFX (SyncSyncDecrement32): + li a1, -1 + amoadd.w a2, a1, (a0) + mv a0, a2 + ret -- 2.7.4