From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=01695bccdc=abner.chang@hpe.com) Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by groups.io with SMTP; Sun, 22 Sep 2019 18:03:12 -0700 Received: from pps.filterd (m0150244.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8N114B1021580 for ; Mon, 23 Sep 2019 01:03:11 GMT Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v5fnuay9b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 23 Sep 2019 01:03:11 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id AA52B57 for ; Mon, 23 Sep 2019 01:03:10 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.44]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id BF1964C; Mon, 23 Sep 2019 01:03:09 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com Subject: [edk2-staging/RISC-V-V2 PATCH v2 28/29] edk2-staging/RISC-V-V2: Add ReadMe Date: Mon, 23 Sep 2019 08:31:54 +0800 Message-Id: <1569198715-31552-30-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-09-22_09:2019-09-20,2019-09-22 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1909230006 Add RiscVEdk2Readme.md Signed-off-by: Abner Chang --- RiscVEdk2Readme.md | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 RiscVEdk2Readme.md diff --git a/RiscVEdk2Readme.md b/RiscVEdk2Readme.md new file mode 100644 index 0000000..ec691fe --- /dev/null +++ b/RiscVEdk2Readme.md @@ -0,0 +1,34 @@ +This branch is used to contribute RISC-V architecture to EDK2 + +The branch owner:
+Abner Chang < abner.chang@hpe.com >
+Gilbert Chen < gilbert.chen@hpe.com > + +## RISC-V EDK2 Port Introduction +RISC-V is an open ISA which was designed to support research and education of computer architecture, but now it becomes +a standard open Instruction Set Architecture for industry implementations. The RISC-V edk2 project is to create a new processor binding in UEFI spec and have the RISC-V edk2 implementation. The goal is to have RISC-V edk2 port as the firmware reference +for RISC-V platforms. + +This branch (RISC-V-V2) on edk2-staging is RISC-V edk2 port with RISC-V OpenSbi (https://github.com/riscv/opensbi) library integrated. RiscVPkg provides the generic and common modules of RISC-V prcessor. The first edk2 RISC-V platform is SiFive U500 FPGA whcih is maintained in U500Pkg under Platform/RiscV/SiFive in edk2-platform repository. + +## RISC-V EDK2 Package +``` +RiscVPkg - RISC-V processor package. This package provides RISC-V processor related protocols/libraries accroding + to UEFI specification and edk2 implementations. +``` +## Toolchain of RISC-V EDK2 port +To build edk2 RISC-V platform requires GCC RISC-V toolchain, refer to https://github.com/riscv/riscv-gnu-toolchain for the details. The commit ID 64879b24 of riscv-gnu-toolchain repository is verified to build RISC-V edk2 platform and boot to EFI SHELL successfully. You have to clone the toolchain from above link and check out commit:64879b24 for building RISC-V edk2 port. The commit later than 64879b24 causes system hangs at the PEI phase to DXE phase transition. We are still figuring out the root cause. + +## EDK2 Build Target +"RISCV64" ARCH is the RISC-V architecture which currently supported and verified. The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu-toolchain @64879b24 as mentioned above, toolchain tag is "GCC5" which is declared in tools_def.txt.
+Below is the edk2 build options for building RISC-V RV64 platform,
+``` +build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCC5 +``` +For example,
+``` +build -a RISCV64 -p Platform/SiFive/U500/U500.dsc -t GCC5 +``` + +Make sure RISC-V toolchain is built succesfully and the toolchain binaries are generated in somewhere you specified when building toolchain. 'GCC5_RISCV64_PREFIX' is the cross compilation prefix to toolchain binraries.
+For example, set 'GCC5_RISCV64_PREFIX' to '~/RiscVToolchain/riscv64-unknown-elf-' before you build RISC-V edk2 port. -- 2.7.4