From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com, Leif Lindholm <leif.lindholm@linaro.org>,
Gilbert Chen <gilbert.chen@hpe.com>
Subject: [platforms/devel-riscv-v2 PATCHv3 01/13] U500Pkg/OpenSbiPlatformLib: Use Fdtlib in EmbeddedPkg
Date: Mon, 23 Sep 2019 11:40:25 +0800 [thread overview]
Message-ID: <1569210037-32285-2-git-send-email-abner.chang@hpe.com> (raw)
In-Reply-To: <1569210037-32285-1-git-send-email-abner.chang@hpe.com>
Use Fdtlib in EmbeddedPkg instead of using OpenSbi one.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../OpenSbiPlatformLib/OpenSbiPlatformLib.inf | 8 +-
.../U500Pkg/Library/OpenSbiPlatformLib/platform.c | 242 +++++++++++----------
2 files changed, 127 insertions(+), 123 deletions(-)
diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
index 473386d..1b20b89 100644
--- a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
@@ -30,16 +30,18 @@
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
RiscVPkg/RiscVPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
Platform/RiscV/RiscVPlatformPkg.dec
[LibraryClasses]
BaseLib
- DebugLib
BaseMemoryLib
- PcdLib
+ DebugLib
DebugAgentLib
- RiscVCpuLib
+ FdtLib
+ PcdLib
PrintLib
+ RiscVCpuLib
[FixedPcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
index 4dca75f..eaaa2d5 100644
--- a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
@@ -1,7 +1,9 @@
/*
- * SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
*
* Authors:
@@ -22,193 +24,193 @@
#define U500_HART_COUNT FixedPcdGet32(PcdHartCount)
-#define U500_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize)
+#define U500_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize)
#define U500_BOOT_HART_ID FixedPcdGet32(PcdBootHartId)
-#define U500_SYS_CLK 100000000
+#define U500_SYS_CLK 100000000
#define U500_CLINT_ADDR 0x2000000
-#define U500_PLIC_ADDR 0xc000000
-#define U500_PLIC_NUM_SOURCES 0x35
-#define U500_PLIC_NUM_PRIORITIES 7
+#define U500_PLIC_ADDR 0xc000000
+#define U500_PLIC_NUM_SOURCES 0x35
+#define U500_PLIC_NUM_PRIORITIES 7
-#define U500_UART_ADDR 0x54000000
+#define U500_UART_ADDR 0x54000000
-#define U500_UART_BAUDRATE 115200
+#define U500_UART_BAUDRATE 115200
/**
* The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode.
* HARTs 1 is selected as boot HART
*/
#ifndef U500_ENABLED_HART_MASK
-#define U500_ENABLED_HART_MASK (1 << U500_BOOT_HART_ID)
+#define U500_ENABLED_HART_MASK (1 << U500_BOOT_HART_ID)
#endif
-#define U500_HARTID_DISABLED ~(U500_ENABLED_HART_MASK)
+#define U500_HARTID_DISABLED ~(U500_ENABLED_HART_MASK)
/* PRCI clock related macros */
//TODO: Do we need a separate driver for this ?
#define U500_PRCI_BASE_ADDR 0x10000000
#define U500_PRCI_CLKMUXSTATUSREG 0x002C
-#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
+#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
static void U500_modify_dt(void *fdt)
{
- u32 i, size;
- int chosen_offset, err;
- int cpu_offset;
- char cpu_node[32] = "";
- const char *mmu_type;
-
- for (i = 0; i < U500_HART_COUNT; i++) {
- sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
- cpu_offset = fdt_path_offset(fdt, cpu_node);
- mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL);
- if (mmu_type && (!strcmp(mmu_type, "riscv,sv39") ||
- !strcmp(mmu_type,"riscv,sv48")))
- continue;
- else
- fdt_setprop_string(fdt, cpu_offset, "status", "masked");
- memset(cpu_node, 0, sizeof(cpu_node));
- }
- size = fdt_totalsize(fdt);
- err = fdt_open_into(fdt, fdt, size + 256);
- if (err < 0)
- sbi_printf("Device Tree can't be expanded to accmodate new node");
-
- chosen_offset = fdt_path_offset(fdt, "/chosen");
- fdt_setprop_string(fdt, chosen_offset, "stdout-path",
- "/soc/serial@10010000:115200");
-
- plic_fdt_fixup(fdt, "riscv,plic0");
+ u32 i, size;
+ int chosen_offset, err;
+ int cpu_offset;
+ char cpu_node[32] = "";
+ const char *mmu_type;
+
+ for (i = 0; i < U500_HART_COUNT; i++) {
+ sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
+ cpu_offset = fdt_path_offset(fdt, cpu_node);
+ mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL);
+ if (mmu_type && (!sbi_strcmp(mmu_type, "riscv,sv39") ||
+ !sbi_strcmp(mmu_type,"riscv,sv48")))
+ continue;
+ else
+ fdt_setprop_string(fdt, cpu_offset, "status", "masked");
+ sbi_memset(cpu_node, 0, sizeof(cpu_node));
+ }
+ size = fdt_totalsize(fdt);
+ err = fdt_open_into(fdt, fdt, size + 256);
+ if (err < 0)
+ sbi_printf("Device Tree can't be expanded to accmodate new node");
+
+ chosen_offset = fdt_path_offset(fdt, "/chosen");
+ fdt_setprop_string(fdt, chosen_offset, "stdout-path",
+ "/soc/serial@10010000:115200");
+
+ plic_fdt_fixup(fdt, "riscv,plic0");
}
static int U500_final_init(bool cold_boot)
{
- void *fdt;
+ void *fdt;
- if (!cold_boot)
- return 0;
+ if (!cold_boot)
+ return 0;
- fdt = sbi_scratch_thishart_arg1_ptr();
- U500_modify_dt(fdt);
+ fdt = sbi_scratch_thishart_arg1_ptr();
+ U500_modify_dt(fdt);
- return 0;
+ return 0;
}
static u32 U500_pmp_region_count(u32 hartid)
{
- return 1;
+ return 1;
}
static int U500_pmp_region_info(u32 hartid, u32 index,
- ulong *prot, ulong *addr, ulong *log2size)
+ ulong *prot, ulong *addr, ulong *log2size)
{
- int ret = 0;
-
- switch (index) {
- case 0:
- *prot = PMP_R | PMP_W | PMP_X;
- *addr = 0;
- *log2size = __riscv_xlen;
- break;
- default:
- ret = -1;
- break;
- };
-
- return ret;
+ int ret = 0;
+
+ switch (index) {
+ case 0:
+ *prot = PMP_R | PMP_W | PMP_X;
+ *addr = 0;
+ *log2size = __riscv_xlen;
+ break;
+ default:
+ ret = -1;
+ break;
+ };
+
+ return ret;
}
static int U500_console_init(void)
{
- unsigned long peri_in_freq;
+ unsigned long peri_in_freq;
- peri_in_freq = U500_SYS_CLK/2;
- return sifive_uart_init(U500_UART_ADDR, peri_in_freq, U500_UART_BAUDRATE);
+ peri_in_freq = U500_SYS_CLK/2;
+ return sifive_uart_init(U500_UART_ADDR, peri_in_freq, U500_UART_BAUDRATE);
}
static int U500_irqchip_init(bool cold_boot)
{
- int rc;
- u32 hartid = sbi_current_hartid();
-
- if (cold_boot) {
- rc = plic_cold_irqchip_init(U500_PLIC_ADDR,
- U500_PLIC_NUM_SOURCES,
- U500_HART_COUNT);
- if (rc)
- return rc;
- }
-
- return plic_warm_irqchip_init(hartid,
- (hartid) ? (2 * hartid - 1) : 0,
- (hartid) ? (2 * hartid) : -1);
+ int rc;
+ u32 hartid = sbi_current_hartid();
+
+ if (cold_boot) {
+ rc = plic_cold_irqchip_init(U500_PLIC_ADDR,
+ U500_PLIC_NUM_SOURCES,
+ U500_HART_COUNT);
+ if (rc)
+ return rc;
+ }
+
+ return plic_warm_irqchip_init(hartid,
+ (hartid) ? (2 * hartid - 1) : 0,
+ (hartid) ? (2 * hartid) : -1);
}
static int U500_ipi_init(bool cold_boot)
{
- int rc;
+ int rc;
- if (cold_boot) {
- rc = clint_cold_ipi_init(U500_CLINT_ADDR,
- U500_HART_COUNT);
- if (rc)
- return rc;
+ if (cold_boot) {
+ rc = clint_cold_ipi_init(U500_CLINT_ADDR,
+ U500_HART_COUNT);
+ if (rc)
+ return rc;
- }
+ }
- return clint_warm_ipi_init();
+ return clint_warm_ipi_init();
}
static int U500_timer_init(bool cold_boot)
{
- int rc;
+ int rc;
- if (cold_boot) {
- rc = clint_cold_timer_init(U500_CLINT_ADDR,
- U500_HART_COUNT);
- if (rc)
- return rc;
- }
+ if (cold_boot) {
+ rc = clint_cold_timer_init(U500_CLINT_ADDR,
+ U500_HART_COUNT);
+ if (rc)
+ return rc;
+ }
- return clint_warm_timer_init();
+ return clint_warm_timer_init();
}
static int U500_system_down(u32 type)
{
- /* For now nothing to do. */
- return 0;
+ /* For now nothing to do. */
+ return 0;
}
const struct sbi_platform_operations platform_ops = {
- .pmp_region_count = U500_pmp_region_count,
- .pmp_region_info = U500_pmp_region_info,
- .final_init = U500_final_init,
- .console_putc = sifive_uart_putc,
- .console_getc = sifive_uart_getc,
- .console_init = U500_console_init,
- .irqchip_init = U500_irqchip_init,
- .ipi_send = clint_ipi_send,
- .ipi_sync = clint_ipi_sync,
- .ipi_clear = clint_ipi_clear,
- .ipi_init = U500_ipi_init,
- .timer_value = clint_timer_value,
- .timer_event_stop = clint_timer_event_stop,
- .timer_event_start = clint_timer_event_start,
- .timer_init = U500_timer_init,
- .system_reboot = U500_system_down,
- .system_shutdown = U500_system_down
+ .pmp_region_count = U500_pmp_region_count,
+ .pmp_region_info = U500_pmp_region_info,
+ .final_init = U500_final_init,
+ .console_putc = sifive_uart_putc,
+ .console_getc = sifive_uart_getc,
+ .console_init = U500_console_init,
+ .irqchip_init = U500_irqchip_init,
+ .ipi_send = clint_ipi_send,
+ .ipi_sync = clint_ipi_sync,
+ .ipi_clear = clint_ipi_clear,
+ .ipi_init = U500_ipi_init,
+ .timer_value = clint_timer_value,
+ .timer_event_stop = clint_timer_event_stop,
+ .timer_event_start = clint_timer_event_start,
+ .timer_init = U500_timer_init,
+ .system_reboot = U500_system_down,
+ .system_shutdown = U500_system_down
};
const struct sbi_platform platform = {
- .opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on.
- .platform_version = SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI Platform version 1.0
- .name = "SiFive Freedom U500",
- .features = SBI_PLATFORM_DEFAULT_FEATURES,
- .hart_count = U500_HART_COUNT,
- .hart_stack_size = U500_HART_STACK_SIZE,
- .disabled_hart_mask = U500_HARTID_DISABLED,
- .platform_ops_addr = (unsigned long)&platform_ops
+ .opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on.
+ .platform_version = SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI Platform version 1.0
+ .name = "SiFive Freedom U500",
+ .features = SBI_PLATFORM_DEFAULT_FEATURES,
+ .hart_count = U500_HART_COUNT,
+ .hart_stack_size = U500_HART_STACK_SIZE,
+ .disabled_hart_mask = U500_HARTID_DISABLED,
+ .platform_ops_addr = (unsigned long)&platform_ops
};
--
2.7.4
next prev parent reply other threads:[~2019-09-23 4:11 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-23 3:40 [platforms/devel-riscv-v2 PATCHv3 00/13] Updates to sync-up with Abner Chang
2019-09-23 3:40 ` Abner Chang [this message]
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 02/13] U500Pkg/Sec: Remove unnecessary PCD reference Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 03/13] U500Pkg/Sec: Add information to header file references Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 04/13] U500Pkg/SerialIoLib: Header file reference change Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 05/13] U500Pkg: Update DEC revision Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 06/13] RiscV :Update INF revision Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 07/13] Silicon/SiFive: Update " Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 08/13] Silicon/SiFive :Update DEC revision Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 09/13] U500Pkg/riscVPlatformTimerLib: Change source code to *.S Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 10/13] RiscV/Sec: " Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 11/13] U500Pkg/SerialIoLib: Add copyrights Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 12/13] RiscV: Update DEC revision Abner Chang
2019-09-23 3:40 ` [platforms/devel-riscv-v2 PATCHv3 13/13] U500Pkg: Leverage EmbeddedPkg modules Abner Chang
2019-10-03 17:55 ` [edk2-devel] [platforms/devel-riscv-v2 PATCHv3 00/13] Updates to sync-up with Leif Lindholm
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