* [edk2-non-osi: PATCH 1/3] Marvell/Cn9130Db: Add DeviceTree
2019-10-10 5:41 [edk2-non-osi: PATCH 0/3] Marvell CN913x device tree Marcin Wojtas
@ 2019-10-10 5:41 ` Marcin Wojtas
2019-10-10 5:41 ` [edk2-non-osi: PATCH 2/3] Marvell/Cn9131Db: " Marcin Wojtas
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Marcin Wojtas @ 2019-10-10 5:41 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
This patch adds device tree sources which are common for Cn913x SoCs
and the CN9130 development board (variant A).
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf | 22 +
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi | 43 ++
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi | 264 ++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi | 10 +
Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi | 552 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts | 185 +++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi | 168 ++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi | 126 +++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts | 29 +
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi | 173 ++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 76 +++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 151 ++++++
12 files changed, 1799 insertions(+)
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
new file mode 100644
index 0000000..091a5b4
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9130DbA.inf
@@ -0,0 +1,22 @@
+## @file
+#
+# Device tree description of the Marvell CN9130-DB-A platform
+#
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9130DbADeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ cn9130-db-A.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
new file mode 100644
index 0000000..bae0ed9
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806-quad.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#include "armada-ap806.dtsi"
+
+/ {
+ model = "Marvell Armada AP806 Quad";
+ compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x000>;
+ enable-method = "psci";
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+ };
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
new file mode 100644
index 0000000..66124bf
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-ap806.dtsi
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#define IRQ_TYPE_LEVEL_HIGH (1 << 2)
+#define IRQ_TYPE_LEVEL_LOW (1 << 3)
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
+
+/dts-v1/;
+
+/ {
+ model = "Marvell Armada AP806";
+ compatible = "marvell,armada-ap806";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ gpio0 = &ap_gpio;
+ spi0 = &spi0;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ ap806 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space@f0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0xf0000000 0x1000000>;
+
+ gic: interrupt-controller@210000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x210000 0x10000>,
+ <0x220000 0x20000>,
+ <0x240000 0x20000>,
+ <0x260000 0x20000>;
+
+ gic_v2m0: v2m@280000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x280000 0x1000>;
+ arm,msi-base-spi = <160>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m1: v2m@290000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x290000 0x1000>;
+ arm,msi-base-spi = <192>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m2: v2m@2a0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2a0000 0x1000>;
+ arm,msi-base-spi = <224>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m3: v2m@2b0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2b0000 0x1000>;
+ arm,msi-base-spi = <256>;
+ arm,msi-num-spis = <32>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupt-parent = <&pic>;
+ interrupts = <17>;
+ };
+
+ odmi: odmi@300000 {
+ compatible = "marvell,odmi-controller";
+ interrupt-controller;
+ msi-controller;
+ marvell,odmi-frames = <4>;
+ reg = <0x300000 0x4000>,
+ <0x304000 0x4000>,
+ <0x308000 0x4000>,
+ <0x30C000 0x4000>;
+ marvell,spi-base = <128>, <136>, <144>, <152>;
+ };
+
+ gicp: gicp@3f0040 {
+ compatible = "marvell,ap806-gicp";
+ reg = <0x3f0040 0x10>;
+ marvell,spi-ranges = <64 64>, <288 64>;
+ msi-controller;
+ };
+
+ pic: interrupt-controller@3f0100 {
+ compatible = "marvell,armada-8k-pic";
+ reg = <0x3f0100 0x10>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ xor@400000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x400000 0x1000>,
+ <0x410000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@420000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x420000 0x1000>,
+ <0x430000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@440000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x440000 0x1000>,
+ <0x450000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@460000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x460000 0x1000>,
+ <0x470000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ spi0: spi@510600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x510600 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@511000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x511000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-ms = <1000>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ uart0: serial@512000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512000 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ uart1: serial@512100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512100 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+
+ };
+
+ watchdog: watchdog@610000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x610000 0x1000>, <0x600000 0x1000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ ap_sdhci0: sdhci@6e0000 {
+ compatible = "marvell,armada-ap806-sdhci";
+ reg = <0x6e0000 0x300>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core";
+ clocks = <&ap_clk 4>;
+ dma-coherent;
+ marvell,xenon-phy-slow-mode;
+ status = "disabled";
+ };
+
+ ap_syscon: system-controller@6f4000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f4000 0x2000>;
+
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
+
+ ap_pinctrl: pinctrl {
+ compatible = "marvell,ap806-pinctrl";
+
+ uart0_pins: uart0-pins {
+ marvell,pins = "mpp11", "mpp19";
+ marvell,function = "uart0";
+ };
+ };
+
+ ap_gpio: gpio@1040 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x1040>;
+ ngpios = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ap_pinctrl 0 0 20>;
+ };
+ };
+
+ ap_thermal: thermal@6f808c {
+ compatible = "marvell,armada-ap806-thermal";
+ reg = <0x6f808c 0x4>,
+ <0x6f8084 0x8>;
+ };
+ };
+ };
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
new file mode 100644
index 0000000..8b610fd
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-common.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ */
+
+/* Common definitions used by Armada 7K/8K DTs */
+#define PASTER(x, y) x ## y
+#define EVALUATOR(x, y) PASTER(x, y)
+#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
+#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
new file mode 100644
index 0000000..b6e5ded
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/armada-cp110.dtsi
@@ -0,0 +1,552 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada CP110.
+ */
+
+#include "armada-common.dtsi"
+
+#define ICU_GRP_NSR 0x0
+#define ICU_GRP_SR 0x1
+#define ICU_GRP_SEI 0x4
+#define ICU_GRP_REI 0x5
+
+#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
+
+/ {
+ /*
+ * The contents of the node are defined below, in order to
+ * save one indentation level
+ */
+ CP110_NAME: CP110_NAME { };
+};
+
+&CP110_NAME {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&CP110_LABEL(icu)>;
+ ranges;
+
+ config-space@CP110_BASE {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
+
+ CP110_LABEL(ethernet): ethernet@0 {
+ compatible = "marvell,armada-7k-pp22";
+ reg = <0x0 0x100000>, <0x129000 0xb000>;
+ clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>,
+ <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(core_clk)>;
+ clock-names = "pp_clk", "gop_clk",
+ "mg_clk", "mg_core_clk", "axi_clk";
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ status = "disabled";
+ dma-coherent;
+
+ CP110_LABEL(eth0): eth0 {
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <0>;
+ gop-port-id = <0>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth1): eth1 {
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <1>;
+ gop-port-id = <2>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth2): eth2 {
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
+ "tx-cpu3", "rx-shared", "link";
+ port-id = <2>;
+ gop-port-id = <3>;
+ status = "disabled";
+ };
+ };
+
+ CP110_LABEL(comphy): phy@120000 {
+ compatible = "marvell,comphy-cp110";
+ reg = <0x120000 0x6000>;
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CP110_LABEL(comphy0): phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy1): phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy2): phy@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy3): phy@3 {
+ reg = <3>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy4): phy@4 {
+ reg = <4>;
+ #phy-cells = <1>;
+ };
+
+ CP110_LABEL(comphy5): phy@5 {
+ reg = <5>;
+ #phy-cells = <1>;
+ };
+ };
+
+ CP110_LABEL(mdio): mdio@12a200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x12a200 0x10>;
+ clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>,
+ <&CP110_LABEL(core_clk)>, <&CP110_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(xmdio): mdio@12a600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,xmdio";
+ reg = <0x12a600 0x10>;
+ clocks = <&CP110_LABEL(ppv2_clk)>, <&CP110_LABEL(ppv2_clk)>,
+ <&CP110_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(icu): interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x440>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+ };
+
+ CP110_LABEL(rtc): rtc@284000 {
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(thermal): thermal@400078 {
+ compatible = "marvell,armada-cp110-thermal";
+ reg = <0x400078 0x4>,
+ <0x400070 0x8>;
+ };
+
+ CP110_LABEL(syscon0): system-controller@440000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x440000 0x2000>;
+
+ CP110_LABEL(clk): clock {
+ compatible = "marvell,cp110-clock";
+ status = "disabled";
+ #clock-cells = <2>;
+ };
+
+ CP110_LABEL(gpio1): gpio@100 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x100>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(gpio2): gpio@140 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x140>;
+ ngpios = <31>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
+ interrupt-controller;
+ interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ CP110_LABEL(usb3_0): usb3@500000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x500000 0x4000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(usb3_1): usb3@510000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x510000 0x4000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(sata0): sata@540000 {
+ compatible = "marvell,armada-8k-ahci",
+ "generic-ahci";
+ reg = <0x540000 0x30000>;
+ dma-coherent;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(xor0): xor@6a0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ };
+
+ CP110_LABEL(xor1): xor@6c0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ };
+
+ CP110_LABEL(spi0): spi@700600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700600 0x50>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(spi1): spi@700680 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c0): i2c@701000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c1): i2c@701100 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart0): serial@702000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702000 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart1): serial@702100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702100 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart2): serial@702200 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702200 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(uart3): serial@702300 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702300 0x100>;
+ reg-shift = <2>;
+ interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP110_LABEL(slow_io_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(nand_controller): nand@720000 {
+ /*
+ * Due to the limitation of the pins available
+ * this controller is only usable on the CPM
+ * for A7K and on the CPS for A8K.
+ */
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
+ reg = <0x720000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(nand_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(trng): trng@760000 {
+ compatible = "marvell,armada-8k-rng",
+ "inside-secure,safexcel-eip76";
+ reg = <0x760000 0x7d>;
+ interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(x2core_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ status = "okay";
+ };
+
+ CP110_LABEL(sdhci0): sdhci@780000 {
+ compatible = "marvell,armada-cp110-sdhci";
+ reg = <0x780000 0x300>;
+ interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "axi";
+ clocks = <&CP110_LABEL(sdio_clk)>, <&CP110_LABEL(core_clk)>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ CP110_LABEL(crypto): crypto@800000 {
+ compatible = "inside-secure,safexcel-eip197";
+ reg = <0x800000 0x200000>;
+ interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mem", "ring0", "ring1",
+ "ring2", "ring3", "eip";
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(x2core_clk)>,
+ <&CP110_LABEL(x2core_clk)>;
+ dma-coherent;
+ };
+ };
+
+ CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
+ <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP110_LABEL(core_clk)>, <&CP110_LABEL(x2core_clk)>;
+ status = "disabled";
+ };
+
+ /* 1 GHz fixed main PLL */
+ CP110_LABEL(mainpll): CP110_LABEL(mainpll) {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ CP110_LABEL(x2core_clk): CP110_LABEL(x2core_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ CP110_LABEL(core_clk): CP110_LABEL(core_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ CP110_LABEL(sdio_clk): CP110_LABEL(sdio_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <2>;
+ clock-div = <5>;
+ };
+
+ CP110_LABEL(nand_clk): CP110_LABEL(nand_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <2>;
+ clock-div = <5>;
+ };
+
+ CP110_LABEL(ppv2_clk): CP110_LABEL(ppv2_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ CP110_LABEL(slow_io_clk): CP110_LABEL(slow_io_clk) {
+ compatible = "fixed-factor-clock";
+ clocks = <&CP110_LABEL(mainpll)>;
+ #clock-cells = <0>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
new file mode 100644
index 0000000..9e4aa51
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db-A.dts
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Model: Marvell CN9130 development board (CP NOR) setup(A)";
+ compatible = "marvell,cn9130-db-A", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* on-board eMMC - U9 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ bus-width = <8>;
+ status = "okay";
+ vqmmc-supply = <&ap0_reg_sd_vccq>;
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cp0_i2c1 {
+ status = "okay";
+};
+
+/* CON 28 */
+&cp0_sdhci0 {
+ status = "okay";
+};
+
+/* U54 */
+&cp0_nand_controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins>;
+
+ nand@0 {
+ reg = <0>;
+ label = "main-storage";
+ nand-rb = <0>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@200000 {
+ label = "Linux";
+ reg = <0x200000 0xd00000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+ };
+ };
+};
+
+/* U55 */
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>; /* CS0 */
+ status = "disabled";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+/* SLM-1521-V2, CON6 */
+&cp0_pcie0 {
+ status = "okay";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 0
+ &cp0_comphy1 0
+ &cp0_comphy2 0
+ &cp0_comphy3 0>;
+};
+
+&cp0_sata0 {
+ status = "okay";
+ /* SLM-1521-V2, CON2 */
+};
+
+&cp0_mdio {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp0_sfp_eth0>;
+};
+
+/* CON56 */
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+/* CON57 */
+&cp0_eth2 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi
new file mode 100644
index 0000000..eeb96f6
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130-db.dtsi
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+#include "cn9130.dtsi" /* include SoC device tree */
+
+/ {
+ model = "DB-CN-9130";
+ compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy0: cp0_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus0>;
+ };
+
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy1: cp0_usb3_phy1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus1>;
+ };
+
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+
+ ap0_reg_sd_vccq: ap0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "ap0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ cp0_sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_sfpp0_i2c>;
+ los-gpio = <&cp0_moudle_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp0_moudle_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp0_moudle_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_moudle_expander1 8 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+};
+
+/*
+ * CP0
+ */
+&cp0_i2c0 {
+ clock-frequency = <100000>;
+
+ /* U36 */
+ expander0: pca953x@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ status = "okay";
+ };
+
+ /* U42 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U38 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
+};
+
+&cp0_i2c1 {
+ clock-frequency = <100000>;
+
+ /* SLM-1521-V2 - U3 */
+ i2c-mux@72 { /* verify address - depends on dpr */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ cp0_sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* U12 */
+ cp0_moudle_expander1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+
+ };
+ };
+};
+
+
+&cp0_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins>;
+ bus-width = <4>;
+ no-1-8-v;
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
new file mode 100644
index 0000000..97ea923
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9130.dtsi
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+/*
+ * Device Tree file for the CN 9130 SoC, made of an AP807 Quad and
+ * three CP110.
+ */
+
+#include "armada-ap806-quad.dtsi"
+
+/ {
+ aliases {
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ };
+};
+
+/* This defines used to calculate the base address of each CP */
+#define CP110_PCIE_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP110_PCIE_BUS_MEM_CFG (0x82000000)
+
+/* CP110-0 Settings */
+#define CP110_NAME cp0
+#define CP110_NUM 0
+#define CP110_BASE f2000000
+#define CP110_PCIE0_BASE f2600000
+#define CP110_PCIE1_BASE f2620000
+#define CP110_PCIE2_BASE f2640000
+#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
+ (0xe0000000 + (iface - 1) * 0x1000000))
+#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NUM
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
+
+/ {
+ model = "Marvell CN 9130";
+ compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_crypto {
+ status = "okay";
+};
+
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,armada-7k-pinctrl";
+
+ cp0_devbus_pins: cp0-devbus-pins {
+ marvell,pins = "mpp15", "mpp16", "mpp17",
+ "mpp18", "mpp19", "mpp20",
+ "mpp21", "mpp22", "mpp23",
+ "mpp24", "mpp25", "mpp26",
+ "mpp27";
+ marvell,function = "dev";
+ };
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = "mpp0", "mpp1", "mpp2",
+ "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8",
+ "mpp9", "mpp10", "mpp11";
+ marvell,function = "ge0";
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = "mpp44", "mpp45", "mpp46",
+ "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52",
+ "mpp53", "mpp54", "mpp55";
+ marvell,function = "ge1";
+ };
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ nand_pins: nand-pins {
+ marvell,pins =
+ "mpp15", "mpp16", "mpp17", "mpp18", "mpp19",
+ "mpp20", "mpp21", "mpp22", "mpp23", "mpp24",
+ "mpp25", "mpp26", "mpp27";
+ marvell,function = "dev";
+ };
+ nand_rb: nand-rb {
+ marvell,pins = "mpp13";
+ marvell,function = "nf";
+ };
+ };
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
new file mode 100644
index 0000000..f08a748
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db-A.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include "cn9130-db-A.dts"
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell CN9131 development board (CP NOR) setup(A)";
+ compatible = "marvell,cn9131-db-A", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* CON50 */
+&cp1_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp1_sfp_eth1>;
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
new file mode 100644
index 0000000..c8e425a
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NUM 1
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+ model = "Marvell CN9131 development board";
+ compatible = "marvell,cn9131-db", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+
+ aliases {
+ gpio3 = &cp1_gpio1;
+ gpio4 = &cp1_gpio2;
+ ethernet3 = &cp1_eth0;
+ ethernet4 = &cp1_eth1;
+ };
+
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp1_usb3_0_phy0: cp1_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp1_reg_usb3_vbus0>;
+ };
+
+ cp1_sfp_eth1: sfp-eth1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp1_i2c0>;
+ los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_sfp_pins>;
+ status = "disabled";
+ };
+};
+
+&cp1_crypto {
+ status = "okay";
+};
+
+&cp1_gpio1 {
+ status = "okay";
+};
+
+&cp1_gpio2 {
+ status = "okay";
+};
+
+&cp1_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+/* CON40 */
+&cp1_pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_pcie_reset_pins>;
+ num-lanes = <2>;
+ num-viewport = <8>;
+ marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy0 0
+ &cp1_comphy1 0>;
+};
+
+&cp1_sata0 {
+ status = "okay";
+ /* CON32 */
+ sata-port@1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy5 1>;
+ };
+};
+
+/* U24 */
+&cp1_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_spi0_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>; /* CS0 */
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+
+};
+
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp1_i2c0_pins: cp1-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp1_spi0_pins: cp1-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
+ marvell,pins = "mpp3";
+ marvell,function = "gpio";
+ };
+ cp1_sfp_pins: sfp-pins {
+ marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
+ marvell,function = "gpio";
+ };
+ cp1_pcie_reset_pins: cp1-pcie-reset-pins {
+ marvell,pins = "mpp0";
+ marvell,function = "gpio";
+ };
+ };
+};
+
+/* CON58 */
+&cp1_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp1_usb3_0_phy0>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy3 1>;
+ phy-names = "usb";
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
new file mode 100644
index 0000000..e9464f8
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts
@@ -0,0 +1,76 @@
+/*
+ * copyright (c) 2019 marvell international ltd.
+ *
+ * spdx-license-identifier: gpl-2.0
+ * https://spdx.org/licenses
+ */
+
+#include "cn9131-db-A.dts"
+#include "cn9132-db.dtsi"
+
+/ {
+ model = "Model: Marvell CN9132 development board (CP NOR) setup(A)";
+ compatible = "marvell,cn9132-db-A", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+
+ aliases {
+ gpio5 = &cp2_gpio1;
+ gpio6 = &cp2_gpio2;
+ ethernet5 = &cp2_eth0;
+ };
+};
+
+&cp2_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp2_eth0 {
+ status = "okay";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp2_sfp_eth0>;
+};
+
+/* SLM-1521-V2, CON6 */
+&cp2_pcie0 {
+ status = "okay";
+ num-lanes = <2>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy0 0
+ &cp2_comphy1 0>;
+};
+
+/* SLM-1521-V2, CON8 */
+&cp2_pcie2 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy5 2>;
+};
+
+&cp2_sata0 {
+ status = "okay";
+ /* SLM-1521-V2, CON4 */
+ sata-port@0 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy2 0>;
+ };
+};
+
+/* CON 2 on SLM-1683 - microSD */
+&cp2_sdhci0 {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON11 */
+&cp2_usb3_1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy3 1>;
+};
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
new file mode 100644
index 0000000..8613607
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi
@@ -0,0 +1,151 @@
+/*
+ * copyright (c) 2019 marvell international ltd.
+ *
+ * spdx-license-identifier: gpl-2.0
+ * https://spdx.org/licenses
+ */
+
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NUM 2
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+ model = "DB-CN-9132";
+ compatible = "marvell,cn9132", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+
+ cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_usb3_0_phy0: cp2_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus0>;
+ };
+
+ cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_usb3_0_phy1: cp2_usb3_phy1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus1>;
+ };
+
+ cp2_reg_sd_vccq: cp2_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp2_sd_vcc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1 3300000 0x0>;
+ };
+
+ cp2_sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp2_sfpp0_i2c>;
+ los-gpio = <&cp2_moudle_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp2_moudle_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp2_moudle_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp2_moudle_expander1 8 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+};
+
+&cp2_crypto {
+ status = "okay";
+};
+
+&cp2_gpio1 {
+ status = "okay";
+};
+
+&cp2_gpio2 {
+ status = "okay";
+};
+
+&cp2_i2c0 {
+ clock-frequency = <100000>;
+
+ /* SLM-1521-V2 - U3 */
+ i2c-mux@72 {
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ cp2_sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* U12 */
+ cp2_moudle_expander1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+ };
+ };
+};
+
+&cp2_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_sdhci_pins>;
+ bus-width = <4>;
+ cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
+ vqmmc-supply = <&cp2_reg_sd_vccq>;
+};
+
+&cp2_syscon0 {
+ cp2_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp2_i2c0_pins: cp2-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp2_sdhci_pins: cp2-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ };
+};
+
+&cp2_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp2_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+&cp2_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp2_usb3_0_phy1>;
+ phy-names = "usb";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread