From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f193.google.com (mail-lj1-f193.google.com [209.85.208.193]) by mx.groups.io with SMTP id smtpd.web12.2518.1570686114555518252 for ; Wed, 09 Oct 2019 22:41:54 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=pPLh0Tcz; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.193, mailfrom: mw@semihalf.com) Received: by mail-lj1-f193.google.com with SMTP id m13so4810041ljj.11 for ; Wed, 09 Oct 2019 22:41:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KaXUAZSH5Nql2e5ODHsJn9CAnNHv8brg0uOdny8K374=; b=pPLh0TczjSN0kaPB03pd8TPyyC3Vlu9iqeNeOhEqKNgdA7Iv7v+FLOzkLKOBfO4Itv tg0CLZKVsetnRt073EgX6emEGA9MTTQr6w2xBJ6Ru1Wp9RweXnCY8ovK4uwQTnw9wE9K vgLSrgPXYgUB8v4kcbPOuOa2PhCWMrCyxvcSCWqiGmct4BjUT7ExvJxfh6osPGlOiiA/ CWm5x6QOhy5mmQ2OAoLQ9t+TrqSLmss6u6LQYgSMM+w34ed/tDxp9BZbeFI6MlHsE0ji FOWPThINwhs5fr+FtdcSD0Us7d1Uca/3kZXGKqEHKZBqJzHbATu1rRcsyN0hIEk5/4xD x1UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KaXUAZSH5Nql2e5ODHsJn9CAnNHv8brg0uOdny8K374=; b=cUwPxM2i9pmIAirLAv8+Jupn+FQixkqkr9QGfBZQQFpce5tkgjDxeflgrB7OOzOmuk XwC9YuyjyhTKvVbqSHKqqFG62NrXfXH2F7LSz/LCLpwnNw8v+9hTIe8+3hY64+bxIDvW A8uXafYrUUKHCWTDkxzcMDiFnBhm25ZaFnKTxGZvHmJPu5dbBF0ogwRHobob37Bm13x3 G4ATrZXZrv2AR0gH0ukXrmA2ywYZfwM4X/RqIM02YmImjYxm0yRnxyjfKbKjGuz9R3Xw +4ZmkxtcB6Uu4wbAtp69Iey5iBHfB5twxP2b4BswzliWSE8y1q1qAkUMkhUMIapWiQDH 3eZQ== X-Gm-Message-State: APjAAAWaTMVzB6Ys/FZnwy3L2oOp1q3d51MFPN4APwQjjMLcX1XBIaXm 2OdWze3UbuBOGYKXonXmjKahccxUPgmphg== X-Google-Smtp-Source: APXvYqz4OaUWIPLDKss6epr/pNogYSvL6GX6x6g8TVSAQybp6Pc8+8/PQujoJ1CSSmm+XUUmK6Xlww== X-Received: by 2002:a2e:89c9:: with SMTP id c9mr4811496ljk.108.1570686112533; Wed, 09 Oct 2019 22:41:52 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id w27sm950028ljd.55.2019.10.09.22.41.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 Oct 2019 22:41:51 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-non-osi: PATCH 3/3] Marvell/Cn9132Db: Add DeviceTree Date: Thu, 10 Oct 2019 07:41:18 +0200 Message-Id: <1570686078-25140-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570686078-25140-1-git-send-email-mw@semihalf.com> References: <1570686078-25140-1-git-send-email-mw@semihalf.com> This patch adjusts the top device tree for the CN9132 development board (variant A), based on the sources which are common for the Cn913x SoCs. Also an .inf file is added to allow its compilation. Signed-off-by: Marcin Wojtas --- Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf | 22 ++++++++++++++++++++ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts | 6 ------ Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi | 20 ++++++++++++------ 3 files changed, 36 insertions(+), 12 deletions(-) create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf new file mode 100644 index 0000000..c9e3b04 --- /dev/null +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9132DbA.inf @@ -0,0 +1,22 @@ +## @file +# +# Device tree description of the Marvell CN9130-DB-A platform +# +# Copyright (c) 2019, Marvell International Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = Cn9132DbADeviceTree + FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + cn9132-db-A.dts + +[Packages] + MdePkg/MdePkg.dec diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts index e9464f8..724d7dc 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db-A.dts @@ -55,12 +55,6 @@ &cp2_sata0 { status = "okay"; - /* SLM-1521-V2, CON4 */ - sata-port@0 { - status = "okay"; - /* Generic PHY, providing serdes lanes */ - phys = <&cp2_comphy2 0>; - }; }; /* CON 2 on SLM-1683 - microSD */ diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi index 8613607..7dc6c6e 100644 --- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi +++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9132-db.dtsi @@ -6,15 +6,23 @@ */ #undef CP110_NUM -#undef CP110_PCIE_MEM_SIZE +#undef CP110_NAME +#undef CP110_BASE +#undef CP110_PCIE0_BASE +#undef CP110_PCIE1_BASE +#undef CP110_PCIE2_BASE #undef CP110_PCIEx_CPU_MEM_BASE -#undef CP110_PCIEx_BUS_MEM_BASE +#undef CP110_PCIEx_MEM_BASE /* CP110-1 Settings */ +#define CP110_NAME cp2 #define CP110_NUM 2 -#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) -#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000) -#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) +#define CP110_BASE f6000000 +#define CP110_PCIE0_BASE f6600000 +#define CP110_PCIE1_BASE f6620000 +#define CP110_PCIE2_BASE f6640000 +#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000) +#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) #include "armada-cp110.dtsi" @@ -124,7 +132,7 @@ &cp2_syscon0 { cp2_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; + compatible = "marvell,armada-7k-pinctrl"; cp2_i2c0_pins: cp2-i2c-pins-0 { marvell,pins = "mpp37", "mpp38"; -- 2.7.4