From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f196.google.com (mail-lj1-f196.google.com [209.85.208.196]) by mx.groups.io with SMTP id smtpd.web10.1684.1570807276051152826 for ; Fri, 11 Oct 2019 08:21:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=n6Q6mlPz; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.196, mailfrom: mw@semihalf.com) Received: by mail-lj1-f196.google.com with SMTP id m7so10243361lji.2 for ; Fri, 11 Oct 2019 08:21:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3JuwrwIJ1Nb8ZuzBRiYoEqPhoVXITL0vcDnNBZIrk14=; b=n6Q6mlPz0CvBkrB8JdDRzWzDxvbjsynJJoA9bU65ibtq74c/LHyiZUSkAIvE+L2M6a DryfCWU5WKYtxSEQ/dCBgB1W6sqkXY6q6ogkACbEPYyZPjBO7MCMshXPS89PEteFVQuX LaPptFT813eMLVulGnjbKJGBw+qHlBrEGnTV9mldjNKKUl9jsQedxBMCJqnRS6OVC4dt qq7ecLK3MX37G8exXsYqARTevQgbu16Ew8bztMxImz84CaXO41v7tKBblMNt7IhJb+UB ItidU2LXa5IAlyMd0de/H3/TSpAIDnbTxwm+kSZviQtZ4CLtXdHGqSyq1yiaUFxmZG3V gOkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3JuwrwIJ1Nb8ZuzBRiYoEqPhoVXITL0vcDnNBZIrk14=; b=XMZWpxvGudjEhW6LWYlRcL6i7A04CcszuNuk23TN5Mhk6xTqA+ObQBftQbDA7lHybf IxXAo6NgKw26WGnR+4cAEAHxXhL4r7ksaaxCuzWhBIE8SfNHOZPZNrkHM1THhJSHNdf6 QwkPRQLdOggSqcoftVTFCF1AxwcrMc8WK4QwfV2LmtqNWvdZVoyWG/DR2dkbNFJ9VLZy aNpCFbN7ZQTany45TS7Vp4T+chQtsPCS0ARAW8z0pVKzOX9JuykShJiuJPOYQgIAPZm3 JP0JULNZLkF0d4OtJx6XWy7SvAmSgMl1QIwjW/kZZlh1bxiIYsBL/v0VWtKFHl4zIp9R 6vYA== X-Gm-Message-State: APjAAAVsKp/vd9tlv3PPkniKZZDFNl8ECm2GdgjTo4LDDoyd0RyjW72d z1Vg07u7UaDIJyjUrdxwTnS6y/SfIdh3ag== X-Google-Smtp-Source: APXvYqy1mnB19oaicewvFevSLuDQyn423nV9TfGLV9JrQFuMidhzKsHX173fBMoS4T82F+jA35F3gQ== X-Received: by 2002:a2e:584b:: with SMTP id x11mr9839131ljd.96.1570807273023; Fri, 11 Oct 2019 08:21:13 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id y4sm2058939ljd.82.2019.10.11.08.21.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 Oct 2019 08:21:12 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-platforms: PATCH v4 1/9] Marvell/Armada7k8k: Fix 32-bit compilation Date: Fri, 11 Oct 2019 17:20:23 +0200 Message-Id: <1570807231-4155-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570807231-4155-1-git-send-email-mw@semihalf.com> References: <1570807231-4155-1-git-send-email-mw@semihalf.com> It turned out, that the recently added features broke ARM compilation. Fix all issues: * Update signatures types in structures (UINTN -> UINT64) * Use fixed type for address in ICU * Limit memory for ARM build to 1GB and stop using non-existent PCD Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h | 2 +- Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h | 2 +- Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 4 ++-- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 8 ++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S | 11 ----------- 5 files changed, 12 insertions(+), 15 deletions(-) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h index a6f551b..3b5a28c 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h @@ -22,7 +22,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent typedef struct { MARVELL_BOARD_DESC_PROTOCOL BoardDescProtocol; - UINTN Signature; + UINT64 Signature; EFI_HANDLE Handle; EFI_LOCK Lock; } MV_BOARD_DESC; diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h index 1cb006a..ce683e7 100644 --- a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h +++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h @@ -36,7 +36,7 @@ typedef struct { EMBEDDED_GPIO GpioProtocol; GPIO_CONTROLLER *SoCGpio; UINTN GpioDeviceCount; - UINTN Signature; + UINT64 Signature; EFI_HANDLE Handle; } MV_GPIO; diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h index 6432916..da7a41e 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -109,8 +109,8 @@ typedef enum { typedef struct { ICU_GROUP Group; - UINTN SetSpiAddr; - UINTN ClrSpiAddr; + EFI_PHYSICAL_ADDRESS SetSpiAddr; + EFI_PHYSICAL_ADDRESS ClrSpiAddr; } ICU_MSI; typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c index a735fe5..cc19694 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c @@ -36,6 +36,7 @@ GetDramSize ( IN OUT UINT64 *MemSize ) { +#if defined(MDE_CPU_AARCH64) ARM_SMC_ARGS SmcRegs = {0}; EFI_STATUS Status; @@ -48,6 +49,13 @@ GetDramSize ( ArmCallSmc (&SmcRegs); *MemSize = SmcRegs.Arg0; +#else + // + // Use fixed value, as currently there is no support + // in Armada early firmware for 32-bit SMC + // + *MemSize = FixedPcdGet64 (PcdSystemMemorySize); +#endif return EFI_SUCCESS; } diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S index 4416163..db43b0f 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S @@ -28,17 +28,6 @@ ASM_FUNC(ArmPlatformPeiBootAction) .err PcdSystemMemoryBase should be 0x0 on this platform! .endif - .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapTarget) - // - // Use the low range for UEFI itself. The remaining memory will be mapped - // and added to the GCD map later. - // - ADRL (r0, mSystemMemoryEnd) - MOV32 (r2, FixedPcdGet32 (PcdDramRemapTarget) - 1) - mov r3, #0 - strd r2, r3, [r0] - .endif - bx lr //UINTN -- 2.7.4