From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f194.google.com (mail-lj1-f194.google.com [209.85.208.194]) by mx.groups.io with SMTP id smtpd.web11.1670.1570807278452800562 for ; Fri, 11 Oct 2019 08:21:19 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=gRPM3IAW; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.194, mailfrom: mw@semihalf.com) Received: by mail-lj1-f194.google.com with SMTP id 7so10210664ljw.7 for ; Fri, 11 Oct 2019 08:21:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=f5ECdp+42V/GeAFPrhwWTHR33cMUJPmHiySfKkKzYKE=; b=gRPM3IAW/lK+H46mSDsCpPpNAiUaJngKI7jWFfZfk+4uCFFnVTQ9Xr+v42X/CGCUbi wNo6u+1TsD+a5m23NET/blMY58NVhpLa023+tIsTrI1nK9vpFGsokoZiLODNGzrLBFBI lfmyN2MpPix1YkC533/kZAVpVl+VfTCwRYMMptYOttMmzltlw23Wq9K8PYhvwgZPWpMD z6PUfK8K9w5CW1VNAxZR/TvTiEzfBim8m/QhNmYFtd0PRl0aOSAEEQW478aLVmvw6sxq OvdrISFF0fFo4b25NRvZexASkJI6hcjxg3b4ywaopNxi7RwYtBKBDriakXZAHmvkvdxr vZgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f5ECdp+42V/GeAFPrhwWTHR33cMUJPmHiySfKkKzYKE=; b=GI7ppVmGdngw8I4vR3SsfDN5CVpWdVXgnKEZriNjrewRIAFDK8pdRfbzvVkBNEN3P9 LqyenVz9xLvzOdOMCkRSF7RP0mjX+7g5ZI1YSzvBQgnAHw2hZtJYNIYfiLqmzUPZh93r 9DBnmhwzaTTRHud5I+V7+4v6nGm7E1SjCazBPiAEr44ZYeM403ktxs18Z0s4HGisb3hU xk7OJfek+HHk3ChJQMfB2OaOP6YBJCafTP5bxwaATtp9aDjMKHRDFhiuOZuZ/qp1dDpV UcM9qP07Oo+hxKu/2tK04QnDnkmacgfE0DNPiNQwonDZeSv0Gk7vwwmJ2WQXEIq5KuMs Hn/g== X-Gm-Message-State: APjAAAWFlgTl4FtaXD0gmIAPn4bswxXt4/z3pEM0yDKxAWyF2CKPl4yq e2C8ygu4AE6HLwtDvSTfTI5xcKOQ8n/kPg== X-Google-Smtp-Source: APXvYqydxM+PNWYq0cJQAFhrK9J+kXnAq27RaDS6TqbkgikKZLMZwSLl+QnfTInc0Ql/jzsuGjjUhg== X-Received: by 2002:a2e:331a:: with SMTP id d26mr9479874ljc.231.1570807276081; Fri, 11 Oct 2019 08:21:16 -0700 (PDT) Return-Path: Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id y4sm2058939ljd.82.2019.10.11.08.21.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 Oct 2019 08:21:15 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Subject: [edk2-platforms: PATCH v4 3/9] Marvell/Cn9130Db: Introduce board support Date: Fri, 11 Oct 2019 17:20:25 +0200 Message-Id: <1570807231-4155-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570807231-4155-1-git-send-email-mw@semihalf.com> References: <1570807231-4155-1-git-send-email-mw@semihalf.com> This patch introduces all necessary components required for building EDK2 firmware for CN9130-DB setup A. Because the board is modular and can be extended to support also CN9131 and CN9132 SoC variants, extract common part into .dsc.inc file, which will be included by them. In order to build this variant, '-D CN9130' flag should be added. Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 107 +++++++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 48 +++++++ Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf | 29 ++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 37 +++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 19 +++ Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c | 126 +++++++++++++++++ Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 144 ++++++++++++++++++++ Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc | 18 +++ 8 files changed, 528 insertions(+) create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.dsc create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc new file mode 100644 index 0000000..33fb7cc --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc @@ -0,0 +1,107 @@ +## @file +# Component description file for the CN9130 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ +[PcdsFixedAtBuild.common] + # CP115 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + + # MPP + gMarvellTokenSpaceGuid.PcdMppChipCount|2 + + # APN807 MPP + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 } + + # CP115 #0 MPP + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 } + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0x9 } + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE } + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + + # I2C + gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 } + gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 } + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 + gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + + # SPI + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 + + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 + + # ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + # ComPhy0 + # 0: PCIE0 5 Gbps + # 1: PCIE0 5 Gbps + # 2: PCIE0 5 Gbps + # 3: PCIE0 5 Gbps + # 4: SFI 10.31 Gbps + # 5: SATA1 5 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } + + # MDIO + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } + + # PHY + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + + # NET + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII) } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } + + # NonDiscoverableDevices + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } + + # PCIE + gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000 + + # RTC + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 + + # SoC Configuration Space + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000 + + # Variable store + gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc new file mode 100644 index 0000000..59f3e9b --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc @@ -0,0 +1,48 @@ +## @file +# Component description file for the CN9130 Development Board (variant A) +# +# Copyright (c) 2019 Marvell International Ltd.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] +!if $(CN9130) + PLATFORM_NAME = Cn9130DbA +!endif + PLATFORM_GUID = 087305a1-8ddd-4027-89ca-68a3ef78fcc7 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES = AARCH64|ARM + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf + BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE = FALSE + DEFINE NETWORK_TLS_ENABLE = FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE + DEFINE NETWORK_ISCSI_ENABLE = FALSE + +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc + +[Components.common] + Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf + +[Components.AARCH64] + Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf + +[LibraryClasses.common] + ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf + NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf new file mode 100644 index 0000000..dfbdc84 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf @@ -0,0 +1,29 @@ +## @file +# +# Copyright (C) 2019, Marvell International Ltd. and its affiliates
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = Cn9130DbABoardDescLib + FILE_GUID = d0f95cbe-c150-47e2-ab8c-b3a3807bcc4b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmadaBoardDescLib + +[Sources] + Cn9130DbABoardDescLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf new file mode 100644 index 0000000..f7cfb36 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf @@ -0,0 +1,37 @@ +## @file +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = Cn9130DbANonDiscoverableInitLib + FILE_GUID = 93886b61-b4f5-4ff3-ba96-6f2f9e7661b9 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = NonDiscoverableInitLib + +[Sources] + NonDiscoverableInitLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib + MvGpioLib + +[Protocols] + gEmbeddedGpioProtocolGuid + +[Depex] + gMarvellPlatformInitCompleteProtocolGuid diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h new file mode 100644 index 0000000..e1a5c34 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h @@ -0,0 +1,19 @@ +/** +* +* Copyright (c) 2019, Marvell International Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#ifndef NON_DISCOVERABLE_INIT_LIB_H__ +#define NON_DISCOVERABLE_INIT_LIB_H__ + +#define CN9130_DB_IO_EXPANDER0 0 +#define CN9130_DB_VBUS0_PIN 0 +#define CN9130_DB_VBUS0_LIMIT_PIN 4 +#define CN9130_DB_VBUS1_PIN 1 +#define CN9130_DB_VBUS1_LIMIT_PIN 5 +#define CN9130_DB_SDMMC_VCC_PIN 14 +#define CN9130_DB_SDMMC_VCCQ_PIN 15 + +#endif diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c new file mode 100644 index 0000000..2b46d14 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c @@ -0,0 +1,126 @@ +/** +* +* Copyright (C) 2019, Marvell International Ltd. and its affiliates. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +// +// GPIO Expander +// +STATIC MV_GPIO_EXPANDER mGpioExpander = { + PCA9555_ID, + 0x21, + 0x0, +}; + + +EFI_STATUS +EFIAPI +ArmadaBoardGpioExpanderGet ( + IN OUT MV_GPIO_EXPANDER **GpioExpanders, + IN OUT UINTN *GpioExpanderCount + ) +{ + *GpioExpanderCount = 1; + *GpioExpanders = &mGpioExpander; + + return EFI_SUCCESS; +} + +// +// PCIE +// +STATIC +MV_PCIE_CONTROLLER mPcieController[] = { + { /* PCIE0 @0xF2640000 */ + .PcieDbiAddress = 0xF2600000, + .ConfigSpaceAddress = 0xD0000000, + .HaveResetGpio = FALSE, + .PcieResetGpio = { 0 }, + .PcieBusMin = 0, + .PcieBusMax = 0xFE, + .PcieIoTranslation = 0xDFF00000, + .PcieIoWinBase = 0x0, + .PcieIoWinSize = 0x10000, + .PcieMmio32Translation = 0, + .PcieMmio32WinBase = 0xC0000000, + .PcieMmio32WinSize = 0x10000000, + .PcieMmio64Translation = 0, + .PcieMmio64WinBase = MAX_UINT64, + .PcieMmio64WinSize = 0, + } +}; + +/** + Return the number and description of PCIE controllers used on the platform. + + @param[in out] **PcieControllers Array containing PCIE controllers' + description. + @param[in out] *PcieControllerCount Amount of used PCIE controllers. + + @retval EFI_SUCCESS The data were obtained successfully. + @retval other Return error status. + +**/ +EFI_STATUS +EFIAPI +ArmadaBoardPcieControllerGet ( + IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers, + IN OUT UINTN *PcieControllerCount + ) +{ + *PcieControllers = mPcieController; + *PcieControllerCount = ARRAY_SIZE (mPcieController); + + return EFI_SUCCESS; +} + +// +// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib +// +STATIC +MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = { + { /* eMMC 0xF06E0000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + TRUE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x40, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + }, + { /* SD/MMC 0xF2780000 */ + 0, /* SOC will be filled by MvBoardDescDxe */ + 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */ + FALSE, /* Xenon1v8Enabled */ + FALSE, /* Xenon8BitBusEnabled */ + FALSE, /* XenonSlowModeEnabled */ + 0x19, /* XenonTuningStepDivisor */ + EmbeddedSlot /* SlotType */ + } +}; + +EFI_STATUS +EFIAPI +ArmadaBoardDescSdMmcGet ( + OUT UINTN *SdMmcDevCount, + OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + *SdMmcDesc = mSdMmcDescTemplate; + *SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate); + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c new file mode 100644 index 0000000..598c649 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c @@ -0,0 +1,144 @@ +/** +* +* Copyright (c) 2017, Linaro Ltd. All rights reserved. +* Copyright (c) 2019, Marvell International Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "NonDiscoverableInitLib.h" + +STATIC +EFI_STATUS +EFIAPI +ConfigurePins ( + IN CONST MV_GPIO_PIN *VbusPin, + IN UINTN PinCount, + IN MV_GPIO_DRIVER_TYPE DriverType + ) +{ + EMBEDDED_GPIO_MODE Mode; + EMBEDDED_GPIO_PIN Gpio; + EMBEDDED_GPIO *GpioProtocol; + EFI_STATUS Status; + UINTN Index; + + Status = MvGpioGetProtocol (DriverType, &GpioProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION__)); + return Status; + } + + for (Index = 0; Index < PinCount; Index++) { + Mode = VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0; + Gpio = GPIO (VbusPin->ControllerId, VbusPin->PinNumber); + GpioProtocol->Set (GpioProtocol, Gpio, Mode); + VbusPin++; + } + + return EFI_SUCCESS; +} + +STATIC CONST MV_GPIO_PIN mCp0XhciVbusPins[] = { + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS0_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS0_LIMIT_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS1_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_VBUS1_LIMIT_PIN, + TRUE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp0XhciInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp0XhciVbusPins, + ARRAY_SIZE (mCp0XhciVbusPins), + MV_GPIO_DRIVER_TYPE_PCA95XX); +} + +STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = { + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_SDMMC_VCC_PIN, + TRUE, + }, + { + MV_GPIO_DRIVER_TYPE_PCA95XX, + CN9130_DB_IO_EXPANDER0, + CN9130_DB_SDMMC_VCCQ_PIN, + FALSE, + }, +}; + +STATIC +EFI_STATUS +EFIAPI +Cp0SdMmcInit ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + return ConfigurePins (mCp0SdMmcPins, + ARRAY_SIZE (mCp0SdMmcPins), + MV_GPIO_DRIVER_TYPE_PCA95XX); +} + +NON_DISCOVERABLE_DEVICE_INIT +EFIAPI +NonDiscoverableDeviceInitializerGet ( + IN NON_DISCOVERABLE_DEVICE_TYPE Type, + IN UINTN Index + ) +{ + if (Type == NonDiscoverableDeviceTypeXhci) { + switch (Index) { + case 0: + case 1: + return Cp0XhciInit; + } + } + + if (Type == NonDiscoverableDeviceTypeSdhci) { + switch (Index) { + case 1: + return Cp0SdMmcInit; + } + } + + return NULL; +} diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc new file mode 100644 index 0000000..0c321d1 --- /dev/null +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc @@ -0,0 +1,18 @@ +# +# Copyright (C) 2019 Marvell International Ltd. and its affiliates +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# Per-board additional content of the DXE phase firmware volume + + INF Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf + INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf + + # DTB + INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf + +!if $(ARCH) == AARCH64 + # ACPI support + INF RuleOverride = ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf +!endif -- 2.7.4