* [edk2-platforms: PATCH v4 1/9] Marvell/Armada7k8k: Fix 32-bit compilation
2019-10-11 15:20 [edk2-platforms: PATCH v4 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
@ 2019-10-11 15:20 ` Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 2/9] Marvell/Cn9130Db: Add ACPI tables Marcin Wojtas
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2019-10-11 15:20 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
It turned out, that the recently added features broke
ARM compilation. Fix all issues:
* Update signatures types in structures (UINTN -> UINT64)
* Use fixed type for address in ICU
* Limit memory for ARM build to 1GB and stop using non-existent PCD
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h | 2 +-
Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h | 2 +-
Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 4 ++--
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 8 ++++++++
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S | 11 -----------
5 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h
index a6f551b..3b5a28c 100644
--- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h
+++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h
@@ -22,7 +22,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
typedef struct {
MARVELL_BOARD_DESC_PROTOCOL BoardDescProtocol;
- UINTN Signature;
+ UINT64 Signature;
EFI_HANDLE Handle;
EFI_LOCK Lock;
} MV_BOARD_DESC;
diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h
index 1cb006a..ce683e7 100644
--- a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h
+++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.h
@@ -36,7 +36,7 @@ typedef struct {
EMBEDDED_GPIO GpioProtocol;
GPIO_CONTROLLER *SoCGpio;
UINTN GpioDeviceCount;
- UINTN Signature;
+ UINT64 Signature;
EFI_HANDLE Handle;
} MV_GPIO;
diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
index 6432916..da7a41e 100644
--- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
+++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
@@ -109,8 +109,8 @@ typedef enum {
typedef struct {
ICU_GROUP Group;
- UINTN SetSpiAddr;
- UINTN ClrSpiAddr;
+ EFI_PHYSICAL_ADDRESS SetSpiAddr;
+ EFI_PHYSICAL_ADDRESS ClrSpiAddr;
} ICU_MSI;
typedef struct {
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
index a735fe5..cc19694 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
@@ -36,6 +36,7 @@ GetDramSize (
IN OUT UINT64 *MemSize
)
{
+#if defined(MDE_CPU_AARCH64)
ARM_SMC_ARGS SmcRegs = {0};
EFI_STATUS Status;
@@ -48,6 +49,13 @@ GetDramSize (
ArmCallSmc (&SmcRegs);
*MemSize = SmcRegs.Arg0;
+#else
+ //
+ // Use fixed value, as currently there is no support
+ // in Armada early firmware for 32-bit SMC
+ //
+ *MemSize = FixedPcdGet64 (PcdSystemMemorySize);
+#endif
return EFI_SUCCESS;
}
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S
index 4416163..db43b0f 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/ARM/ArmPlatformHelper.S
@@ -28,17 +28,6 @@ ASM_FUNC(ArmPlatformPeiBootAction)
.err PcdSystemMemoryBase should be 0x0 on this platform!
.endif
- .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapTarget)
- //
- // Use the low range for UEFI itself. The remaining memory will be mapped
- // and added to the GCD map later.
- //
- ADRL (r0, mSystemMemoryEnd)
- MOV32 (r2, FixedPcdGet32 (PcdDramRemapTarget) - 1)
- mov r3, #0
- strd r2, r3, [r0]
- .endif
-
bx lr
//UINTN
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [edk2-platforms: PATCH v4 2/9] Marvell/Cn9130Db: Add ACPI tables
2019-10-11 15:20 [edk2-platforms: PATCH v4 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 1/9] Marvell/Armada7k8k: Fix 32-bit compilation Marcin Wojtas
@ 2019-10-11 15:20 ` Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 3/9] Marvell/Cn9130Db: Introduce board support Marcin Wojtas
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2019-10-11 15:20 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
This patch adds ACPI tables and necessary headers,
which are common for Cn913x SoCs and the CN9130 development board
(variant A). Wiring up of support will be done in the follow-up
commits.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 56 ++++
| 37 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h | 20 ++
Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 36 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 324 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc | 41 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc | 80 +++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc | 58 ++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc | 135 ++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc | 210 +++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 49 +++
11 files changed, 1046 insertions(+)
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
new file mode 100644
index 0000000..191a747
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf
@@ -0,0 +1,56 @@
+## @file
+# Component description file for PlatformAcpiTables module.
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Cn913xDbA/Dsdt.asl
+ Cn913xDbA/Mcfg.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Pptt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+[BuildOptions]
+ *_*_*_ASLCC_FLAGS = -DCN9130
--git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
new file mode 100644
index 0000000..b5fd397
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
@@ -0,0 +1,37 @@
+/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '}
+#define ACPI_OEM_REVISION 0
+#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O')
+#define ACPI_CREATOR_REVISION 0
+
+#if defined(CN9130)
+#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ',' ')
+#endif
+
+/**
+ * A macro to initialize the common header part of EFI ACPI tables
+ * as defined by EFI_ACPI_DESCRIPTION_HEADER structure.
+ **/
+#define __ACPI_HEADER(sign, type, rev) { \
+ sign, /* UINT32 Signature */ \
+ sizeof (type), /* UINT32 Length */ \
+ rev, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ ACPI_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \
+ ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ ACPI_OEM_REVISION, /* UINT32 OemRevision */ \
+ ACPI_CREATOR_ID, /* UINT32 CreatorId */ \
+ ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h
new file mode 100644
index 0000000..634bd8d
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Pcie.h
@@ -0,0 +1,20 @@
+/**
+
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#define PCI_BUS_MIN 0x0
+#define PCI_BUS_MAX 0x0
+#define PCI_BUS_COUNT 0x1
+#define PCI_MMIO32_BASE 0xC0000000
+#define PCI_MMIO32_SIZE 0x10000000
+#define PCI_MMIO64_BASE 0x800000000
+#define PCI_MMIO64_SIZE 0x100000000
+#define PCI_IO_BASE 0x0
+#define PCI_IO_SIZE 0x10000
+#define PCI_IO_TRANSLATION 0xDFF00000
+#define PCI_ECAM_BASE 0xD0008000
+#define PCI_ECAM_SIZE 0x10000000
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
new file mode 100644
index 0000000..6befe2a
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h
@@ -0,0 +1,36 @@
+/**
+
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ Glossary - abbreviations used in Marvell SampleAtReset library implementation:
+ ICU - Interrupt Consolidation Unit
+ AP - Application Processor hardware block (CN913x incorporates AP807)
+ CP - South Bridge hardware blocks (CN913x incorporates CP115)
+
+**/
+
+#define CP_GIC_SPI_CP0_PCI0 64
+#define CP_GIC_SPI_CP0_PCI1 65
+#define CP_GIC_SPI_CP0_PCI2 66
+#define CP_GIC_SPI_CP0_SDMMC 67
+#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127
+#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126
+#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125
+#define CP_GIC_SPI_CP0_EIP_RNG0 105
+#define CP_GIC_SPI_CP0_USB_H1 112
+#define CP_GIC_SPI_CP0_USB_H0 113
+#define CP_GIC_SPI_CP0_SATA_H0 114
+
+#define CP_GIC_SPI_CP1_PCI0 288
+#define CP_GIC_SPI_CP1_PCI1 289
+#define CP_GIC_SPI_CP1_PCI2 290
+#define CP_GIC_SPI_CP1_SDMMC 291
+#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351
+#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350
+#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349
+#define CP_GIC_SPI_CP1_EIP_RNG0 329
+#define CP_GIC_SPI_CP1_USB_H1 336
+#define CP_GIC_SPI_CP1_USB_H0 337
+#define CP_GIC_SPI_CP1_SATA_H0 338
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
new file mode 100644
index 0000000..3dcf78a
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
@@ -0,0 +1,324 @@
+/** @file
+
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Cn913xDbA/Pcie.h"
+#include "IcuInterrupts.h"
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
+{
+ Scope (_SB)
+ {
+ Device (CPU0)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x000) // _UID: Unique ID
+ }
+ Device (CPU1)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x001) // _UID: Unique ID
+ }
+ Device (CPU2)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x100) // _UID: Unique ID
+ }
+ Device (CPU3)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, 0x101) // _UID: Unique ID
+ }
+
+ Device (AHC0)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2540000, // Address Base (MMIO)
+ 0x00030000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_SATA_H0
+ }
+ })
+ }
+
+ Device (XHC0)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2500000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H0
+ }
+ })
+ }
+
+ Device (XHC1)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF2510000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP0_USB_H1
+ }
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, "MRVL0001") // _HID: Hardware ID
+ Name (_CID, "HISI0031") // _CID: Compatible ID
+ Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ FixedPcdGet64(PcdSerialRegisterBase), // Address Base
+ 0x00000100, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 51
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSerialClockRate) },
+ Package () { "reg-io-width", 1 },
+ Package () { "reg-shift", 2 },
+ }
+ })
+ }
+
+ Device (PP20)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "10gbase-kr"},
+ }
+ })
+ }
+ Device (ETH1)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT1
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 1 },
+ Package () { "gop-port-id", 2 },
+ Package () { "phy-mode", "rgmii-id"},
+ }
+ })
+ }
+ Device (ETH2)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP0_PORT2
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 2 },
+ Package () { "gop-port-id", 3 },
+ Package () { "phy-mode", "rgmii-id"},
+ }
+ })
+ }
+ }
+
+ Device (RNG0)
+ {
+ Name (_HID, "PRP0001") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)
+ {
+ CP_GIC_SPI_CP0_EIP_RNG0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "compatible", "inside-secure,safexcel-eip76" },
+ }
+ })
+ }
+
+ //
+ // PCIe Root Bus
+ //
+ Device (PCI0)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, 0x00) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_PRT, Package () // _PRT: PCI Routing Table
+ {
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }
+ })
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ PCI_BUS_MIN, // Range Minimum
+ PCI_BUS_MAX, // Range Maximum
+ 0x0000, // Translation Offset
+ PCI_BUS_COUNT // Length
+ )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ PCI_MMIO32_BASE, // Range Minimum
+ 0xCFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ PCI_MMIO32_SIZE // Length
+ )
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ PCI_IO_BASE, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ PCI_IO_TRANSLATION, // Translation Address
+ PCI_IO_SIZE, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ })
+ Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
+ } // Method(_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ PCI_ECAM_BASE,
+ PCI_ECAM_SIZE
+ )
+ })
+ }
+ Name (SUPP, 0x00)
+ Name (CTRL, 0x00)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, 0x00, CDW1)
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */
+ Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (And (SUPP, 0x16), 0x16))
+ {
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */
+ }
+
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ }
+
+ Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */
+ Return (Arg3)
+ }
+ Else
+ {
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */
+ Return (Arg3)
+ }
+ } // Method(_OSC)
+ }
+ }
+}
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc
new file mode 100644
index 0000000..88f59ab
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Mcfg.aslc
@@ -0,0 +1,41 @@
+/** @file
+
+ Memory mapped config space base address table (MCFG)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+#include "Cn913xDbA/Pcie.h"
+
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure;
+} ACPI_6_0_MCFG_STRUCTURE;
+#pragma pack()
+
+STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg = {
+ {
+ __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ ACPI_6_0_MCFG_STRUCTURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION),
+ EFI_ACPI_RESERVED_QWORD
+ }, {
+ PCI_ECAM_BASE, // BaseAddress
+ 0, // PciSegmentGroupNumber
+ PCI_BUS_MIN, // StartBusNumber
+ PCI_BUS_MAX, // EndBusNumber
+ EFI_ACPI_RESERVED_DWORD // Reserved
+ }
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc
new file mode 100644
index 0000000..ea396bd
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Fadt.aslc
@@ -0,0 +1,80 @@
+/** @file
+
+ Fixed ACPI Description Table (FADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+#define FADT_FLAGS EFI_ACPI_6_0_HW_REDUCED_ACPI | \
+ EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE | \
+ EFI_ACPI_6_0_HEADLESS
+
+EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ __ACPI_HEADER (EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ FADT_FLAGS, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch
+ EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorVersion
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc
new file mode 100644
index 0000000..46bfe37
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Gtdt.aslc
@@ -0,0 +1,58 @@
+/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+// active low, level triggered
+#define GTDT_GTIMER_FLAGS EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+
+// active high, level triggered
+#define GTDT_WDG_FLAGS 0x0
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Header;
+ EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE SbsaWatchdog;
+} ACPI_6_0_GTDT_STRUCTURE;
+#pragma pack()
+
+ACPI_6_0_GTDT_STRUCTURE Gtdt = {
+ {
+ __ACPI_HEADER (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ ACPI_6_0_GTDT_STRUCTURE,
+ EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION),
+ 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecureEL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecureEL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecureEL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBaseAddress
+ 0x1, // UINT32 PlatformTimerCount
+ sizeof (Gtdt.Header) // UINT32 PlatformTimerOffset
+ }, {
+ EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type
+ sizeof (Gtdt.SbsaWatchdog), // UINT16 Length
+ 0x0, // UINT8 Reserved
+ FixedPcdGet64 (PcdGenericWatchdogRefreshBase), // UINT64 RefreshFramePhysicalAddress
+ FixedPcdGet64 (PcdGenericWatchdogControlBase), // UINT64 WatchdogControlFramePhysicalAddress
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), // UINT32 WatchdogTimerGSIV
+ GTDT_WDG_FLAGS // UINT32 WatchdogTimerFlags
+ },
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc
new file mode 100644
index 0000000..abd3cfc
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Madt.aslc
@@ -0,0 +1,135 @@
+/** @file
+
+ Multiple APIC Description Table (MADT)
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+#define GICC_BASE FixedPcdGet64 (PcdGicInterruptInterfaceBase)
+#define GICD_BASE FixedPcdGet64 (PcdGicDistributorBase)
+#define GICH_BASE 0xF0240000
+#define GICV_BASE 0xF0260000
+#define VGIC_MAINT_INT 25
+
+#define GIC_MSI_FRAME0 0xF0280000
+#define GIC_MSI_FRAME1 0xF0290000
+#define GIC_MSI_FRAME2 0xF02A0000
+#define GIC_MSI_FRAME3 0xF02B0000
+
+#define PMU_INTERRUPT_CPU0 130
+#define PMU_INTERRUPT_CPU1 131
+#define PMU_INTERRUPT_CPU2 132
+#define PMU_INTERRUPT_CPU3 133
+
+#define PMU_INTERRUPT_FLAG EFI_ACPI_6_0_GIC_ENABLED | EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL
+
+#pragma pack(push, 1)
+typedef struct {
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_0_GIC_STRUCTURE GicC[4];
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicD;
+ EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE GicM[4];
+} ACPI_6_0_MADT_STRUCTURE;
+#pragma pack(pop)
+
+
+ACPI_6_0_MADT_STRUCTURE Madt = {
+ {
+ __ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ ACPI_6_0_MADT_STRUCTURE,
+ EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION),
+ 0, // UINT32 LocalApicAddress
+ 0 // UINT32 Flags
+ },
+ {
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, // GicId
+ 0x000, // AcpiCpuUid
+ 0x000, // Mpidr
+ PMU_INTERRUPT_FLAG, // Flags
+ PMU_INTERRUPT_CPU0, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, // GicId
+ 0x001, // AcpiCpuUid
+ 0x001, // Mpidr
+ PMU_INTERRUPT_FLAG, // Flags
+ PMU_INTERRUPT_CPU1, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, // GicId
+ 0x100, // AcpiCpuUid
+ 0x100, // Mpidr
+ PMU_INTERRUPT_FLAG, // Flags
+ PMU_INTERRUPT_CPU2, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, // GicId
+ 0x101, // AcpiCpuUid
+ 0x101, // Mpidr
+ PMU_INTERRUPT_FLAG, // Flags
+ PMU_INTERRUPT_CPU3, // PmuIrq
+ GICC_BASE, // GicBase
+ GICV_BASE, // GicVBase
+ GICH_BASE, // GicHBase
+ VGIC_MAINT_INT, // GsivId
+ 0, // GicRBase
+ 0 // Efficiency
+ ),
+ },
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0x0, // GicDistHwId
+ GICD_BASE, // GicDistBase
+ 0x0, // GicDistVector
+ EFI_ACPI_6_0_GIC_V2 // GicVersion
+ ),
+ {
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x0, // GicMsiFrameId
+ GIC_MSI_FRAME0, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x1, // GicMsiFrameId
+ GIC_MSI_FRAME1, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x2, // GicMsiFrameId
+ GIC_MSI_FRAME2, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x3, // GicMsiFrameId
+ GIC_MSI_FRAME3, // BaseAddress
+ 0, // Flags
+ 0, // SPICount
+ 0 // SPIBase
+ ),
+ }
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Madt;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc
new file mode 100644
index 0000000..f37c751
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Pptt.aslc
@@ -0,0 +1,210 @@
+/** @file
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+#include "AcpiHeader.h"
+
+#define NUM_CORES FixedPcdGet64 (PcdCoreCount)
+
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 Offset[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache;
+} ACPI_6_2_PPTT_CORE;
+
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset[1];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache;
+ ACPI_6_2_PPTT_CORE Cores[2];
+} ACPI_6_2_PPTT_CLUSTER;
+
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset[1];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache;
+ ACPI_6_2_PPTT_CLUSTER Clusters[NUM_CORES / 2];
+} ACPI_6_2_PPTT_PACKAGE;
+
+typedef struct {
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt;
+ ACPI_6_2_PPTT_PACKAGE Packages[1];
+} ACPI_6_2_PPTT_STRUCTURE;
+#pragma pack()
+
+#define PPTT_CORE(pid, cid, id) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_CORE, DCache), \
+ {}, \
+ { \
+ 0, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \
+ }, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, \
+ Packages[pid].Clusters[cid]), /* Parent */ \
+ 256 * (cid) + (id), /* AcpiProcessorId */ \
+ 2, /* NumberOfPrivateResources */ \
+ }, { \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, \
+ Packages[pid].Clusters[cid].Cores[id].DCache), \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, \
+ Packages[pid].Clusters[cid].Cores[id].ICache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_32KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 2, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 0, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ 3 * SIZE_16KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 3, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType */ \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ 0, /* WritePolicy */ \
+ }, \
+ 64 /* LineSize */ \
+ } \
+}
+
+#define PPTT_CLUSTER(pid, cid) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_CLUSTER, L2Cache), \
+ {}, \
+ { \
+ 0, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
+ }, \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid]), /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 1, /* NumberOfPrivateResources */ \
+ }, { \
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid].Clusters[cid].L2Cache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_512KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 16, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ PPTT_CORE(pid, cid, 0), \
+ PPTT_CORE(pid, cid, 1), \
+ } \
+}
+
+ACPI_6_2_PPTT_STRUCTURE Pptt = {
+ {
+ __ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ ACPI_6_2_PPTT_STRUCTURE,
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION),
+ },
+ {
+ {
+ {
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR,
+ FIELD_OFFSET (ACPI_6_2_PPTT_PACKAGE, L3Cache),
+ {},
+ {
+ 1, /* PhysicalPackage */
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */
+ },
+ 0, /* Parent */
+ 0, /* AcpiProcessorId */
+ 1, /* NumberOfPrivateResources */
+ }, {
+ FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[0].L3Cache),
+ }, {
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE,
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE),
+ {},
+ {
+ 1, /* SizePropertyValid */
+ 1, /* NumberOfSetsValid */
+ 1, /* AssociativityValid */
+ 1, /* AllocationTypeValid */
+ 1, /* CacheTypeValid */
+ 1, /* WritePolicyValid */
+ 1, /* LineSizeValid */
+ },
+ 0, /* NextLevelOfCache */
+ SIZE_1MB, /* Size */
+ 2048, /* NumberOfSets */
+ 8, /* Associativity */
+ {
+ 0, /* AllocationType */
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK,
+ },
+ 64 /* LineSize */
+ }, {
+ PPTT_CLUSTER (0, 0),
+#if NUM_CORES > 3
+ PPTT_CLUSTER (0, 1),
+#endif
+ }
+ }
+ }
+};
+
+VOID * CONST ReferenceAcpiTable = &Pptt;
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
new file mode 100644
index 0000000..f663d8a
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc
@@ -0,0 +1,49 @@
+/** @file
+ Serial Port Console Redirection Table (SPCR)
+
+ Copyright (c) 2017, Linaro Limited. All rights reserved.
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/AcpiLib.h>
+
+#include "AcpiHeader.h"
+
+#define MV_UART_AS32(Address) { EFI_ACPI_5_0_SYSTEM_MEMORY, 32, 0, EFI_ACPI_5_0_BYTE, Address }
+
+EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION
+ ),
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, // InterfaceType
+ { EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE }, // Reserved1[3]
+ MV_UART_AS32 (FixedPcdGet64(PcdSerialRegisterBase)), // BaseAddress
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, // InterruptType
+ 0, // Irq
+ 51, // GlobalSystemInterrupt
+ 0, // BaudRate
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, // Parity
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, // StopBits
+ 0, // FlowControl
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, // TerminalType
+ EFI_ACPI_RESERVED_BYTE, // Language
+ 0xFFFF, // PciDeviceId
+ 0xFFFF, // PciVendorId
+ 0, // PciBusNumber
+ 0, // PciDeviceNumber
+ 0, // PciFunctionNumber
+ 0, // PciFlags
+ 0, // PciSegment
+ EFI_ACPI_RESERVED_DWORD // Reserved2
+};
+
+VOID CONST * CONST ReferenceAcpiTable = &Spcr;
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [edk2-platforms: PATCH v4 3/9] Marvell/Cn9130Db: Introduce board support
2019-10-11 15:20 [edk2-platforms: PATCH v4 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 1/9] Marvell/Armada7k8k: Fix 32-bit compilation Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 2/9] Marvell/Cn9130Db: Add ACPI tables Marcin Wojtas
@ 2019-10-11 15:20 ` Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 4/9] Marvell/Library: ArmadaSoCDescLib/MppLib: Extend Xenon information Marcin Wojtas
` (5 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2019-10-11 15:20 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
This patch introduces all necessary components required
for building EDK2 firmware for CN9130-DB setup A.
Because the board is modular and can be extended to support
also CN9131 and CN9132 SoC variants, extract common part into
.dsc.inc file, which will be included by them.
In order to build this variant, '-D CN9130' flag should be added.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 107 +++++++++++++++
Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 48 +++++++
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf | 29 ++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 37 +++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 19 +++
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c | 126 +++++++++++++++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 144 ++++++++++++++++++++
Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc | 18 +++
8 files changed, 528 insertions(+)
create mode 100644 Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
create mode 100644 Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
create mode 100644 Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc
diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
new file mode 100644
index 0000000..33fb7cc
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -0,0 +1,107 @@
+## @file
+# Component description file for the CN9130 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # CP115 count
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|1
+
+ # MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|2
+
+ # APN807 MPP
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+
+ # CP115 #0 MPP
+ gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0x9 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x9, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # I2C
+ gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 }
+ gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
+ gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
+ gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+
+ # SPI
+ gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
+ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+
+ # ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+ # ComPhy0
+ # 0: PCIE0 5 Gbps
+ # 1: PCIE0 5 Gbps
+ # 2: PCIE0 5 Gbps
+ # 3: PCIE0 5 Gbps
+ # 4: SFI 10.31 Gbps
+ # 5: SATA1 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+
+ # UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ # MDIO
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+
+ # PHY
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+ # NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+
+ # PCIE
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000
+
+ # RTC
+ gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
+
+ # SoC Configuration Space
+ gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000
+
+ # Variable store
+ gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE
diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
new file mode 100644
index 0000000..59f3e9b
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
@@ -0,0 +1,48 @@
+## @file
+# Component description file for the CN9130 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+!if $(CN9130)
+ PLATFORM_NAME = Cn9130DbA
+!endif
+ PLATFORM_GUID = 087305a1-8ddd-4027-89ca-68a3ef78fcc7
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001B
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+ BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc
+
+ #
+ # Network definition
+ #
+ DEFINE NETWORK_IP6_ENABLE = FALSE
+ DEFINE NETWORK_TLS_ENABLE = FALSE
+ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
+ DEFINE NETWORK_ISCSI_ENABLE = FALSE
+
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+
+[Components.common]
+ Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf
+
+[Components.AARCH64]
+ Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf
+
+[LibraryClasses.common]
+ ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
+ NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
new file mode 100644
index 0000000..dfbdc84
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
@@ -0,0 +1,29 @@
+## @file
+#
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9130DbABoardDescLib
+ FILE_GUID = d0f95cbe-c150-47e2-ab8c-b3a3807bcc4b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmadaBoardDescLib
+
+[Sources]
+ Cn9130DbABoardDescLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
new file mode 100644
index 0000000..f7cfb36
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
@@ -0,0 +1,37 @@
+## @file
+#
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9130DbANonDiscoverableInitLib
+ FILE_GUID = 93886b61-b4f5-4ff3-ba96-6f2f9e7661b9
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NonDiscoverableInitLib
+
+[Sources]
+ NonDiscoverableInitLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ MvGpioLib
+
+[Protocols]
+ gEmbeddedGpioProtocolGuid
+
+[Depex]
+ gMarvellPlatformInitCompleteProtocolGuid
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
new file mode 100644
index 0000000..e1a5c34
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
@@ -0,0 +1,19 @@
+/**
+*
+* Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#ifndef NON_DISCOVERABLE_INIT_LIB_H__
+#define NON_DISCOVERABLE_INIT_LIB_H__
+
+#define CN9130_DB_IO_EXPANDER0 0
+#define CN9130_DB_VBUS0_PIN 0
+#define CN9130_DB_VBUS0_LIMIT_PIN 4
+#define CN9130_DB_VBUS1_PIN 1
+#define CN9130_DB_VBUS1_LIMIT_PIN 5
+#define CN9130_DB_SDMMC_VCC_PIN 14
+#define CN9130_DB_SDMMC_VCCQ_PIN 15
+
+#endif
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
new file mode 100644
index 0000000..2b46d14
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.c
@@ -0,0 +1,126 @@
+/**
+*
+* Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/ArmadaBoardDescLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/MvGpioLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+//
+// GPIO Expander
+//
+STATIC MV_GPIO_EXPANDER mGpioExpander = {
+ PCA9555_ID,
+ 0x21,
+ 0x0,
+};
+
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardGpioExpanderGet (
+ IN OUT MV_GPIO_EXPANDER **GpioExpanders,
+ IN OUT UINTN *GpioExpanderCount
+ )
+{
+ *GpioExpanderCount = 1;
+ *GpioExpanders = &mGpioExpander;
+
+ return EFI_SUCCESS;
+}
+
+//
+// PCIE
+//
+STATIC
+MV_PCIE_CONTROLLER mPcieController[] = {
+ { /* PCIE0 @0xF2640000 */
+ .PcieDbiAddress = 0xF2600000,
+ .ConfigSpaceAddress = 0xD0000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xFE,
+ .PcieIoTranslation = 0xDFF00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xC0000000,
+ .PcieMmio32WinSize = 0x10000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = MAX_UINT64,
+ .PcieMmio64WinSize = 0,
+ }
+};
+
+/**
+ Return the number and description of PCIE controllers used on the platform.
+
+ @param[in out] **PcieControllers Array containing PCIE controllers'
+ description.
+ @param[in out] *PcieControllerCount Amount of used PCIE controllers.
+
+ @retval EFI_SUCCESS The data were obtained successfully.
+ @retval other Return error status.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaBoardPcieControllerGet (
+ IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,
+ IN OUT UINTN *PcieControllerCount
+ )
+{
+ *PcieControllers = mPcieController;
+ *PcieControllerCount = ARRAY_SIZE (mPcieController);
+
+ return EFI_SUCCESS;
+}
+
+//
+// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib
+//
+STATIC
+MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = {
+ { /* eMMC 0xF06E0000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ TRUE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x40, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ },
+ { /* SD/MMC 0xF2780000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ FALSE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x19, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ }
+};
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardDescSdMmcGet (
+ OUT UINTN *SdMmcDevCount,
+ OUT MV_BOARD_SDMMC_DESC **SdMmcDesc
+ )
+{
+ *SdMmcDesc = mSdMmcDescTemplate;
+ *SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
new file mode 100644
index 0000000..598c649
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
@@ -0,0 +1,144 @@
+/**
+*
+* Copyright (c) 2017, Linaro Ltd. All rights reserved.
+* Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/MvGpioLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/NonDiscoverableDevice.h>
+
+#include "NonDiscoverableInitLib.h"
+
+STATIC
+EFI_STATUS
+EFIAPI
+ConfigurePins (
+ IN CONST MV_GPIO_PIN *VbusPin,
+ IN UINTN PinCount,
+ IN MV_GPIO_DRIVER_TYPE DriverType
+ )
+{
+ EMBEDDED_GPIO_MODE Mode;
+ EMBEDDED_GPIO_PIN Gpio;
+ EMBEDDED_GPIO *GpioProtocol;
+ EFI_STATUS Status;
+ UINTN Index;
+
+ Status = MvGpioGetProtocol (DriverType, &GpioProtocol);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION__));
+ return Status;
+ }
+
+ for (Index = 0; Index < PinCount; Index++) {
+ Mode = VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0;
+ Gpio = GPIO (VbusPin->ControllerId, VbusPin->PinNumber);
+ GpioProtocol->Set (GpioProtocol, Gpio, Mode);
+ VbusPin++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC CONST MV_GPIO_PIN mCp0XhciVbusPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_VBUS0_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_VBUS0_LIMIT_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_VBUS1_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_VBUS1_LIMIT_PIN,
+ TRUE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+Cp0XhciInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mCp0XhciVbusPins,
+ ARRAY_SIZE (mCp0XhciVbusPins),
+ MV_GPIO_DRIVER_TYPE_PCA95XX);
+}
+
+STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_SDMMC_VCC_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_PCA95XX,
+ CN9130_DB_IO_EXPANDER0,
+ CN9130_DB_SDMMC_VCCQ_PIN,
+ FALSE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+Cp0SdMmcInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mCp0SdMmcPins,
+ ARRAY_SIZE (mCp0SdMmcPins),
+ MV_GPIO_DRIVER_TYPE_PCA95XX);
+}
+
+NON_DISCOVERABLE_DEVICE_INIT
+EFIAPI
+NonDiscoverableDeviceInitializerGet (
+ IN NON_DISCOVERABLE_DEVICE_TYPE Type,
+ IN UINTN Index
+ )
+{
+ if (Type == NonDiscoverableDeviceTypeXhci) {
+ switch (Index) {
+ case 0:
+ case 1:
+ return Cp0XhciInit;
+ }
+ }
+
+ if (Type == NonDiscoverableDeviceTypeSdhci) {
+ switch (Index) {
+ case 1:
+ return Cp0SdMmcInit;
+ }
+ }
+
+ return NULL;
+}
diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc
new file mode 100644
index 0000000..0c321d1
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc
@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2019 Marvell International Ltd. and its affiliates
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+# Per-board additional content of the DXE phase firmware volume
+
+ INF Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.inf
+ INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf
+
+ # DTB
+ INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf
+
+!if $(ARCH) == AARCH64
+ # ACPI support
+ INF RuleOverride = ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf
+!endif
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [edk2-platforms: PATCH v4 4/9] Marvell/Library: ArmadaSoCDescLib/MppLib: Extend Xenon information
2019-10-11 15:20 [edk2-platforms: PATCH v4 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (2 preceding siblings ...)
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 3/9] Marvell/Cn9130Db: Introduce board support Marcin Wojtas
@ 2019-10-11 15:20 ` Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 5/9] Marvell/Library: IcuLib: Fix debug information Marcin Wojtas
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2019-10-11 15:20 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
Hitherto SoC description and MppLib libraries code assumed
that there could be only two Xenon SdMmc controller
instances in the SoC. Remove those limitations, so that
to support CN913x SoCs, which may have up to 4 of such interfaces.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 5 +--
Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 34 +++++++++++++-------
Silicon/Marvell/Library/MppLib/MppLib.c | 4 +--
3 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
index 0296d43..265b4f4 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
@@ -90,8 +90,9 @@
//
// Platform description of SDMMC controllers
//
-#define MV_SOC_MAX_SDMMC_COUNT 2
-#define MV_SOC_SDMMC_BASE(Index) ((Index) == 0 ? 0xF06E0000 : 0xF2780000)
+#define MV_SOC_SDMMC_PER_CP_COUNT 1
+#define MV_SOC_AP80X_SDMMC_BASE 0xF06E0000
+#define MV_SOC_CP_SDMMC_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x780000)
//
// Platform description of UTMI PHY's
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
index 5947601..3ffd57e 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
@@ -349,26 +349,36 @@ EFI_STATUS
EFIAPI
ArmadaSoCDescSdMmcGet (
IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc,
- IN OUT UINTN *DescCount
+ IN OUT UINTN *Count
)
{
- MV_SOC_SDMMC_DESC *Desc;
- UINTN Index;
+ MV_SOC_SDMMC_DESC *SdMmc;
+ UINTN CpCount, CpIndex;
- Desc = AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC_DESC));
- if (Desc == NULL) {
+ CpCount = FixedPcdGet8 (PcdMaxCpCount);
+
+ *Count = CpCount * MV_SOC_SDMMC_PER_CP_COUNT + MV_SOC_AP806_COUNT;
+ SdMmc = AllocateZeroPool (*Count * sizeof (MV_SOC_SDMMC_DESC));
+ if (SdMmc == NULL) {
DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
return EFI_OUT_OF_RESOURCES;
}
- for (Index = 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) {
- Desc[Index].SdMmcBaseAddress = MV_SOC_SDMMC_BASE (Index);
- Desc[Index].SdMmcMemSize = SIZE_1KB;
- Desc[Index].SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent;
- }
+ *SdMmcDesc = SdMmc;
+
+ /* AP80x controller */
+ SdMmc->SdMmcBaseAddress = MV_SOC_AP80X_SDMMC_BASE;
+ SdMmc->SdMmcMemSize = SIZE_1KB;
+ SdMmc->SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent;
+ SdMmc++;
- *SdMmcDesc = Desc;
- *DescCount = MV_SOC_MAX_SDMMC_COUNT;
+ /* CP11x controllers */
+ for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
+ SdMmc->SdMmcBaseAddress = MV_SOC_CP_SDMMC_BASE (CpIndex);
+ SdMmc->SdMmcMemSize = SIZE_1KB;
+ SdMmc->SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent;
+ SdMmc++;
+ }
return EFI_SUCCESS;
}
diff --git a/Silicon/Marvell/Library/MppLib/MppLib.c b/Silicon/Marvell/Library/MppLib/MppLib.c
index 40d9077..f20668d 100644
--- a/Silicon/Marvell/Library/MppLib/MppLib.c
+++ b/Silicon/Marvell/Library/MppLib/MppLib.c
@@ -139,11 +139,9 @@ SetSdMmcPhyMpp (
case 0:
Offset = SD_MMC_PHY_AP_MPP_OFFSET;
break;
- case 1:
+ default:
Offset = SD_MMC_PHY_CP0_MPP_OFFSET;
break;
- default:
- return;
}
/*
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [edk2-platforms: PATCH v4 5/9] Marvell/Library: IcuLib: Fix debug information
2019-10-11 15:20 [edk2-platforms: PATCH v4 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (3 preceding siblings ...)
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 4/9] Marvell/Library: ArmadaSoCDescLib/MppLib: Extend Xenon information Marcin Wojtas
@ 2019-10-11 15:20 ` Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 6/9] Marvell/Cn9131Db: Introduce board support Marcin Wojtas
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2019-10-11 15:20 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
In case the number of CP11x components exceeded the maximum
of currently supported, the user is informed with the information.
It turned out that the print arguments were incorrect - fix it.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Marvell/Library/IcuLib/IcuLib.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Library/IcuLib/IcuLib.c
index 343c21b..4d9f174 100644
--- a/Silicon/Marvell/Library/IcuLib/IcuLib.c
+++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c
@@ -280,8 +280,8 @@ ArmadaIcuInitialize (
if (CpCount > ICU_MAX_SUPPORTED_UNITS) {
DEBUG ((DEBUG_ERROR,
"%a: Default ICU to GIC mapping is available for maximum %d CP110 units",
- ICU_MAX_SUPPORTED_UNITS,
- __FUNCTION__));
+ __FUNCTION__,
+ ICU_MAX_SUPPORTED_UNITS));
CpCount = ICU_MAX_SUPPORTED_UNITS;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [edk2-platforms: PATCH v4 6/9] Marvell/Cn9131Db: Introduce board support
2019-10-11 15:20 [edk2-platforms: PATCH v4 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (4 preceding siblings ...)
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 5/9] Marvell/Library: IcuLib: Fix debug information Marcin Wojtas
@ 2019-10-11 15:20 ` Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 7/9] Marvell/Cn9132Db: " Marcin Wojtas
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2019-10-11 15:20 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
This patch introduces all necessary components required
for building EDK2 firmware for CN9131-DB setup A.
In order to build this variant, '-D CN9131' flag should be added.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc | 72 ++++++++++++++
Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 5 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 57 ++++++++++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 2 +
| 2 +
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 29 ++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 98 ++++++++++++++++++++
7 files changed, 265 insertions(+)
create mode 100644 Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
diff --git a/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
new file mode 100644
index 0000000..7235b9f
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
@@ -0,0 +1,72 @@
+## @file
+# Component description file for the CN9131 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # CP115 count
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|2
+
+ # MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|3
+
+ # CP115 #1 MPP
+ gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x7, 0x2, 0x2, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ # ComPhy1
+ # 0: PCIE0 5 Gbps
+ # 1: PCIE0 5 Gbps
+ # 2: UNCONNECTED
+ # 3: USB3_HOST1 5 Gbps
+ # 4: SFI 10.31 Gbps
+ # 5: SATA1 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_UNCONNECTED), $(CP_USB3_HOST1), $(CP_SFI), $(CP_SATA1)}
+ gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_DEFAULT), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+
+ # UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ # MDIO
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+
+ # PHY
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+ # NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
index 59f3e9b..8e32891 100644
--- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
+++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
@@ -15,6 +15,8 @@
[Defines]
!if $(CN9130)
PLATFORM_NAME = Cn9130DbA
+!elseif $(CN9131)
+ PLATFORM_NAME = Cn9131DbA
!endif
PLATFORM_GUID = 087305a1-8ddd-4027-89ca-68a3ef78fcc7
PLATFORM_VERSION = 0.1
@@ -36,6 +38,9 @@
!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+!if $(CN9131)
+!include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
+!endif
[Components.common]
Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
new file mode 100644
index 0000000..bbf1b51
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf
@@ -0,0 +1,57 @@
+## @file
+# Component description file for PlatformAcpiTables module.
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+# Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Cn9131DbA/Ssdt.asl
+ Cn913xDbA/Dsdt.asl
+ Cn913xDbA/Mcfg.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Pptt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+[BuildOptions]
+ *_*_*_ASLCC_FLAGS = -DCN9131
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
index e1a5c34..3ca6374 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
@@ -15,5 +15,7 @@
#define CN9130_DB_VBUS1_LIMIT_PIN 5
#define CN9130_DB_SDMMC_VCC_PIN 14
#define CN9130_DB_SDMMC_VCCQ_PIN 15
+#define CN9131_DB_VBUS0_PIN 3
+#define CN9131_DB_VBUS0_LIMIT_PIN 2
#endif
--git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
index b5fd397..2838676 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h
@@ -18,6 +18,8 @@
#if defined(CN9130)
#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','0',' ',' ')
+#elif defined (CN9131)
+#define ACPI_OEM_TABLE_ID SIGNATURE_64('C','N','9','1','3','1',' ',' ')
#endif
/**
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
index 598c649..dded150 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
@@ -91,6 +91,33 @@ Cp0XhciInit (
MV_GPIO_DRIVER_TYPE_PCA95XX);
}
+STATIC CONST MV_GPIO_PIN mCp1XhciVbusPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP1_CONTROLLER0,
+ CN9131_DB_VBUS0_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP1_CONTROLLER0,
+ CN9131_DB_VBUS0_LIMIT_PIN,
+ TRUE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+Cp1XhciInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mCp1XhciVbusPins,
+ ARRAY_SIZE (mCp1XhciVbusPins),
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
+}
+
STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = {
{
MV_GPIO_DRIVER_TYPE_PCA95XX,
@@ -130,6 +157,8 @@ NonDiscoverableDeviceInitializerGet (
case 0:
case 1:
return Cp0XhciInit;
+ case 2:
+ return Cp1XhciInit;
}
}
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
new file mode 100644
index 0000000..99bc751
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
@@ -0,0 +1,98 @@
+/** @file
+
+ Secondary System Description Table Fields (SSDT)
+
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "IcuInterrupts.h"
+
+DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
+{
+ Scope (_SB)
+ {
+ Device (AHC1)
+ {
+ Name (_HID, "LNRO001E") // _HID: Hardware ID
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Name (_CLS, Package (0x03) // _CLS: Class Code
+ {
+ 0x01,
+ 0x06,
+ 0x01
+ })
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF4540000, // Address Base (MMIO)
+ 0x00030000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP1_SATA_H0
+ }
+ })
+ }
+
+ Device (XHC2)
+ {
+ Name (_HID, "PNP0D10") // _HID: Hardware ID
+ Name (_UID, 0x01) // _UID: Unique ID
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xF4510000, // Address Base (MMIO)
+ 0x00004000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_CP1_USB_H1
+ }
+ })
+ }
+ Device (PP21)
+ {
+ Name (_HID, "MRVL0110") // _HID: Hardware ID
+ Name (_CCA, 0x01) // Cache-coherent controller
+ Name (_UID, 0x00) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
+ Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "clock-frequency", 333333333 },
+ }
+ })
+ Device (ETH0)
+ {
+ Name (_ADR, 0x0)
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ CP_GIC_SPI_PP2_CP1_PORT0
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "port-id", 0 },
+ Package () { "gop-port-id", 0 },
+ Package () { "phy-mode", "10gbase-kr"},
+ }
+ })
+ }
+ }
+ }
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [edk2-platforms: PATCH v4 7/9] Marvell/Cn9132Db: Introduce board support
2019-10-11 15:20 [edk2-platforms: PATCH v4 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (5 preceding siblings ...)
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 6/9] Marvell/Cn9131Db: Introduce board support Marcin Wojtas
@ 2019-10-11 15:20 ` Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 8/9] Marvell/Drivers: SmbiosPlatformDxe: Load SMBIOS strings from PCD Marcin Wojtas
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 9/9] Marvell: Customize per-board SBMIOS strings Marcin Wojtas
8 siblings, 0 replies; 12+ messages in thread
From: Marcin Wojtas @ 2019-10-11 15:20 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
This patch introduces all necessary components required
for building EDK2 firmware for CN9132-DB setup A. Note
the ACPI is not yet available for this variant, due to
the current ICU (CP1xx interrupt controller) support
implementation.
In order to build this variant, '-D CN9132' flag should be added.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc | 72 +++++++++++
Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 13 +-
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf | 29 +++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 4 +
Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c | 135 ++++++++++++++++++++
Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 42 ++++++
Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc | 2 +
7 files changed, 296 insertions(+), 1 deletion(-)
create mode 100644 Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
create mode 100644 Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
diff --git a/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
new file mode 100644
index 0000000..a0b90fa
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
@@ -0,0 +1,72 @@
+## @file
+# Component description file for the CN9132 Development Board (variant A)
+#
+# Copyright (c) 2019 Marvell International Ltd.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ # CP115 count
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|3
+
+ # MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|4
+
+ # CP115 #2 MPP
+ gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000
+ gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x9, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x0, 0x0, 0x8, 0x0, 0x8, 0x0, 0x0, 0x2, 0x2, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0x0, 0x0, 0x0, 0xA, 0xB, 0xE, 0xE, 0xE, 0xE }
+ gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }
+ # ComPhy1
+ # 0: PCIE0 5 Gbps
+ # 1: PCIE0 5 Gbps
+ # 2: SATA0 5 Gbps
+ # 3: USB3_HOST1 5 Gbps
+ # 4: SFI 10.31 Gbps
+ # 5: PCIE2 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_SATA0), $(CP_USB3_HOST1), $(CP_SFI), $(CP_PCIE2)}
+ gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+
+ # UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ # MDIO
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+
+ # PHY
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+ # NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII), $(PHY_SFI), $(PHY_SFI) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }
+
+ # NonDiscoverableDevices
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1, 0x0, 0x1 }
diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
index 8e32891..3f6b70e 100644
--- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
+++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
@@ -17,6 +17,8 @@
PLATFORM_NAME = Cn9130DbA
!elseif $(CN9131)
PLATFORM_NAME = Cn9131DbA
+!elseif $(CN9132)
+ PLATFORM_NAME = Cn9132DbA
!endif
PLATFORM_GUID = 087305a1-8ddd-4027-89ca-68a3ef78fcc7
PLATFORM_VERSION = 0.1
@@ -38,16 +40,25 @@
!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
!include Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
-!if $(CN9131)
+!if $(CN9131) || $(CN9132)
!include Platform/Marvell/Cn913xDb/Cn9131DbA.dsc.inc
!endif
+!if $(CN9132)
+!include Platform/Marvell/Cn913xDb/Cn9132DbA.dsc.inc
+!endif
[Components.common]
Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf
+!ifndef $(CN9132)
[Components.AARCH64]
Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf
+!endif
[LibraryClasses.common]
+!if $(CN9132)
+ ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
+!else
ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
+!endif
NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
new file mode 100644
index 0000000..27a0214
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.inf
@@ -0,0 +1,29 @@
+## @file
+#
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9132DbABoardDescLib
+ FILE_GUID = cf7a0f12-45fe-417b-9c34-053605973b68
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmadaBoardDescLib
+
+[Sources]
+ Cn9132DbABoardDescLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Marvell/Marvell.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
index 3ca6374..a641420 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.h
@@ -17,5 +17,9 @@
#define CN9130_DB_SDMMC_VCCQ_PIN 15
#define CN9131_DB_VBUS0_PIN 3
#define CN9131_DB_VBUS0_LIMIT_PIN 2
+#define CN9132_DB_VBUS0_PIN 2
+#define CN9132_DB_VBUS0_LIMIT_PIN 0
+#define CN9132_DB_VBUS1_PIN 3
+#define CN9132_DB_VBUS1_LIMIT_PIN 1
#endif
diff --git a/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
new file mode 100644
index 0000000..d2846dd
--- /dev/null
+++ b/Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9132DbABoardDescLib.c
@@ -0,0 +1,135 @@
+/**
+*
+* Copyright (C) 2019, Marvell International Ltd. and its affiliates.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/ArmadaBoardDescLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/MvGpioLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+//
+// GPIO Expander
+//
+STATIC MV_GPIO_EXPANDER mGpioExpander = {
+ PCA9555_ID,
+ 0x21,
+ 0x0,
+};
+
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardGpioExpanderGet (
+ IN OUT MV_GPIO_EXPANDER **GpioExpanders,
+ IN OUT UINTN *GpioExpanderCount
+ )
+{
+ *GpioExpanderCount = 1;
+ *GpioExpanders = &mGpioExpander;
+
+ return EFI_SUCCESS;
+}
+
+//
+// PCIE
+//
+STATIC
+MV_PCIE_CONTROLLER mPcieController[] = {
+ { /* PCIE0 @0xF2640000 */
+ .PcieDbiAddress = 0xF2600000,
+ .ConfigSpaceAddress = 0xD0000000,
+ .HaveResetGpio = FALSE,
+ .PcieResetGpio = { 0 },
+ .PcieBusMin = 0,
+ .PcieBusMax = 0xFE,
+ .PcieIoTranslation = 0xDFF00000,
+ .PcieIoWinBase = 0x0,
+ .PcieIoWinSize = 0x10000,
+ .PcieMmio32Translation = 0,
+ .PcieMmio32WinBase = 0xC0000000,
+ .PcieMmio32WinSize = 0x10000000,
+ .PcieMmio64Translation = 0,
+ .PcieMmio64WinBase = MAX_UINT64,
+ .PcieMmio64WinSize = 0,
+ }
+};
+
+/**
+ Return the number and description of PCIE controllers used on the platform.
+
+ @param[in out] **PcieControllers Array containing PCIE controllers'
+ description.
+ @param[in out] *PcieControllerCount Amount of used PCIE controllers.
+
+ @retval EFI_SUCCESS The data were obtained successfully.
+ @retval other Return error status.
+
+**/
+EFI_STATUS
+EFIAPI
+ArmadaBoardPcieControllerGet (
+ IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,
+ IN OUT UINTN *PcieControllerCount
+ )
+{
+ *PcieControllers = mPcieController;
+ *PcieControllerCount = ARRAY_SIZE (mPcieController);
+
+ return EFI_SUCCESS;
+}
+
+//
+// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib
+//
+STATIC
+MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] = {
+ { /* eMMC 0xF06E0000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ TRUE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x40, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ },
+ { /* SD/MMC 0xF2780000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ FALSE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x19, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ },
+ { /* SD/MMC 0xF6780000 */
+ 0, /* SOC will be filled by MvBoardDescDxe */
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
+ FALSE, /* Xenon1v8Enabled */
+ FALSE, /* Xenon8BitBusEnabled */
+ FALSE, /* XenonSlowModeEnabled */
+ 0x19, /* XenonTuningStepDivisor */
+ EmbeddedSlot /* SlotType */
+ }
+};
+
+EFI_STATUS
+EFIAPI
+ArmadaBoardDescSdMmcGet (
+ OUT UINTN *SdMmcDevCount,
+ OUT MV_BOARD_SDMMC_DESC **SdMmcDesc
+ )
+{
+ *SdMmcDesc = mSdMmcDescTemplate;
+ *SdMmcDevCount = ARRAY_SIZE (mSdMmcDescTemplate);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
index dded150..42dc54a 100644
--- a/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
+++ b/Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.c
@@ -118,6 +118,45 @@ Cp1XhciInit (
MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
}
+STATIC CONST MV_GPIO_PIN mCp2XhciVbusPins[] = {
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS0_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS0_LIMIT_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS1_PIN,
+ TRUE,
+ },
+ {
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
+ MV_GPIO_CP2_CONTROLLER0,
+ CN9132_DB_VBUS1_LIMIT_PIN,
+ TRUE,
+ },
+};
+
+STATIC
+EFI_STATUS
+EFIAPI
+Cp2XhciInit (
+ IN NON_DISCOVERABLE_DEVICE *This
+ )
+{
+ return ConfigurePins (mCp2XhciVbusPins,
+ ARRAY_SIZE (mCp2XhciVbusPins),
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);
+}
+
STATIC CONST MV_GPIO_PIN mCp0SdMmcPins[] = {
{
MV_GPIO_DRIVER_TYPE_PCA95XX,
@@ -159,6 +198,9 @@ NonDiscoverableDeviceInitializerGet (
return Cp0XhciInit;
case 2:
return Cp1XhciInit;
+ case 3:
+ case 4:
+ return Cp2XhciInit;
}
}
diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc
index 0c321d1..78bdb79 100644
--- a/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc
+++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.fdf.inc
@@ -12,7 +12,9 @@
# DTB
INF RuleOverride = DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf
+!ifndef $(CN9132)
!if $(ARCH) == AARCH64
# ACPI support
INF RuleOverride = ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf
!endif
+!endif
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [edk2-platforms: PATCH v4 8/9] Marvell/Drivers: SmbiosPlatformDxe: Load SMBIOS strings from PCD
2019-10-11 15:20 [edk2-platforms: PATCH v4 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (6 preceding siblings ...)
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 7/9] Marvell/Cn9132Db: " Marcin Wojtas
@ 2019-10-11 15:20 ` Marcin Wojtas
2019-10-14 8:43 ` Leif Lindholm
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 9/9] Marvell: Customize per-board SBMIOS strings Marcin Wojtas
8 siblings, 1 reply; 12+ messages in thread
From: Marcin Wojtas @ 2019-10-11 15:20 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap, Patryk Duda
From: Patryk Duda <pdk@semihalf.com>
This patch implements convenient way of changing strings included
in SMBIOS Table1, Table2, Table3.
Strings can be altered by defining following PCDs:
gMarvellTokenSpaceGuid.PcdProductManufacturer
gMarvellTokenSpaceGuid.PcdProductPlatformName
gMarvellTokenSpaceGuid.PcdProductSerial
gMarvellTokenSpaceGuid.PcdProductVersion
Signed-off-by: Patryk Duda <pdk@semihalf.com>
---
Silicon/Marvell/Marvell.dec | 6 ++++++
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 4 ++++
Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 22 ++++++++++----------
3 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec
index d337d3e..cdf8154 100644
--- a/Silicon/Marvell/Marvell.dec
+++ b/Silicon/Marvell/Marvell.dec
@@ -169,6 +169,12 @@
gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034
gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035
+#Platform description
+ gMarvellTokenSpaceGuid.PcdProductManufacturer|"Marvell"|VOID*|0x50000100
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board"|VOID*|0x50000101
+ gMarvellTokenSpaceGuid.PcdProductSerial|"Serial Not Set"|VOID*|0x50000103
+ gMarvellTokenSpaceGuid.PcdProductVersion|"Revision unknown"|VOID*|0x50000102
+
#RTC
gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT64|0x40000052
diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
index 8b4586c..7722146 100644
--- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
@@ -36,6 +36,10 @@
[FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision
+ gMarvellTokenSpaceGuid.PcdProductManufacturer
+ gMarvellTokenSpaceGuid.PcdProductPlatformName
+ gMarvellTokenSpaceGuid.PcdProductSerial
+ gMarvellTokenSpaceGuid.PcdProductVersion
[Protocols]
gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
index 08f4fa7..d29478c 100644
--- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
+++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
@@ -101,10 +101,10 @@ STATIC SMBIOS_TABLE_TYPE1 mArmadaDefaultType1 = {
};
STATIC CHAR8 CONST *mArmadaDefaultType1Strings[] = {
- "Marvell \0",/* Manufacturer */
- "Armada 7k/8k Family Board \0",/* Product Name placeholder*/
- "Revision unknown \0",/* Version placeholder */
- " \0",/* 32 character buffer */
+ (CHAR8 *)PcdGetPtr (PcdProductManufacturer),
+ (CHAR8 *)PcdGetPtr (PcdProductPlatformName),
+ (CHAR8 *)PcdGetPtr (PcdProductVersion),
+ (CHAR8 *)PcdGetPtr (PcdProductSerial),
NULL
};
@@ -129,10 +129,10 @@ STATIC SMBIOS_TABLE_TYPE2 mArmadaDefaultType2 = {
};
STATIC CHAR8 CONST *mArmadaDefaultType2Strings[] = {
- "Marvell \0",/* Manufacturer */
- "Armada 7k/8k Family Board \0",/* Product Name placeholder*/
- "Revision unknown \0",/* Version placeholder */
- "Serial Not Set \0",/* Serial */
+ (CHAR8 *)PcdGetPtr (PcdProductManufacturer),
+ (CHAR8 *)PcdGetPtr (PcdProductPlatformName),
+ (CHAR8 *)PcdGetPtr (PcdProductVersion),
+ (CHAR8 *)PcdGetPtr (PcdProductSerial),
"Base of Chassis \0",/* Board location */
NULL
};
@@ -160,9 +160,9 @@ STATIC SMBIOS_TABLE_TYPE3 mArmadaDefaultType3 = {
};
STATIC CHAR8 CONST *mArmadaDefaultType3Strings[] = {
- "Marvell \0",/* Manufacturer placeholder */
- "Revision unknown \0",/* Version placeholder */
- "Serial Not Set \0",/* Serial placeholder */
+ (CHAR8 *)PcdGetPtr (PcdProductManufacturer),
+ (CHAR8 *)PcdGetPtr (PcdProductVersion),
+ (CHAR8 *)PcdGetPtr (PcdProductSerial),
NULL
};
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [edk2-platforms: PATCH v4 8/9] Marvell/Drivers: SmbiosPlatformDxe: Load SMBIOS strings from PCD
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 8/9] Marvell/Drivers: SmbiosPlatformDxe: Load SMBIOS strings from PCD Marcin Wojtas
@ 2019-10-14 8:43 ` Leif Lindholm
0 siblings, 0 replies; 12+ messages in thread
From: Leif Lindholm @ 2019-10-14 8:43 UTC (permalink / raw)
To: Marcin Wojtas; +Cc: devel, ard.biesheuvel, jsd, jaz, kostap, Patryk Duda
On Fri, Oct 11, 2019 at 05:20:30PM +0200, Marcin Wojtas wrote:
> From: Patryk Duda <pdk@semihalf.com>
>
> This patch implements convenient way of changing strings included
> in SMBIOS Table1, Table2, Table3.
>
> Strings can be altered by defining following PCDs:
> gMarvellTokenSpaceGuid.PcdProductManufacturer
> gMarvellTokenSpaceGuid.PcdProductPlatformName
> gMarvellTokenSpaceGuid.PcdProductSerial
> gMarvellTokenSpaceGuid.PcdProductVersion
>
> Signed-off-by: Patryk Duda <pdk@semihalf.com>
> ---
> Silicon/Marvell/Marvell.dec | 6 ++++++
> Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 4 ++++
> Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 22 ++++++++++----------
> 3 files changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec
> index d337d3e..cdf8154 100644
> --- a/Silicon/Marvell/Marvell.dec
> +++ b/Silicon/Marvell/Marvell.dec
> @@ -169,6 +169,12 @@
> gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034
> gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035
>
> +#Platform description
> + gMarvellTokenSpaceGuid.PcdProductManufacturer|"Marvell"|VOID*|0x50000100
> + gMarvellTokenSpaceGuid.PcdProductPlatformName|"Marvell Development Board"|VOID*|0x50000101
> + gMarvellTokenSpaceGuid.PcdProductSerial|"Serial Not Set"|VOID*|0x50000103
> + gMarvellTokenSpaceGuid.PcdProductVersion|"Revision unknown"|VOID*|0x50000102
> +
> #RTC
> gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT64|0x40000052
>
> diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
> index 8b4586c..7722146 100644
> --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
> +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
> @@ -36,6 +36,10 @@
>
> [FixedPcd]
> gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision
> + gMarvellTokenSpaceGuid.PcdProductManufacturer
> + gMarvellTokenSpaceGuid.PcdProductPlatformName
> + gMarvellTokenSpaceGuid.PcdProductSerial
> + gMarvellTokenSpaceGuid.PcdProductVersion
>
> [Protocols]
> gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
> diff --git a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
> index 08f4fa7..d29478c 100644
> --- a/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
> +++ b/Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
> @@ -101,10 +101,10 @@ STATIC SMBIOS_TABLE_TYPE1 mArmadaDefaultType1 = {
> };
>
> STATIC CHAR8 CONST *mArmadaDefaultType1Strings[] = {
> - "Marvell \0",/* Manufacturer */
> - "Armada 7k/8k Family Board \0",/* Product Name placeholder*/
> - "Revision unknown \0",/* Version placeholder */
> - " \0",/* 32 character buffer */
> + (CHAR8 *)PcdGetPtr (PcdProductManufacturer),
> + (CHAR8 *)PcdGetPtr (PcdProductPlatformName),
> + (CHAR8 *)PcdGetPtr (PcdProductVersion),
> + (CHAR8 *)PcdGetPtr (PcdProductSerial),
These really ought to be (CONST CHAR8 *), as the compiler informs you
if dropping the cast altogether:
pointer targets in initialization of ‘const CHAR8 *’ {aka ‘const char
*’} from ‘const UINT8 *’ {aka ‘const unsigned char *’} differ in signedness
The build error without the cast is related to the type the pointer is
pointing to (UINT8), not the const attribute.
This would fail if we started building with clang -Weverything, or
ecplicitly with -Wcast-qual:
error: cast from 'const unsigned char *' to 'char *' drops const
qualifier [-Werror,-Wcast-qual]
Could you resubmit a version of this patch addressing only this
concern, throughout?
Best Regards,
Leif
> NULL
> };
>
> @@ -129,10 +129,10 @@ STATIC SMBIOS_TABLE_TYPE2 mArmadaDefaultType2 = {
> };
>
> STATIC CHAR8 CONST *mArmadaDefaultType2Strings[] = {
> - "Marvell \0",/* Manufacturer */
> - "Armada 7k/8k Family Board \0",/* Product Name placeholder*/
> - "Revision unknown \0",/* Version placeholder */
> - "Serial Not Set \0",/* Serial */
> + (CHAR8 *)PcdGetPtr (PcdProductManufacturer),
> + (CHAR8 *)PcdGetPtr (PcdProductPlatformName),
> + (CHAR8 *)PcdGetPtr (PcdProductVersion),
> + (CHAR8 *)PcdGetPtr (PcdProductSerial),
> "Base of Chassis \0",/* Board location */
> NULL
> };
> @@ -160,9 +160,9 @@ STATIC SMBIOS_TABLE_TYPE3 mArmadaDefaultType3 = {
> };
>
> STATIC CHAR8 CONST *mArmadaDefaultType3Strings[] = {
> - "Marvell \0",/* Manufacturer placeholder */
> - "Revision unknown \0",/* Version placeholder */
> - "Serial Not Set \0",/* Serial placeholder */
> + (CHAR8 *)PcdGetPtr (PcdProductManufacturer),
> + (CHAR8 *)PcdGetPtr (PcdProductVersion),
> + (CHAR8 *)PcdGetPtr (PcdProductSerial),
> NULL
> };
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [edk2-platforms: PATCH v4 9/9] Marvell: Customize per-board SBMIOS strings
2019-10-11 15:20 [edk2-platforms: PATCH v4 0/9] Marvell Octeon CN913X SoC family support Marcin Wojtas
` (7 preceding siblings ...)
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 8/9] Marvell/Drivers: SmbiosPlatformDxe: Load SMBIOS strings from PCD Marcin Wojtas
@ 2019-10-11 15:20 ` Marcin Wojtas
2019-10-14 8:44 ` Leif Lindholm
8 siblings, 1 reply; 12+ messages in thread
From: Marcin Wojtas @ 2019-10-11 15:20 UTC (permalink / raw)
To: devel; +Cc: leif.lindholm, ard.biesheuvel, mw, jsd, jaz, kostap
Now that the customization of Type1/2/3 SBMIOS
tables strings is possible, adjust them for all
supported boards.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 4 ++++
Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 4 ++++
Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 11 +++++++++++
Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 5 +++++
4 files changed, 24 insertions(+)
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
index 523e60e..0c2c748 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
@@ -45,6 +45,10 @@
#
################################################################################
[PcdsFixedAtBuild.common]
+ #Platform description
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB"
+ gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.5"
+
#CP110 count
gMarvellTokenSpaceGuid.PcdMaxCpCount|1
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
index 4e6e62b..40aeb62 100644
--- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
@@ -45,6 +45,10 @@
#
################################################################################
[PcdsFixedAtBuild.common]
+ #Platform description
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 DB"
+ gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.4"
+
#MPP
gMarvellTokenSpaceGuid.PcdMppChipCount|3
diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
index 3f6b70e..a754c3e 100644
--- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
+++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
@@ -62,3 +62,14 @@
ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
!endif
NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
+
+[PcdsFixedAtBuild.common]
+ #Platform description
+ !if $(CN9130)
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9130 DB-A"
+ !elseif $(CN9131)
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9131 DB-A"
+ !elseif $(CN9132)
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9132 DB-A"
+ !endif
+ gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
index 2b42d75..fec0cc2 100644
--- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
@@ -46,6 +46,11 @@
#
################################################################################
[PcdsFixedAtBuild.common]
+ #Platform description
+ gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 MacchiatoBin"
+ gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.3"
+
#MPP
gMarvellTokenSpaceGuid.PcdMppChipCount|3
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [edk2-platforms: PATCH v4 9/9] Marvell: Customize per-board SBMIOS strings
2019-10-11 15:20 ` [edk2-platforms: PATCH v4 9/9] Marvell: Customize per-board SBMIOS strings Marcin Wojtas
@ 2019-10-14 8:44 ` Leif Lindholm
0 siblings, 0 replies; 12+ messages in thread
From: Leif Lindholm @ 2019-10-14 8:44 UTC (permalink / raw)
To: Marcin Wojtas; +Cc: devel, ard.biesheuvel, jsd, jaz, kostap
On Fri, Oct 11, 2019 at 05:20:31PM +0200, Marcin Wojtas wrote:
> Now that the customization of Type1/2/3 SBMIOS
> tables strings is possible, adjust them for all
> supported boards.
>
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 4 ++++
> Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 4 ++++
> Platform/Marvell/Cn913xDb/Cn913xDbA.dsc | 11 +++++++++++
> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 5 +++++
> 4 files changed, 24 insertions(+)
>
> diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
> index 523e60e..0c2c748 100644
> --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
> +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
> @@ -45,6 +45,10 @@
> #
> ################################################################################
> [PcdsFixedAtBuild.common]
> + #Platform description
> + gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 7040 DB"
> + gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.5"
> +
> #CP110 count
> gMarvellTokenSpaceGuid.PcdMaxCpCount|1
>
> diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
> index 4e6e62b..40aeb62 100644
> --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
> +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
> @@ -45,6 +45,10 @@
> #
> ################################################################################
> [PcdsFixedAtBuild.common]
> + #Platform description
> + gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 DB"
> + gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.4"
> +
> #MPP
> gMarvellTokenSpaceGuid.PcdMppChipCount|3
>
> diff --git a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
> index 3f6b70e..a754c3e 100644
> --- a/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
> +++ b/Platform/Marvell/Cn913xDb/Cn913xDbA.dsc
> @@ -62,3 +62,14 @@
> ArmadaBoardDescLib|Platform/Marvell/Cn913xDb/BoardDescriptionLib/Cn9130DbABoardDescLib.inf
> !endif
> NonDiscoverableInitLib|Platform/Marvell/Cn913xDb/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
> +
> +[PcdsFixedAtBuild.common]
> + #Platform description
> + !if $(CN9130)
> + gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9130 DB-A"
> + !elseif $(CN9131)
> + gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9131 DB-A"
> + !elseif $(CN9132)
> + gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN9132 DB-A"
> + !endif
> + gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"
> diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
> index 2b42d75..fec0cc2 100644
> --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
> +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
> @@ -46,6 +46,11 @@
> #
> ################################################################################
> [PcdsFixedAtBuild.common]
> + #Platform description
> + gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"
> + gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 MacchiatoBin"
> + gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.3"
> +
> #MPP
> gMarvellTokenSpaceGuid.PcdMppChipCount|3
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 12+ messages in thread