[edk2-platforms: PATCH v4 4/9] Marvell/Library: ArmadaSoCDescLib/MppLib: Extend Xenon information

["Marcin Wojtas" <mw@semihalf.com>]

Hitherto SoC description and MppLib libraries code assumed
that there could be only two Xenon SdMmc controller
instances in the SoC. Remove those limitations, so that
to support CN913x SoCs, which may have up to 4 of such interfaces.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
---
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h |  5 +--
 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 34 +++++++++++++-------
 Silicon/Marvell/Library/MppLib/MppLib.c                                        |  4 +--
 3 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
index 0296d43..265b4f4 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
@@ -90,8 +90,9 @@
 //
 // Platform description of SDMMC controllers
 //
-#define MV_SOC_MAX_SDMMC_COUNT           2
-#define MV_SOC_SDMMC_BASE(Index)         ((Index) == 0 ? 0xF06E0000 : 0xF2780000)
+#define MV_SOC_SDMMC_PER_CP_COUNT        1
+#define MV_SOC_AP80X_SDMMC_BASE          0xF06E0000
+#define MV_SOC_CP_SDMMC_BASE(Cp)         (MV_SOC_CP_BASE (Cp) + 0x780000)
 
 //
 // Platform description of UTMI PHY's
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
index 5947601..3ffd57e 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
@@ -349,26 +349,36 @@ EFI_STATUS
 EFIAPI
 ArmadaSoCDescSdMmcGet (
   IN OUT MV_SOC_SDMMC_DESC  **SdMmcDesc,
-  IN OUT UINTN               *DescCount
+  IN OUT UINTN               *Count
   )
 {
-  MV_SOC_SDMMC_DESC *Desc;
-  UINTN Index;
+  MV_SOC_SDMMC_DESC *SdMmc;
+  UINTN CpCount, CpIndex;
 
-  Desc = AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC_DESC));
-  if (Desc == NULL) {
+  CpCount = FixedPcdGet8 (PcdMaxCpCount);
+
+  *Count = CpCount * MV_SOC_SDMMC_PER_CP_COUNT + MV_SOC_AP806_COUNT;
+  SdMmc = AllocateZeroPool (*Count * sizeof (MV_SOC_SDMMC_DESC));
+  if (SdMmc == NULL) {
     DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
     return EFI_OUT_OF_RESOURCES;
   }
 
-  for (Index = 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) {
-    Desc[Index].SdMmcBaseAddress = MV_SOC_SDMMC_BASE (Index);
-    Desc[Index].SdMmcMemSize = SIZE_1KB;
-    Desc[Index].SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent;
-  }
+  *SdMmcDesc = SdMmc;
+
+  /* AP80x controller */
+  SdMmc->SdMmcBaseAddress = MV_SOC_AP80X_SDMMC_BASE;
+  SdMmc->SdMmcMemSize = SIZE_1KB;
+  SdMmc->SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent;
+  SdMmc++;
 
-  *SdMmcDesc = Desc;
-  *DescCount = MV_SOC_MAX_SDMMC_COUNT;
+  /* CP11x controllers */
+  for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
+    SdMmc->SdMmcBaseAddress = MV_SOC_CP_SDMMC_BASE (CpIndex);
+    SdMmc->SdMmcMemSize = SIZE_1KB;
+    SdMmc->SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent;
+    SdMmc++;
+  }
 
   return EFI_SUCCESS;
 }
diff --git a/Silicon/Marvell/Library/MppLib/MppLib.c b/Silicon/Marvell/Library/MppLib/MppLib.c
index 40d9077..f20668d 100644
--- a/Silicon/Marvell/Library/MppLib/MppLib.c
+++ b/Silicon/Marvell/Library/MppLib/MppLib.c
@@ -139,11 +139,9 @@ SetSdMmcPhyMpp (
   case 0:
     Offset = SD_MMC_PHY_AP_MPP_OFFSET;
     break;
-  case 1:
+  default:
     Offset = SD_MMC_PHY_CP0_MPP_OFFSET;
     break;
-  default:
-    return;
   }
 
   /*
-- 
2.7.4