From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com,
Michael D Kinney <michael.d.kinney@intel.com>,
Liming Gao <liming.gao@intel.com>,
Leif Lindholm <leif.lindholm@linaro.org>,
Gilbert Chen <gilbert.chen@hpe.com>
Subject: [edk2-staging/RISC-V-V2 PATCH v3 10/39] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
Date: Mon, 28 Oct 2019 09:58:48 +0800 [thread overview]
Message-ID: <1572227957-13169-11-git-send-email-abner.chang@hpe.com> (raw)
In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com>
Support RISC-V image relocation.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
.../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 9 ++
MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
.../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 133 +++++++++++++++++++++
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
5 files changed, 151 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
index 395c140..50546eb 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
@@ -3,6 +3,7 @@
# The IPF version library supports loading IPF and EBC PE/COFF image.
# The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
# The X64 version library support loading IA32, X64 and EBC PE/COFF images.
+# The RISC-V version library support loading RISC-V images.
#
# Caution: This module requires additional review when modified.
# This library will have external input - PE/COFF image.
@@ -11,6 +12,7 @@
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -41,6 +43,9 @@
[Sources.ARM]
Arm/PeCoffLoaderEx.c
+[Sources.RISCV64]
+ RiscV/PeCoffLoaderEx.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
index b74277f..f8eea65 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
@@ -2,6 +2,7 @@
Declaration of internal functions in PE/COFF Lib.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -16,6 +17,14 @@
#include <Library/PeCoffExtraActionLib.h>
#include <IndustryStandard/PeImage.h>
+//
+// Macro definitions for RISC-V architecture.
+//
+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
+#define RISCV_IMM_BITS 12
+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
+#define RISCV_CONST_HIGH_PART(VALUE) \
+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
/**
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
index 07bb62f..25ffcb1 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
@@ -1,6 +1,6 @@
/** @file
Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but
- only supports relocating IA32, x64, IPF, and EBC images.
+ only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
Caution: This file requires additional review when modified.
This library will have external input - PE/COFF image.
@@ -17,6 +17,7 @@
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
new file mode 100644
index 0000000..e4aba4c
--- /dev/null
+++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
@@ -0,0 +1,133 @@
+/** @file
+ PE/Coff loader for RISC-V PE image
+
+ Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "BasePeCoffLibInternals.h"
+#include <Library/BaseLib.h>
+
+/**
+ Performs an RISC-V specific relocation fixup and is a no-op on
+ other instruction sets.
+ RISC-V splits 32-bit fixup into 20bit and 12-bit with two relocation
+ types. We have to know the lower 12-bit fixup first then we can deal
+ carry over on high 20-bit fixup. So we log the high 20-bit in
+ FixupData.
+
+ @param Reloc The pointer to the relocation record.
+ @param Fixup The pointer to the address to fix up.
+ @param FixupData The pointer to a buffer to log the fixups.
+ @param Adjust The offset to adjust the fixup.
+
+ @return Status code.
+
+**/
+RETURN_STATUS
+PeCoffLoaderRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ UINT32 Value;
+ UINT32 Value2;
+ UINT32 *RiscVHi20Fixup;
+
+ switch ((*Reloc) >> 12) {
+ case EFI_IMAGE_REL_BASED_RISCV_HI20:
+ *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup;
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
+ RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
+ if (RiscVHi20Fixup != NULL) {
+
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\
+ (RV_X (*(UINT32 *)Fixup, 0, 20));
+ }
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
+ RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
+ if (RiscVHi20Fixup != NULL) {
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ Value2 = *(UINT32 *)Fixup & 0x01fff07f;
+ Value &= RISCV_IMM_REACH - 1;
+ *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
+ }
+ break;
+
+ default:
+ return RETURN_UNSUPPORTED;
+
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Returns TRUE if the machine type of PE/COFF image is supported. Supported
+ does not mean the image can be executed it means the PE/COFF loader supports
+ loading and relocating of the image type. It's up to the caller to support
+ the entry point.
+
+ @param Machine Machine type from the PE Header.
+
+ @return TRUE if this PE/COFF loader can load the image
+
+**/
+BOOLEAN
+PeCoffLoaderImageFormatSupported (
+ IN UINT16 Machine
+ )
+{
+ if (Machine == IMAGE_FILE_MACHINE_RISCV64) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Performs an Itanium-based specific re-relocation fixup and is a no-op on other
+ instruction sets. This is used to re-relocated the image into the EFI virtual
+ space for runtime calls.
+
+ @param Reloc The pointer to the relocation record.
+ @param Fixup The pointer to the address to fix up.
+ @param FixupData The pointer to a buffer to log the fixups.
+ @param Adjust The offset to adjust the fixup.
+
+ @return Status code.
+
+**/
+RETURN_STATUS
+PeHotRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ return RETURN_UNSUPPORTED;
+}
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
index b0ea702..cf45f1d 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
@@ -4,6 +4,7 @@
// The IPF version library supports loading IPF and EBC PE/COFF image.
// The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
// The X64 version library support loading IA32, X64 and EBC PE/COFF images.
+// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COFF images.
//
// Caution: This module requires additional review when modified.
// This library will have external input - PE/COFF image.
@@ -12,6 +13,7 @@
//
// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
--
2.7.4
next prev parent reply other threads:[~2019-10-28 2:31 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 01/39] RiscVPkg: RISC-V processor package Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 02/39] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
2019-11-21 16:24 ` Leif Lindholm
2019-12-19 4:09 ` [edk2-devel] " Abner Chang
2019-12-19 13:21 ` Leif Lindholm
2019-12-19 14:48 ` Abner Chang
[not found] ` <15E1CD20DD2FE7F1.29030@groups.io>
2019-12-20 3:04 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 04/39] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 05/39] MdePkg/Include: RISC-V definitions Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 06/39] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 07/39] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 08/39] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 09/39] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
2019-11-21 16:36 ` Leif Lindholm
2019-10-28 1:58 ` Abner Chang [this message]
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 11/39] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 12/39] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 13/39] MdeModulePkg/Logo Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 14/39] NetworkPkg Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 15/39] RiscVPkg/Library: RISC-V CPU library Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 16/39] RiscVPkg/Library: Add RISC-V exception library Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 17/39] RiscVPkg/Library: Add RISC-V timer library Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 18/39] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
2019-11-21 16:48 ` [edk2-devel] " Leif Lindholm
2019-12-19 6:00 ` Abner Chang
2019-12-20 15:04 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 19/39] RiscVPkg/Library: RISC-V platform level DxeIPL libraries Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 20/39] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 21/39] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 22/39] RiscVPlatformPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 23/39] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 24/39] BaseTools: BaseTools changes for RISC-V platform Abner Chang
2019-11-21 16:55 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts Abner Chang
2019-11-19 18:17 ` [edk2-devel] " Mark Salter
2019-11-20 8:23 ` Abner Chang
2019-11-21 7:40 ` Abner Chang
2019-11-21 16:56 ` Leif Lindholm
2019-11-22 3:49 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 26/39] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 27/39] RiscVPkg/RiscVOpensbLlib: Add submodule opensbi Abner Chang
2019-11-21 17:00 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 28/39] RiscVPlatformPkg/FirmwareContextProcessorSpecificLib:Add FirmwareContextProcessorSpecificLib module Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib Abner Chang
2019-11-21 17:02 ` Leif Lindholm
2019-11-22 12:28 ` Abner Chang
2019-11-22 14:08 ` Leif Lindholm
2019-11-22 14:19 ` Abner Chang
2019-11-22 14:55 ` Leif Lindholm
2019-11-22 16:05 ` [edk2-devel] " Abner Chang
2019-11-22 16:32 ` Leif Lindholm
2019-11-23 7:38 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 30/39] RiscVPlatformPkg/OpensbiPlatformLibNull: NULL instance of RiscVOpensbiPlatformLib Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 31/39] RiscVPlatformPkg/PlatformMemoryTestLibNull: NULL instance of PlatformMemoryTestLib Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 32/39] RiscVPlatformPkg/PlatformUpdateProgressLibNull: NULL instance of PlatformUpdateProgressLib Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 33/39] RiscVPlatformPkg/PlatformBootManagerLib: Platform Boot Manager library Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 34/39] RiscVPkg/RiscVPlatformTimerLibNull: NULL instance of RISC-V platform timer library Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 35/39] RiscVPlatformPkg/SecMain: RISC-V SecMain module Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 36/39] RiscVPlatformPkg: Add RiscVPlatformPkg Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md Abner Chang
2019-11-21 17:09 ` Leif Lindholm
2019-11-22 3:57 ` [edk2-devel] " Abner Chang
2019-11-22 9:34 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 38/39] edk2-staging: Revise Maintainers.txt for RISC-V packages Abner Chang
2019-10-29 1:05 ` [edk2-devel] " Laszlo Ersek
2019-10-29 1:31 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md Abner Chang
2019-10-29 1:07 ` [edk2-devel] " Laszlo Ersek
2019-10-29 1:35 ` Abner Chang
2019-10-29 2:01 ` Leif Lindholm
2019-10-31 8:20 ` Laszlo Ersek
2019-11-21 17:15 ` Leif Lindholm
2019-11-22 2:05 ` Abner Chang
2019-11-22 9:42 ` Leif Lindholm
2019-11-22 11:46 ` Abner Chang
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