From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.558.1572229908179072247 for ; Sun, 27 Oct 2019 19:31:48 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=02044412f4=abner.chang@hpe.com) Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S2VlJA004926; Mon, 28 Oct 2019 02:31:48 GMT Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com with ESMTP id 2vvbh619mk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 02:31:47 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 81EC2BB; Mon, 28 Oct 2019 02:31:31 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id B616E47; Mon, 28 Oct 2019 02:31:29 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Michael D Kinney , Liming Gao , Leif Lindholm , Gilbert Chen Subject: [edk2-staging/RISC-V-V2 PATCH v3 10/39] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code. Date: Mon, 28 Oct 2019 09:58:48 +0800 Message-Id: <1572227957-13169-11-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-27_09:2019-10-25,2019-10-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 adultscore=0 phishscore=0 suspectscore=1 mlxscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1910280025 Support RISC-V image relocation. Signed-off-by: Abner Chang Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 + .../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 9 ++ MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +- .../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 133 +++++++++++++++++++++ MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 + 5 files changed, 151 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf index 395c140..50546eb 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf @@ -3,6 +3,7 @@ # The IPF version library supports loading IPF and EBC PE/COFF image. # The IA32 version library support loading IA32, X64 and EBC PE/COFF images. # The X64 version library support loading IA32, X64 and EBC PE/COFF images. +# The RISC-V version library support loading RISC-V images. # # Caution: This module requires additional review when modified. # This library will have external input - PE/COFF image. @@ -11,6 +12,7 @@ # # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+# Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +43,9 @@ [Sources.ARM] Arm/PeCoffLoaderEx.c +[Sources.RISCV64] + RiscV/PeCoffLoaderEx.c + [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h index b74277f..f8eea65 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h @@ -2,6 +2,7 @@ Declaration of internal functions in PE/COFF Lib. Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -16,6 +17,14 @@ #include #include +// +// Macro definitions for RISC-V architecture. +// +#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) +#define RISCV_IMM_BITS 12 +#define RISCV_IMM_REACH (1LL< Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c new file mode 100644 index 0000000..e4aba4c --- /dev/null +++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c @@ -0,0 +1,133 @@ +/** @file + PE/Coff loader for RISC-V PE image + + Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include "BasePeCoffLibInternals.h" +#include + +/** + Performs an RISC-V specific relocation fixup and is a no-op on + other instruction sets. + RISC-V splits 32-bit fixup into 20bit and 12-bit with two relocation + types. We have to know the lower 12-bit fixup first then we can deal + carry over on high 20-bit fixup. So we log the high 20-bit in + FixupData. + + @param Reloc The pointer to the relocation record. + @param Fixup The pointer to the address to fix up. + @param FixupData The pointer to a buffer to log the fixups. + @param Adjust The offset to adjust the fixup. + + @return Status code. + +**/ +RETURN_STATUS +PeCoffLoaderRelocateImageEx ( + IN UINT16 *Reloc, + IN OUT CHAR8 *Fixup, + IN OUT CHAR8 **FixupData, + IN UINT64 Adjust + ) +{ + UINT32 Value; + UINT32 Value2; + UINT32 *RiscVHi20Fixup; + + switch ((*Reloc) >> 12) { + case EFI_IMAGE_REL_BASED_RISCV_HI20: + *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup; + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12I: + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData)); + if (RiscVHi20Fixup != NULL) { + + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |= ~(RISCV_IMM_REACH-1); + } + Value += Value2; + Value += (UINT32)Adjust; + Value2 = RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\ + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12)); + *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\ + (RV_X (*(UINT32 *)Fixup, 0, 20)); + } + break; + + case EFI_IMAGE_REL_BASED_RISCV_LOW12S: + RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData)); + if (RiscVHi20Fixup != NULL) { + Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12); + Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5)); + if (Value2 & (RISCV_IMM_REACH/2)) { + Value2 |= ~(RISCV_IMM_REACH-1); + } + Value += Value2; + Value += (UINT32)Adjust; + Value2 = RISCV_CONST_HIGH_PART (Value); + *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \ + (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12)); + Value2 = *(UINT32 *)Fixup & 0x01fff07f; + Value &= RISCV_IMM_REACH - 1; + *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25))); + } + break; + + default: + return RETURN_UNSUPPORTED; + + } + return RETURN_SUCCESS; +} + +/** + Returns TRUE if the machine type of PE/COFF image is supported. Supported + does not mean the image can be executed it means the PE/COFF loader supports + loading and relocating of the image type. It's up to the caller to support + the entry point. + + @param Machine Machine type from the PE Header. + + @return TRUE if this PE/COFF loader can load the image + +**/ +BOOLEAN +PeCoffLoaderImageFormatSupported ( + IN UINT16 Machine + ) +{ + if (Machine == IMAGE_FILE_MACHINE_RISCV64) { + return TRUE; + } + + return FALSE; +} + +/** + Performs an Itanium-based specific re-relocation fixup and is a no-op on other + instruction sets. This is used to re-relocated the image into the EFI virtual + space for runtime calls. + + @param Reloc The pointer to the relocation record. + @param Fixup The pointer to the address to fix up. + @param FixupData The pointer to a buffer to log the fixups. + @param Adjust The offset to adjust the fixup. + + @return Status code. + +**/ +RETURN_STATUS +PeHotRelocateImageEx ( + IN UINT16 *Reloc, + IN OUT CHAR8 *Fixup, + IN OUT CHAR8 **FixupData, + IN UINT64 Adjust + ) +{ + return RETURN_UNSUPPORTED; +} diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni index b0ea702..cf45f1d 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni @@ -4,6 +4,7 @@ // The IPF version library supports loading IPF and EBC PE/COFF image. // The IA32 version library support loading IA32, X64 and EBC PE/COFF images. // The X64 version library support loading IA32, X64 and EBC PE/COFF images. +// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COFF images. // // Caution: This module requires additional review when modified. // This library will have external input - PE/COFF image. @@ -12,6 +13,7 @@ // // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
// // SPDX-License-Identifier: BSD-2-Clause-Patent // -- 2.7.4