From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web12.561.1572229908841978044 for ; Sun, 27 Oct 2019 19:31:49 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=02044412f4=abner.chang@hpe.com) Received: from pps.filterd (m0150244.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S2VkEe021309; Mon, 28 Oct 2019 02:31:48 GMT Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2vvet60gjb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 02:31:47 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 0EBA559; Mon, 28 Oct 2019 02:31:44 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id B014D47; Mon, 28 Oct 2019 02:31:42 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Leif Lindholm , Gilbert Chen Subject: [edk2-staging/RISC-V-V2 PATCH v3 16/39] RiscVPkg/Library: Add RISC-V exception library Date: Mon, 28 Oct 2019 09:58:54 +0800 Message-Id: <1572227957-13169-17-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-27_09:2019-10-25,2019-10-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 suspectscore=1 priorityscore=1501 phishscore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1910280025 Initial RISC-V Supervisor Mode trap handler. Signed-off-by: Abner Chang Cc: Leif Lindholm Cc: Gilbert Chen --- .../CpuExceptionHandlerDxeLib.inf | 43 +++++ .../RiscVExceptionLib/CpuExceptionHandlerLib.h | 16 ++ .../RiscVExceptionLib/CpuExceptionHandlerLib.c | 191 +++++++++++++++++++++ .../RiscVExceptionLib/CpuExceptionHandlerLib.uni | 13 ++ .../RiscVExceptionLib/SupervisorTrapHandler.S | 88 ++++++++++ 5 files changed, 351 insertions(+) create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni create mode 100644 RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf new file mode 100644 index 0000000..2463bac --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf @@ -0,0 +1,43 @@ +## @file +# RISC-V CPU Exception Handler Library +# +# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = CpuExceptionHandlerLib + MODULE_UNI_FILE = CpuExceptionHandlerLib.uni + FILE_GUID = 16309FCF-E900-459C-B071-052118394D11 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = CpuExceptionHandlerLib + CONSTRUCTOR = CpuExceptionHandlerLibConstructor + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources.RISCV64] + SupervisorTrapHandler.S + +[Sources.common] + CpuExceptionHandlerLib.c + CpuExceptionHandlerLib.h + +[LibraryClasses] + BaseLib + DebugLib + RiscVCpuLib + UefiBootServicesTableLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h new file mode 100644 index 0000000..1d141d1 --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h @@ -0,0 +1,16 @@ +/**@file + + RISC-V Exception Handler library definition file. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_ +#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_ + +extern void SupervisorModeTrap(void); + +#endif diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c new file mode 100644 index 0000000..e25ce3a --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c @@ -0,0 +1,191 @@ +/** @file + RISC-V Exception Handler library implementition. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "CpuExceptionHandlerLib.h" + +STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2]; + +/** + Initializes all CPU exceptions entries and provides the default exception handlers. + + Caller should try to get an array of interrupt and/or exception vectors that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS CPU Exception Entries have been successfully initialized + with default exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + return EFI_SUCCESS; +} + +/** + Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers. + + Caller should try to get an array of interrupt and/or exception vectors that are in use and need to + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. + If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. + If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly. + + @param[in] VectorInfo Pointer to reserved vector list. + + @retval EFI_SUCCESS All CPU interrupt/exception entries have been successfully initialized + with default interrupt/exception handlers. + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuInterruptHandlers ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL + ) +{ + return EFI_SUCCESS; +} + +/** + Registers a function to be called from the processor interrupt handler. + + This function registers and enables the handler specified by InterruptHandler for a processor + interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the + handler for the processor interrupt or exception type specified by InterruptType is uninstalled. + The installed handler is called once for each processor interrupt or exception. + NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned. + + @param[in] InterruptType Defines which interrupt or exception to hook. + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called + when a processor interrupt occurs. If this parameter is NULL, then the handler + will be uninstalled. + + @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled. + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was + previously installed. + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not + previously installed. + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported, + or this function is not supported. +**/ +EFI_STATUS +EFIAPI +RegisterCpuInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler + ) +{ + + DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, InterruptType, InterruptHandler)); + mInterruptHandlers[InterruptType] = InterruptHandler; + return EFI_SUCCESS; +} +/** + Machine mode trap handler. + +**/ +VOID +RiscVSupervisorModeTrapHandler ( + VOID + ) +{ + EFI_SYSTEM_CONTEXT RiscVSystemContext; + UINTN SCause; + + // + // Check scasue register. + // + SCause = (UINTN)csr_read(RISCV_CSR_SUPERVISOR_SCAUSE); + if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) != 0) { + // + // This is interrupt event. + // + SCause &= ~(1UL << (sizeof (UINTN) * 8- 1)); + if((SCause == SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL)) { + mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, (CONST EFI_SYSTEM_CONTEXT)RiscVSystemContext); + } + } +} + +/** + Initializes all CPU exceptions entries with optional extra initializations. + + By default, this method should include all functionalities implemented by + InitializeCpuExceptionHandlers(), plus extra initialization works, if any. + This could be done by calling InitializeCpuExceptionHandlers() directly + in this method besides the extra works. + + InitData is optional and its use and content are processor arch dependent. + The typical usage of it is to convey resources which have to be reserved + elsewhere and are necessary for the extra initializations of exception. + + @param[in] VectorInfo Pointer to reserved vector list. + @param[in] InitData Pointer to data optional for extra initializations + of exception. + + @retval EFI_SUCCESS The exceptions have been successfully + initialized. + @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid + content. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +InitializeCpuExceptionHandlersEx ( + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, + IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL + ) +{ + return InitializeCpuExceptionHandlers (VectorInfo); +} + +/** + The constructor function to initial interrupt handlers in + RISCV_MACHINE_MODE_CONTEXT. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The destructor completed successfully. + @retval Other value The destructor did not complete successfully. + +**/ +EFI_STATUS +EFIAPI +CpuExceptionHandlerLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + // + // Set Superviosr mode trap handler. + // + csr_write(CSR_STVEC, SupervisorModeTrap); + + return EFI_SUCCESS; +} diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni new file mode 100644 index 0000000..00cca22 --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni @@ -0,0 +1,13 @@ +// /** @file +// +// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Exception Handler Librarys." + +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU Exception Handler Librarys." + diff --git a/RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S b/RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S new file mode 100644 index 0000000..7d3cdd8 --- /dev/null +++ b/RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S @@ -0,0 +1,88 @@ +/** @file + RISC-V Processor supervisor mode trap handler + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + + .align 3 + .section .entry, "ax", %progbits + .globl SupervisorModeTrap +SupervisorModeTrap: + addi sp, sp, -34 * 8 + /* Save all general regisers except SP and T0 */ + sd ra, 1 * 8(sp) + sd gp, 2 * 8(sp) + sd tp, 3 * 8(sp) + sd t1, 4 * 8(sp) + sd t2, 5 * 8(sp) + sd s0, 6 * 8(sp) + sd s1, 7 * 8(sp) + sd a0, 8 * 8(sp) + sd a1, 9 * 8(sp) + sd a2, 10 * 8(sp) + sd a3, 11 * 8(sp) + sd a4, 12 * 8(sp) + sd a5, 13 * 8(sp) + sd a6, 14 * 8(sp) + sd a7, 15 * 8(sp) + sd s2, 16 * 8(sp) + sd s3, 17 * 8(sp) + sd s4, 18 * 8(sp) + sd s5, 19 * 8(sp) + sd s6, 20 * 8(sp) + sd s7, 21 * 8(sp) + sd s8, 22 * 8(sp) + sd s9, 23 * 8(sp) + sd s10, 24 * 8(sp) + sd s11, 25 * 8(sp) + sd t3, 26 * 8(sp) + sd t4, 27 * 8(sp) + sd t5, 28 * 8(sp) + sd t6, 29 * 8(sp) + + /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */ + call RiscVSupervisorModeTrapHandler + + /* Restore all general regisers except SP and T0 */ + ld ra, 1 * 8(sp) + ld gp, 2 * 8(sp) + ld tp, 3 * 8(sp) + ld t1, 4 * 8(sp) + ld t2, 5 * 8(sp) + ld s0, 6 * 8(sp) + ld s1, 7 * 8(sp) + ld a0, 8 * 8(sp) + ld a1, 9 * 8(sp) + ld a2, 10 * 8(sp) + ld a3, 11 * 8(sp) + ld a4, 12 * 8(sp) + ld a5, 13 * 8(sp) + ld a6, 14 * 8(sp) + ld a7, 15 * 8(sp) + ld s2, 16 * 8(sp) + ld s3, 17 * 8(sp) + ld s4, 18 * 8(sp) + ld s5, 19 * 8(sp) + ld s6, 20 * 8(sp) + ld s7, 21 * 8(sp) + ld s8, 22 * 8(sp) + ld s9, 23 * 8(sp) + ld s10, 24 * 8(sp) + ld s11, 25 * 8(sp) + ld t3, 26 * 8(sp) + ld t4, 27 * 8(sp) + ld t5, 28 * 8(sp) + ld t6, 29 * 8(sp) + addi sp, sp, 34 * 8 + sret -- 2.7.4