From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com, Leif Lindholm <leif.lindholm@linaro.org>,
Gilbert Chen <gilbert.chen@hpe.com>
Subject: [edk2-staging/RISC-V-V2 PATCH v3 19/39] RiscVPkg/Library: RISC-V platform level DxeIPL libraries.
Date: Mon, 28 Oct 2019 09:58:57 +0800 [thread overview]
Message-ID: <1572227957-13169-20-git-send-email-abner.chang@hpe.com> (raw)
In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com>
RiscVDxeIplHandoffLib.inf: Simply use stack switch to hand off to DXE
phase.
RiscVDxeIplHandoffOpenSbiLib.inf: Hand off to DXE phase using OpenSBI
interface.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../RiscVDxeIplHandoffLib.inf | 32 +++++++
.../RiscVDxeIplHandoffOpenSbiLib.inf | 33 +++++++
.../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 +++++++++
.../RiscVDxeIplHandoffOpenSbiLib.c | 101 +++++++++++++++++++++
4 files changed, 207 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
new file mode 100644
index 0000000..986db1d
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Instance of RISC-V DXE IPL to DXE core handoff platform library
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformDxeIplLib
+ FILE_GUID = 2A77EE71-9F55-43F9-8773-7854A5B56086
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscVDxeIplHandoffLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
new file mode 100644
index 0000000..262071d
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Instance of RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformDxeIplLib
+ FILE_GUID = 906A4BB9-8DE2-4CE0-A609-23818A8FF514
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscVDxeIplHandoffOpenSbiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
new file mode 100644
index 0000000..211b4e8
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
@@ -0,0 +1,41 @@
+/** @file
+ RISC-V platform level DXE core hand off library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+
+ //
+ // Transfer the control to the entry point of DxeCore.
+ //
+ SwitchStack (
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
+ HobList.Raw,
+ NULL,
+ TopOfStack
+ );
+}
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
new file mode 100644
index 0000000..26975c0
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
@@ -0,0 +1,101 @@
+/** @file
+ RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_init.h>
+#include <sbi/sbi_scratch.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/RiscVPlatformDxeIpl.h>
+
+/**
+ RISC-V platform DXE IPL to DXE OpenSBI mdoe switch handler.
+ This function is executed in RISC-V Supervisor mode.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+RiscVDxeIplHandoffOpenSbiHandler (
+ IN UINTN HardId,
+ IN OPENSBI_SWITCH_MODE_CONTEXT *ThisSwitchContext
+ )
+{
+ DEBUG ((DEBUG_INFO, "OpenSBI mode switch DXE IPL Handoff handler entry\n"));
+
+ SwitchStack (
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)ThisSwitchContext->DxeCoreEntryPoint,
+ ThisSwitchContext->HobList.Raw,
+ NULL,
+ ThisSwitchContext->TopOfStack
+ );
+
+ //
+ // Shold never came back.
+ //
+ UNREACHABLE();
+}
+
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+ struct sbi_scratch *ThisScratch;
+ OPENSBI_SWITCH_MODE_CONTEXT OpenSbiSwitchModeContext;
+
+ DEBUG ((DEBUG_INFO, "DXE IPL to DXE Core using OpenSBI\n"));
+ //
+ // Setup next address in OpenSBI scratch
+ //
+ OpenSbiSwitchModeContext.BaseOfStack = BaseOfStack;
+ OpenSbiSwitchModeContext.TopOfStack = TopOfStack;
+ OpenSbiSwitchModeContext.HobList = HobList;
+ OpenSbiSwitchModeContext.DxeCoreEntryPoint = DxeCoreEntryPoint;
+ ThisScratch = sbi_scratch_thishart_ptr ();
+ ThisScratch->next_arg1 = (UINTN)&OpenSbiSwitchModeContext;
+ ThisScratch->next_addr = (UINTN)RiscVDxeIplHandoffOpenSbiHandler;
+ ThisScratch->next_mode = PRV_S;
+
+ DEBUG ((DEBUG_INFO, " Base address of satck: 0x%x\n", BaseOfStack));
+ DEBUG ((DEBUG_INFO, " Top address of satck: 0x%x\n", TopOfStack));
+ DEBUG ((DEBUG_INFO, " HOB list address: 0x%x\n", &HobList));
+ DEBUG ((DEBUG_INFO, " DXE core entry pointer: 0x%x\n", DxeCoreEntryPoint));
+ DEBUG ((DEBUG_INFO, " OpenSBI Switch mode arg1: 0x%x\n", (UINTN)&OpenSbiSwitchModeContext));
+ DEBUG ((DEBUG_INFO, " OpenSBI Switch mode handler address: 0x%x\n", (UINTN)RiscVDxeIplHandoffOpenSbiHandler));
+ DEBUG ((DEBUG_INFO, " OpenSBI Switch mode to privilege 0x%x\n", PRV_S));
+ sbi_init (ThisScratch);
+}
--
2.7.4
next prev parent reply other threads:[~2019-10-28 2:31 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 01/39] RiscVPkg: RISC-V processor package Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 02/39] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
2019-11-21 16:24 ` Leif Lindholm
2019-12-19 4:09 ` [edk2-devel] " Abner Chang
2019-12-19 13:21 ` Leif Lindholm
2019-12-19 14:48 ` Abner Chang
[not found] ` <15E1CD20DD2FE7F1.29030@groups.io>
2019-12-20 3:04 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 04/39] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 05/39] MdePkg/Include: RISC-V definitions Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 06/39] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 07/39] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 08/39] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 09/39] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
2019-11-21 16:36 ` Leif Lindholm
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 10/39] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 11/39] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 12/39] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 13/39] MdeModulePkg/Logo Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 14/39] NetworkPkg Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 15/39] RiscVPkg/Library: RISC-V CPU library Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 16/39] RiscVPkg/Library: Add RISC-V exception library Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 17/39] RiscVPkg/Library: Add RISC-V timer library Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 18/39] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
2019-11-21 16:48 ` [edk2-devel] " Leif Lindholm
2019-12-19 6:00 ` Abner Chang
2019-12-20 15:04 ` Abner Chang
2019-10-28 1:58 ` Abner Chang [this message]
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 20/39] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 21/39] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 22/39] RiscVPlatformPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 23/39] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 24/39] BaseTools: BaseTools changes for RISC-V platform Abner Chang
2019-11-21 16:55 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts Abner Chang
2019-11-19 18:17 ` [edk2-devel] " Mark Salter
2019-11-20 8:23 ` Abner Chang
2019-11-21 7:40 ` Abner Chang
2019-11-21 16:56 ` Leif Lindholm
2019-11-22 3:49 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 26/39] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 27/39] RiscVPkg/RiscVOpensbLlib: Add submodule opensbi Abner Chang
2019-11-21 17:00 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 28/39] RiscVPlatformPkg/FirmwareContextProcessorSpecificLib:Add FirmwareContextProcessorSpecificLib module Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib Abner Chang
2019-11-21 17:02 ` Leif Lindholm
2019-11-22 12:28 ` Abner Chang
2019-11-22 14:08 ` Leif Lindholm
2019-11-22 14:19 ` Abner Chang
2019-11-22 14:55 ` Leif Lindholm
2019-11-22 16:05 ` [edk2-devel] " Abner Chang
2019-11-22 16:32 ` Leif Lindholm
2019-11-23 7:38 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 30/39] RiscVPlatformPkg/OpensbiPlatformLibNull: NULL instance of RiscVOpensbiPlatformLib Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 31/39] RiscVPlatformPkg/PlatformMemoryTestLibNull: NULL instance of PlatformMemoryTestLib Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 32/39] RiscVPlatformPkg/PlatformUpdateProgressLibNull: NULL instance of PlatformUpdateProgressLib Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 33/39] RiscVPlatformPkg/PlatformBootManagerLib: Platform Boot Manager library Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 34/39] RiscVPkg/RiscVPlatformTimerLibNull: NULL instance of RISC-V platform timer library Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 35/39] RiscVPlatformPkg/SecMain: RISC-V SecMain module Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 36/39] RiscVPlatformPkg: Add RiscVPlatformPkg Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md Abner Chang
2019-11-21 17:09 ` Leif Lindholm
2019-11-22 3:57 ` [edk2-devel] " Abner Chang
2019-11-22 9:34 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 38/39] edk2-staging: Revise Maintainers.txt for RISC-V packages Abner Chang
2019-10-29 1:05 ` [edk2-devel] " Laszlo Ersek
2019-10-29 1:31 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md Abner Chang
2019-10-29 1:07 ` [edk2-devel] " Laszlo Ersek
2019-10-29 1:35 ` Abner Chang
2019-10-29 2:01 ` Leif Lindholm
2019-10-31 8:20 ` Laszlo Ersek
2019-11-21 17:15 ` Leif Lindholm
2019-11-22 2:05 ` Abner Chang
2019-11-22 9:42 ` Leif Lindholm
2019-11-22 11:46 ` Abner Chang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1572227957-13169-20-git-send-email-abner.chang@hpe.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox