From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web10.564.1572229912949538959 for ; Sun, 27 Oct 2019 19:31:53 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=02044412f4=abner.chang@hpe.com) Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S2VivL015280; Mon, 28 Oct 2019 02:31:52 GMT Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2vvynnms8h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 02:31:52 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 90E1E6C; Mon, 28 Oct 2019 02:31:51 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id C63C649; Mon, 28 Oct 2019 02:31:49 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Dandan Bi , Liming Gao , Leif Lindholm , Gilbert Chen Subject: [edk2-staging/RISC-V-V2 PATCH v3 20/39] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Date: Mon, 28 Oct 2019 09:58:58 +0800 Message-Id: <1572227957-13169-21-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-27_09:2019-10-25,2019-10-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 spamscore=0 mlxscore=0 phishscore=0 bulkscore=0 suspectscore=1 priorityscore=1501 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1910280025 Implementation of RISC-V platform level DxeIPL. Signed-off-by: Abner Chang Cc: Dandan Bi Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +++- RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 ++++++++++++ MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 76 ++++++++++++++++++++++ 3 files changed, 129 insertions(+), 1 deletion(-) create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf index 98bc17f..5532323 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -7,6 +7,7 @@ # # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +26,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 +# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64 # [Sources] @@ -49,6 +50,9 @@ [Sources.ARM, Sources.AARCH64] Arm/DxeLoadFunc.c +[Sources.RISCV64] + RiscV64/DxeLoadFunc.c + [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec @@ -56,6 +60,9 @@ [Packages.ARM, Packages.AARCH64] ArmPkg/ArmPkg.dec +[Packages.RISCV64] + RiscVPkg/RiscVPkg.dec + [LibraryClasses] PcdLib MemoryAllocationLib @@ -75,6 +82,10 @@ [LibraryClasses.ARM, LibraryClasses.AARCH64] ArmMmuLib +[LibraryClasses.RISCV64] + RiscVPlatformDxeIplLib + RiscVOpensbiLib + [Ppis] gEfiDxeIplPpiGuid ## PRODUCES gEfiPeiDecompressPpiGuid ## PRODUCES diff --git a/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h new file mode 100644 index 0000000..30058f2 --- /dev/null +++ b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h @@ -0,0 +1,41 @@ +/** @file + Header file of RISC-V platform DXE IPL + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP.All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef RISC_V_PLATFORM_DXEIPL_H_ +#define RISC_V_PLATFORM_DXEIPL_H_ + +typedef struct { + VOID *TopOfStack; + VOID *BaseOfStack; + EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint; + EFI_PEI_HOB_POINTERS HobList; +} OPENSBI_SWITCH_MODE_CONTEXT; + +/** + RISC-V platform DXE IPL to DXE core handoff process. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param BaseOfStack Base address of stack + @param TopOfStack Top address of stack + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ + +VOID +RiscVPlatformHandOffToDxeCore ( + IN VOID *BaseOfStack, + IN VOID *TopOfStack, + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ); +#endif + diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c new file mode 100644 index 0000000..48efdd8 --- /dev/null +++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c @@ -0,0 +1,76 @@ +/** @file + RISC-V specific functionality for DxeLoad. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DxeIpl.h" +#include + +typedef +VOID* +(EFIAPI *DXEENTRYPOINT) ( + IN VOID *HobStart + ); + +/** + Transfers control to DxeCore. + + This function performs a CPU architecture specific operations to execute + the entry point of DxeCore with the parameters of HobList. + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase. + + @param DxeCoreEntryPoint The entry point of DxeCore. + @param HobList The start of HobList passed to DxeCore. + +**/ +VOID +HandOffToDxeCore ( + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint, + IN EFI_PEI_HOB_POINTERS HobList + ) +{ + VOID *BaseOfStack; + VOID *TopOfStack; + EFI_STATUS Status; + // + // + // Allocate 128KB for the Stack + // + BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE)); + if (BaseOfStack == NULL) { + DEBUG((DEBUG_ERROR, "%a: Can't allocate memory for stack.", __FUNCTION__)); + ASSERT(FALSE); + } + + // + // Compute the top of the stack we were allocated. Pre-allocate a UINTN + // for safety. + // + TopOfStack = (VOID *)((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT); + TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT); + + // + // End of PEI phase signal + // + Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "%a: Fail to signal End of PEI event.", __FUNCTION__)); + ASSERT(FALSE); + } + // + // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore. + // + UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE); + + DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack pointer at %x\n", BaseOfStack, TopOfStack)); + + // + // Transfer the control to the entry point of DxeCore. + // + RiscVPlatformHandOffToDxeCore (BaseOfStack, TopOfStack, DxeCoreEntryPoint, HobList); +} + -- 2.7.4