From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web10.554.1572229908017017268 for ; Sun, 27 Oct 2019 19:31:48 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=02044412f4=abner.chang@hpe.com) Received: from pps.filterd (m0148664.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S2VhtW008598; Mon, 28 Oct 2019 02:31:43 GMT Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 2vvd90rwv2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 02:31:43 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 06F4C56; Mon, 28 Oct 2019 02:31:14 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id A443E46; Mon, 28 Oct 2019 02:31:12 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Leif Lindholm , Gilbert Chen Subject: [edk2-staging/RISC-V-V2 PATCH v3 02/39] RiscVPkg/Include: Add header files of RISC-V CPU package Date: Mon, 28 Oct 2019 09:58:40 +0800 Message-Id: <1572227957-13169-3-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-27_09:2019-10-25,2019-10-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 spamscore=0 suspectscore=1 priorityscore=1501 mlxscore=0 bulkscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1910280025 RISC-V package library definitions. IndustryStandard/RiscV.h -Add RiscV.h which conform with RISC-V Privilege Spec v1.10. RiscVImpl.h -Definition of EDK2 RISC-V implementation. Signed-off-by: Abner Chang Cc: Leif Lindholm Cc: Gilbert Chen --- RiscVPkg/Include/IndustryStandard/RiscV.h | 118 ++++++++++++++++++++++++++++++ RiscVPkg/Include/RiscVImpl.h | 72 ++++++++++++++++++ 2 files changed, 190 insertions(+) create mode 100644 RiscVPkg/Include/IndustryStandard/RiscV.h create mode 100644 RiscVPkg/Include/RiscVImpl.h diff --git a/RiscVPkg/Include/IndustryStandard/RiscV.h b/RiscVPkg/Include/IndustryStandard/RiscV.h new file mode 100644 index 0000000..56aed81 --- /dev/null +++ b/RiscVPkg/Include/IndustryStandard/RiscV.h @@ -0,0 +1,118 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_INDUSTRY_STANDARD_H_ +#define RISCV_INDUSTRY_STANDARD_H_ + +#if defined (MDE_CPU_RISCV64) +#define RISC_V_XLEN_BITS 64 +#else +#endif + +#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0) +#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1) +#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2) +#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3) +#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4) +#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5) +#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6) +#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7) +#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8) +#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9) +#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10) +#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11) +#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12) +#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13) +#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14) +#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15) +#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16) +#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17) +#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18) +#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19) +#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20) +#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21) +#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22) +#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23) +#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24) +#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25) + +// +// RISC-V CSR definitions. +// +// +// Machine information +// +#define RISCV_CSR_MACHINE_MVENDORID 0xF11 +#define RISCV_CSR_MACHINE_MARCHID 0xF12 +#define RISCV_CSR_MACHINE_MIMPID 0xF13 +#define RISCV_CSR_MACHINE_HARRID 0xF14 +// +// Machine Trap Setup. +// +#define RISCV_CSR_MACHINE_MSTATUS 0x300 +#define RISCV_CSR_MACHINE_MISA 0x301 +#define RISCV_CSR_MACHINE_MEDELEG 0x302 +#define RISCV_CSR_MACHINE_MIDELEG 0x303 +#define RISCV_CSR_MACHINE_MIE 0x304 +#define RISCV_CSR_MACHINE_MTVEC 0x305 + +#define RISCV_TIMER_COMPARE_BITS 32 +// +// Machine Timer and Counter. +// +//#define RISCV_CSR_MACHINE_MTIME 0x701 +//#define RISCV_CSR_MACHINE_MTIMEH 0x741 +// +// Machine Trap Handling. +// +#define RISCV_CSR_MACHINE_MSCRATCH 0x340 +#define RISCV_CSR_MACHINE_MEPC 0x341 +#define RISCV_CSR_MACHINE_MCAUSE 0x342 + #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f + #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1) +#define RISCV_CSR_MACHINE_MBADADDR 0x343 +#define RISCV_CSR_MACHINE_MIP 0x344 + +// +// Machine Protection and Translation. +// +#define RISCV_CSR_MACHINE_MBASE 0x380 +#define RISCV_CSR_MACHINE_MBOUND 0x381 +#define RISCV_CSR_MACHINE_MIBASE 0x382 +#define RISCV_CSR_MACHINE_MIBOUND 0x383 +#define RISCV_CSR_MACHINE_MDBASE 0x384 +#define RISCV_CSR_MACHINE_MDBOUND 0x385 + +// +// Supervisor mode CSR. +// +#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140 +#define RISCV_CSR_SUPERVISOR_SEPC 0x141 +#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142 + #define SCAUSE_USER_SOFTWARE_INT 0 + #define SCAUSE_SUPERVISOR_SOFTWARE_INT 1 + #define SCAUSE_USER_TIMER_INT 4 + #define SCAUSE_SUPERVISOR_TIMER_INT 5 + #define SCAUSE_USER_EXTERNAL_INT 8 + #define SCAUSE_SUPERVISOR_EXTERNAL_INT 9 +#define RISCV_CSR_SUPERVISOR_STVAL 0x143 +#define RISCV_CSR_SUPERVISOR_SIP 0x144 + +// +// Machine Read-Write Shadow of Hypervisor Read-Only Registers +// +#define RISCV_CSR_HTIMEW 0xB01 +#define RISCV_CSR_HTIMEHW 0xB81 +// +// Machine Host-Target Interface (Non-Standard Berkeley Extension) +// +#define RISCV_CSR_MTOHOST 0x780 +#define RISCV_CSR_MFROMHOST 0x781 + +#endif diff --git a/RiscVPkg/Include/RiscVImpl.h b/RiscVPkg/Include/RiscVImpl.h new file mode 100644 index 0000000..1629266 --- /dev/null +++ b/RiscVPkg/Include/RiscVImpl.h @@ -0,0 +1,72 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_H_ +#define RISCV_H_ + +#include + +// +// Structure for 128-bit value +// +typedef struct { + UINT64 Value64_L; + UINT64 Value64_H; +} RISCV_UINT128; + +#define RISCV_MACHINE_CONTEXT_SIZE 0x1000 +typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _EXCEPTION_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander; + EFI_PHYSICAL_ADDRESS InstAccessFaultHander; + EFI_PHYSICAL_ADDRESS IllegalInstHander; + EFI_PHYSICAL_ADDRESS BreakpointHander; + EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS LoadAccessFaultHander; + EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander; + EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander; + EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander; + EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander; +} EXCEPTION_HANDLER_CONTEXT; + +/// +/// Exception handlers in context. +/// +typedef struct _INTERRUPT_HANDLER_CONTEXT { + EFI_PHYSICAL_ADDRESS SoftwareIntHandler; + EFI_PHYSICAL_ADDRESS TimerIntHandler; +} INTERRUPT_HANDLER_CONTEXT; + +/// +/// Interrupt handlers in context. +/// +typedef struct _TRAP_HANDLER_CONTEXT { + EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext; + INTERRUPT_HANDLER_CONTEXT IntHandlerContext; +} TRAP_HANDLER_CONTEXT; + +/// +/// Machine mode context used for saveing hart-local context. +/// +typedef struct _RISCV_MACHINE_MODE_CONTEXT { + EFI_PHYSICAL_ADDRESS PeiService; /// PEI service. + EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap handler. + EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap handler. + EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap handler. + EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handler. + TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine mode. +} RISCV_MACHINE_MODE_CONTEXT; + +#endif -- 2.7.4