From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.585.1572229941873815874 for ; Sun, 27 Oct 2019 19:32:21 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=02044412f4=abner.chang@hpe.com) Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S2Vivx024730; Mon, 28 Oct 2019 02:32:21 GMT Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2vw02avnc6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 02:32:21 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id CA24554; Mon, 28 Oct 2019 02:32:20 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 763E44A; Mon, 28 Oct 2019 02:32:19 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Leif Lindholm , Gilbert Chen Subject: [edk2-staging/RISC-V-V2 PATCH v3 36/39] RiscVPlatformPkg: Add RiscVPlatformPkg Date: Mon, 28 Oct 2019 09:59:14 +0800 Message-Id: <1572227957-13169-37-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-27_09:2019-10-25,2019-10-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 mlxscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1910280025 Add RISC-V platform package. Signed-off-by: Abner Chang Cc: Leif Lindholm Cc: Gilbert Chen --- RiscVPlatformPkg/RiscVPlatformPkg.dec | 72 +++++++++++++++++++++++++++ RiscVPlatformPkg/RiscVPlatformPkg.dsc | 73 ++++++++++++++++++++++++++++ RiscVPlatformPkg/Readme.md | 78 ++++++++++++++++++++++++++++++ RiscVPlatformPkg/RiscVPlatformPkg.uni | 15 ++++++ RiscVPlatformPkg/RiscVPlatformPkgExtra.uni | 12 +++++ 5 files changed, 250 insertions(+) create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.dec create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.dsc create mode 100644 RiscVPlatformPkg/Readme.md create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.uni create mode 100644 RiscVPlatformPkg/RiscVPlatformPkgExtra.uni diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.dec b/RiscVPlatformPkg/RiscVPlatformPkg.dec new file mode 100644 index 0000000..da7f846 --- /dev/null +++ b/RiscVPlatformPkg/RiscVPlatformPkg.dec @@ -0,0 +1,72 @@ +## @file RiscVPlatformPkg.dec +# This Package provides UEFI RISC-V platform modules and libraries. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x0001001b + PACKAGE_NAME = RiscVPlatformPkg + PACKAGE_UNI_FILE = RiscVPlatformPkg.uni + PACKAGE_GUID = 6A67AF99-4592-40F8-B6BE-62BCA10DA1EC + PACKAGE_VERSION = 1.0 + +[Includes] + Include + +[LibraryClasses] + +[LibraryClasses.RISCV32, LibraryClasses.RISCV64] + +[Guids] + gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}} + +[PcdsFixedAtBuild] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|0x0|UINT32|0x00001000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize|0x0|UINT32|0x00001001 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|0x0|UINT32|0x00001002 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005 + +# +# Definition of EFI Variable region +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001010 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001012 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001013 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001014 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001015 +# +# Firmware region which is protected by PMP. +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022 +# +# Definition of RISC-V Hart +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024 +# +# Definitions for OpenSbi +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001025 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize|0|UINT32|0x00001026 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize|0|UINT32|0x00001027 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x00001028 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001029 + +[PcdsPatchableInModule] + +[PcdsFeatureFlag] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001006 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + +[UserExtensions.TianoCore."ExtraFiles"] + RiscVPlatformPkgExtra.uni diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.dsc b/RiscVPlatformPkg/RiscVPlatformPkg.dsc new file mode 100644 index 0000000..7f4bdda --- /dev/null +++ b/RiscVPlatformPkg/RiscVPlatformPkg.dsc @@ -0,0 +1,73 @@ +#/** @file +# RISC-V platform package. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +################################################################################ +# +# Defines Section +# +################################################################################ +[Defines] + PLATFORM_NAME = RiscVPlatform + PLATFORM_GUID = 840A9576-5869-491E-9210-89769DED4650 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001c + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = RISCV64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG +!ifdef $(SOURCE_DEBUG_ENABLE) + GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable +!endif + +################################################################################ +# +# SKU Identification section - list of all SKU IDs supported by this Platform. +# +################################################################################ +[SkuIds] + 0|DEFAULT + +[LibraryClasses.common] + RealTimeClockLib|RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf + RiscVOpensbiPlatformLib|RiscVPlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf + RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf + RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + +[LibraryClasses.common.PEIM] + FirmwareContextProcessorSpecificLib|RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[LibraryClasses.common.SEC] + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf + +[LibraryClasses.common.DXE_DRIVER] + PlatformBootManagerLib|RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + +[Components.common.SEC] + RiscVPlatformPkg/Universal/Sec/SecMain.inf + diff --git a/RiscVPlatformPkg/Readme.md b/RiscVPlatformPkg/Readme.md new file mode 100644 index 0000000..ebf7bf5 --- /dev/null +++ b/RiscVPlatformPkg/Readme.md @@ -0,0 +1,78 @@ +# Introduction + +## EDK2 RISC-V Platform Package +RISC-V platform package provides the generic and common modules for RISC-V +platforms. RISC-V platform package could include RiscPlatformPkg.dec to +use the common drivers, libraries, definitions, PCDs and etc. for the +platform development. + +### Download the sources ### +``` +git clone https://github.com/tianocore/edk2-staging.git +# Checkout RISC-V-V2 branch +git clone https://github.com/tianocore/edk2-platforms.git +# Checkout devel-riscv-v2-PATCHv5 branch +git clone https://github.com/tianocore/edk2-non-osi.git +``` +### EDK2 project +Currently, the EDK2 RISC-V platform can only build with edk2 project in +**edk2-staging/RISC-V-V2** branch. The build architecture whcih is supported +and verified so far is "RISCV64". +The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu-toolchain @64879b24, +toolchain tag is "GCC5" declared in tools_def.txt + +## RISC-V Platform PCD settings +### EDK2 Firmware Volume Settings +EDK2 Firmware volume related PCDs which declared in platform FDF file. + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdRiscVSecFvBase| The base address of SEC Firmware Volume| +|PcdRiscVSecFvSize| The size of SEC Firmware Volume| +|PcdRiscVPeiFvBase| The base address of PEI Firmware Volume| +|PcdRiscVPeiFvSize| The size of SEC Firmware Volume| +|PcdRiscVDxeFvBase| The base address of DXE Firmware Volume| +|PcdRiscVDxeFvSize| The size of SEC Firmware Volume| + +### EDK2 EFI Variable Region Settings +The PCD settings regard to EFI Variable + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdVariableFdBaseAddress| The EFI variable firmware device base address| +|PcdVariableFdSize| The EFI variable firmware device size| +|PcdVariableFdBlockSize| The block size of EFI variable firmware device| +|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within firmware device| +|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable fault tolerance worksapce (FTW) within firmware device| +|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare FTW within firmware device| + +### RISC-V Physical Memory Protection (PMP) Region Settings +Below PCDs could be set in platform FDF file. + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdFwStartAddress| The starting address of firmware region to protected by PMP| +|PcdFwEndAddress| The ending address of firmware region to protected by PMP| + +### RISC-V Processor HART Settings + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific| +|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS| + +### RISC-V OpenSBI Settings + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V HARTs| +|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-V HARTs| +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for booting system use OpenSBI| +|PcdTemporaryRamBase| The base address of temporary memory for PEI phase| +|PcdTemporaryRamSize| The temporary memory size for PEI phase| + +## Supported Operating Systems +Only support to boot to EFI Shell so far. + +## Known Issues and Limitations +Only RISC-V RV64 is verified. diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.uni b/RiscVPlatformPkg/RiscVPlatformPkg.uni new file mode 100644 index 0000000..deb91fa --- /dev/null +++ b/RiscVPlatformPkg/RiscVPlatformPkg.uni @@ -0,0 +1,15 @@ +// /** @file +// RISC-V Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V platform modules and libraries" + +#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V platform modules and libraries." + + diff --git a/RiscVPlatformPkg/RiscVPlatformPkgExtra.uni b/RiscVPlatformPkg/RiscVPlatformPkgExtra.uni new file mode 100644 index 0000000..493f5f4 --- /dev/null +++ b/RiscVPlatformPkg/RiscVPlatformPkgExtra.uni @@ -0,0 +1,12 @@ +// /** @file +// RISC-V Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_PACKAGE_NAME +#language en-US +"RISC-V platform package" -- 2.7.4