From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web09.612.1572229910631195298 for ; Sun, 27 Oct 2019 19:31:50 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=02044412f4=abner.chang@hpe.com) Received: from pps.filterd (m0134423.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S2Vk54026281; Mon, 28 Oct 2019 02:31:46 GMT Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2vvbnuhb0w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 02:31:46 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id BF34754; Mon, 28 Oct 2019 02:31:15 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 6BAF745; Mon, 28 Oct 2019 02:31:14 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Leif Lindholm , Gilbert Chen Subject: [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Date: Mon, 28 Oct 2019 09:58:41 +0800 Message-Id: <1572227957-13169-4-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-27_09:2019-10-25,2019-10-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 mlxscore=0 phishscore=0 bulkscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1910280025 Add EDK2 RISC-V OpenSBI header files. Signed-off-by: Abner Chang Cc: Leif Lindholm Cc: Gilbert Chen --- RiscVPkg/Include/sbi/SbiFirmwareContext.h | 33 ++++++++++++++++++++ RiscVPkg/Include/sbi/sbi.h | 52 +++++++++++++++++++++++++++++++ RiscVPkg/Include/sbi/sbi_bits.h | 17 ++++++++++ RiscVPkg/Include/sbi/sbi_types.h | 45 ++++++++++++++++++++++++++ 4 files changed, 147 insertions(+) create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h create mode 100644 RiscVPkg/Include/sbi/sbi.h create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h create mode 100644 RiscVPkg/Include/sbi/sbi_types.h diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h b/RiscVPkg/Include/sbi/SbiFirmwareContext.h new file mode 100644 index 0000000..c3d3489 --- /dev/null +++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h @@ -0,0 +1,33 @@ +/** @file + RISC-V OpesbSBI Platform Firmware context definition + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef SBI_FIRMWARE_CONTEXT_H_ +#define SBI_FIRMWARE_CONTEXT_H_ + +#include + +#define RISC_V_MAX_HART_SUPPORTED 16 + +// +// keep the structure member in 64-bit alignment. +// +typedef struct { + UINT64 IsaExtensionSupported; // The ISA extension this core supported. + RISCV_UINT128 MachineVendorId; // Machine vendor ID + RISCV_UINT128 MachineArchId; // Machine Architecture ID + RISCV_UINT128 MachineImplId; // Machine Implementation ID +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC; + +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7) + +typedef struct { + VOID *PeiServiceTable; // PEI Service table + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED]; +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT; +#endif + diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h new file mode 100644 index 0000000..04e7f18 --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi.h @@ -0,0 +1,52 @@ +/** @file + SBI inline function calls. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef EDK2_SBI_H_ +#define EDK2_SBI_H_ + +#include // Reference to header file wrapper +#include // Reference to header file in opensbi + +#define SBI_SET_TIMER 0 +#define SBI_CONSOLE_PUTCHAR 1 +#define SBI_CONSOLE_GETCHAR 2 +#define SBI_CLEAR_IPI 3 +#define SBI_SEND_IPI 4 +#define SBI_REMOTE_FENCE_I 5 +#define SBI_REMOTE_SFENCE_VMA 6 +#define SBI_REMOTE_SFENCE_VMA_ASID 7 +#define SBI_SHUTDOWN 8 + +#define SBI_CALL(which, arg0, arg1, arg2) ({ \ + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \ + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \ + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \ + register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \ + asm volatile ("ecall" \ + : "+r" (a0) \ + : "r" (a1), "r" (a2), "r" (a7) \ + : "memory"); \ + a0; \ +}) + +#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0) +#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0) +#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0) + +#define sbi_console_putchar(ch) SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch) +#define sbi_console_getchar() SBI_CALL_0(SBI_CONSOLE_GETCHAR) +#define sbi_set_timer(stime_value) SBI_CALL_1(SBI_SET_TIMER, stime_value) +#define sbi_shutdown() SBI_CALL_0(SBI_SHUTDOWN) +#define sbi_clear_ipi() SBI_CALL_0(SBI_CLEAR_IPI) +#define sbi_send_ipi(hart_mask) SBI_CALL_1(SBI_SEND_IPI, hart_mask) +#define sbi_remote_fence_i(hart_mask) SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask) +#define sbi_remote_sfence_vma(hart_mask, start, size) SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask) +#define sbi_remote_sfence_vma_asid(hart_mask, start, size, asid) SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask) + +#endif diff --git a/RiscVPkg/Include/sbi/sbi_bits.h b/RiscVPkg/Include/sbi/sbi_bits.h new file mode 100644 index 0000000..c935547 --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi_bits.h @@ -0,0 +1,17 @@ +/** @file + RISC-V OpesbSBI header file reference. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef EDK2_SBI_BITS_H_ +#define EDK2_SBI_BITS_H_ + +#undef MAX +#undef MIN + +#include "include/sbi/sbi_bits.h" // Reference to header file in opensbi + +#endif diff --git a/RiscVPkg/Include/sbi/sbi_types.h b/RiscVPkg/Include/sbi/sbi_types.h new file mode 100644 index 0000000..95ee213 --- /dev/null +++ b/RiscVPkg/Include/sbi/sbi_types.h @@ -0,0 +1,45 @@ +/** @file + RISC-V OpesbSBI header file reference. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef EDK2_SBI_TYPES_H_ +#define EDK2_SBI_TYPES_H_ + +typedef INT8 s8; +typedef UINT8 u8; +typedef UINT8 uint8_t; + +typedef INT16 s16; +typedef UINT16 u16; +typedef INT16 int16_t; +typedef UINT16 uint16_t; + +typedef INT32 s32; +typedef UINT32 u32; +typedef INT32 int32_t; +typedef UINT32 uint32_t; + +typedef INT64 s64; +typedef UINT64 u64; +typedef INT64 int64_t; +typedef UINT64 uint64_t; + +#define PRILX "016lx" + +typedef INT32 bool; +typedef unsigned long ulong; +typedef UINT64 uintptr_t; +typedef UINT64 size_t; +typedef INT64 ssize_t; +typedef UINT64 virtual_addr_t; +typedef UINT64 virtual_size_t; +typedef UINT64 physical_addr_t; +typedef UINT64 physical_size_t; + +#define __packed __attribute__((packed)) +#define __noreturn __attribute__((noreturn)) +#endif -- 2.7.4