From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.567.1572229903834961280 for ; Sun, 27 Oct 2019 19:31:44 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=02044412f4=abner.chang@hpe.com) Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S2VhY5006421; Mon, 28 Oct 2019 02:31:43 GMT Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0a-002e3701.pphosted.com with ESMTP id 2vvywmvp6x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 02:31:43 +0000 Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 15FC46B; Mon, 28 Oct 2019 02:31:17 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 336674C; Mon, 28 Oct 2019 02:31:15 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Michael D Kinney , Liming Gao , Leif Lindholm , Gilbert Chen Subject: [edk2-staging/RISC-V-V2 PATCH v3 04/39] MdePkg: RISC-V RV64 binding in MdePkg Date: Mon, 28 Oct 2019 09:58:42 +0800 Message-Id: <1572227957-13169-5-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> References: <1572227957-13169-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-27_09:2019-10-25,2019-10-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 impostorscore=0 spamscore=0 suspectscore=1 clxscore=1015 adultscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1910280025 Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h Signed-off-by: Abner Chang Cc: Michael D Kinney Cc: Liming Gao Cc: Leif Lindholm Cc: Gilbert Chen --- MdePkg/MdePkg.dec | 5 +- MdePkg/Include/RiscV64/ProcessorBind.h | 173 +++++++++++++++++++++++++++++++++ 2 files changed, 177 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 3fd7d16..1aaa97d 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -6,7 +6,7 @@ # # Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+# (C) Copyright 2016 - 2019 Hewlett Packard Enterprise Development LP
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -39,6 +39,9 @@ [Includes.AARCH64] Include/AArch64 +[Includes.RISCV64] + Include/RiscV64 + [LibraryClasses] ## @libraryclass Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec # and the standard requests defined in Usb 1.1 spec. diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV64/ProcessorBind.h new file mode 100644 index 0000000..b887250 --- /dev/null +++ b/MdePkg/Include/RiscV64/ProcessorBind.h @@ -0,0 +1,173 @@ +/** @file + Processor or Compiler specific defines and types for RISC-V + + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PROCESSOR_BIND_H__ +#define PROCESSOR_BIND_H__ + +/// +/// Define the processor type so other code can make processor based choices +/// +#define MDE_CPU_RISCV64 + +// +// Make sure we are using the correct packing rules per EFI specification +// +#if !defined(__GNUC__) +#pragma pack() +#endif + +/// +/// 8-byte unsigned value +/// +typedef unsigned long long UINT64 __attribute__ ((aligned (8))); +/// +/// 8-byte signed value +/// +typedef long long INT64 __attribute__ ((aligned (8))); +/// +/// 4-byte unsigned value +/// +typedef unsigned int UINT32 __attribute__ ((aligned (4))); +/// +/// 4-byte signed value +/// +typedef int INT32 __attribute__ ((aligned (4))); +/// +/// 2-byte unsigned value +/// +typedef unsigned short UINT16 __attribute__ ((aligned (2))); +/// +/// 2-byte Character. Unless otherwise specified all strings are stored in the +/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards. +/// +typedef unsigned short CHAR16 __attribute__ ((aligned (2))); +/// +/// 2-byte signed value +/// +typedef short INT16 __attribute__ ((aligned (2))); +/// +/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other +/// values are undefined. +/// +typedef unsigned char BOOLEAN; +/// +/// 1-byte unsigned value +/// +typedef unsigned char UINT8; +/// +/// 1-byte Character +/// +typedef char CHAR8; +/// +/// 1-byte signed value +/// +typedef signed char INT8; +/// +/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef UINT64 UINTN __attribute__ ((aligned (8))); +/// +/// Signed value of native width. (4 bytes on supported 32-bit processor instructions, +/// 8 bytes on supported 64-bit processor instructions) +/// +typedef INT64 INTN __attribute__ ((aligned (8))); + +// +// Processor specific defines +// + +/// +/// A value of native width with the highest bit set. +/// +#define MAX_BIT 0x8000000000000000ULL +/// +/// A value of native width with the two highest bits set. +/// +#define MAX_2_BITS 0xC000000000000000ULL + +/// +/// Maximum legal RV64 address +/// +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL + +/// +/// Maximum usable address at boot time (48 bits using 4 KB pages in Supervisor mode) +/// +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL + +/// +/// Maximum legal RISC-V INTN and UINTN values. +/// +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL) +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL) + +/// +/// The stack alignment required for RISC-V +/// +#define CPU_STACK_ALIGNMENT 16 + +/// +/// Page allocation granularity for RISC-V +/// +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000) +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000) + +// +// Modifier to ensure that all protocol member functions and EFI intrinsics +// use the correct C calling convention. All protocol member functions and +// EFI intrinsics are required to modify their member functions with EFIAPI. +// +#ifdef EFIAPI + /// + /// If EFIAPI is already defined, then we use that definition. + /// +#elif defined(__GNUC__) + /// + /// Define the standard calling convention regardless of optimization level + /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI + /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64) + /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for + /// x64. Warning the assembly code in the MDE x64 does not follow the correct + /// ABI for the standard x64 (x86-64) GCC. + /// + #define EFIAPI +#else + /// + /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI + /// is the standard. + /// + #define EFIAPI +#endif + +#if defined(__GNUC__) + /// + /// For GNU assembly code, .global or .globl can declare global symbols. + /// Define this macro to unify the usage. + /// + #define ASM_GLOBAL .globl +#endif + +/** + Return the pointer to the first instruction of a function given a function pointer. + On x64 CPU architectures, these two pointer values are the same, + so the implementation of this macro is very simple. + + @param FunctionPointer A pointer to a function. + + @return The pointer to the first instruction of a function given a function pointer. + +**/ +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer) + +#ifndef __USER_LABEL_PREFIX__ +#define __USER_LABEL_PREFIX__ +#endif + +#endif -- 2.7.4