* [platform/devel-riscv-v2 PATCHv5 01/18] Silicon/SiFive: Initial version of SiFive silicon package.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 02/18] SiFive/E51: Initial version of SiFive E51 core library Abner Chang
` (17 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
This is the initial version of SiFive silicon package. Provides PCD
tokens.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Silicon/SiFive/SiFive.dec | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Silicon/SiFive/SiFive.dec
diff --git a/Silicon/SiFive/SiFive.dec b/Silicon/SiFive/SiFive.dec
new file mode 100644
index 0000000..85ddfe0
--- /dev/null
+++ b/Silicon/SiFive/SiFive.dec
@@ -0,0 +1,39 @@
+## @file
+# SiFive silicon package definitions
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = SiFiveSiliconPkg
+ PACKAGE_GUID = 576912B2-7077-4B78-A934-4C133FEB20BB
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+ Include # Root include for the package
+
+[LibraryClasses]
+
+[Guids]
+ gEfiSiFiveSiliconTokenSpaceGuid = {0x5F3E9E15, 0x8FFC, 0x4F53, { 0x8E, 0x64, 0x92, 0x0B, 0xA5, 0x39, 0x81, 0xB0 }}
+
+[Protocols]
+
+[PcdsFixedAtBuild]
+ # E51 Core GUID
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveE51CoreGuid |{0xD4, 0x69, 0x54, 0x87, 0x96, 0x96, 0x48, 0x7F, 0x9F, 0x57, 0xB6, 0xF1, 0xDE, 0x7D, 0x97, 0x42}|VOID*|0x00001000
+ # U54 Core GUID
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54CoreGuid |{0x64, 0x70, 0xF6, 0x90, 0x11, 0x59, 0x47, 0xF1, 0xB8, 0xD5, 0xCF, 0x89, 0x10, 0xC5, 0x30, 0x20}|VOID*|0x00001001
+ # U54 MC Coreplex GUID
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54MCCoreplexGuid |{0x67, 0xBF, 0x15, 0xD9, 0x7E, 0x4F, 0x48, 0x27, 0x87, 0x19, 0x79, 0x0B, 0xA6, 0x22, 0x7C, 0xBE}|VOID*|0x00001002
+ # U5 MC Coreplex GUID
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU5MCCoreplexGuid |{0x06, 0x38, 0x9F, 0x33, 0xF9, 0xDB, 0x43, 0x13, 0x9A, 0x9B, 0x1C, 0x68, 0xD6, 0x04, 0xEA, 0xFF}|VOID*|0x00001003
+
+[PcdsDynamic, PcdsDynamicEx]
+
+[PcdsFeatureFlag]
+
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 02/18] SiFive/E51: Initial version of SiFive E51 core library.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 01/18] Silicon/SiFive: Initial version of SiFive silicon package Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 03/18] SiFive/U54: Initial version of SiFive U54 " Abner Chang
` (16 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
SiFive E51 core library for building core information hob data.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 47 ++++
Silicon/SiFive/Include/Library/SiFiveE51.h | 60 +++++
.../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 242 +++++++++++++++++++++
3 files changed, 349 insertions(+)
create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h
create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
new file mode 100644
index 0000000..a065373
--- /dev/null
+++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -0,0 +1,47 @@
+## @file
+# Library instance to create core information HOB
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = SiliconSiFiveE51CoreInfoLib
+ FILE_GUID = 80A59B85-1245-4309-AC58-2CFA4199B46C
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconSiFiveE51CoreInfoLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ CoreInfoHob.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+ RiscVPkg/RiscVPkg.dec
+ Silicon/SiFive/SiFive.dec
+
+[LibraryClasses]
+ BaseLib
+ FirmwareContextProcessorSpecificLib
+ MemoryAllocationLib
+ PcdLib
+ PrintLib
+
+[FixedPcd]
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveE51CoreGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
+
diff --git a/Silicon/SiFive/Include/Library/SiFiveE51.h b/Silicon/SiFive/Include/Library/SiFiveE51.h
new file mode 100644
index 0000000..6b58766
--- /dev/null
+++ b/Silicon/SiFive/Include/Library/SiFiveE51.h
@@ -0,0 +1,60 @@
+/** @file
+ SiFive E51 Core library definitions.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SIFIVE_E51_CORE_H_
+#define SIFIVE_E51_CORE_H_
+
+#include <PiPei.h>
+
+#include <SmbiosProcessorSpecificData.h>
+#include <ProcessorSpecificHobData.h>
+
+/**
+ Function to build core specific information HOB.
+
+ @param ParentProcessorGuid Parent processor od this core. ParentProcessorGuid
+ could be the same as CoreGuid if one processor has
+ only one core.
+ @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param HartId Hart ID of this core.
+ @param IsBootHart TRUE means this is the boot HART.
+ @param GuidHobData Pointer to receive RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51CoreProcessorSpecificDataHob (
+ IN EFI_GUID *ParentProcessorGuid,
+ IN UINTN ParentProcessorUid,
+ IN UINTN HartId,
+ IN BOOLEAN IsBootHart,
+ OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData
+ );
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51ProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
+ );
+
+#endif
diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 0000000..68eabc3
--- /dev/null
+++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,242 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ResourcePublicationLib.h>
+
+#include <SmbiosProcessorSpecificData.h>
+
+#include <RiscVImpl.h>
+#include <ProcessorSpecificHobData.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi.h>
+#include <sbi/SbiFirmwareContext.h>
+#include <Library/FirmwareContextProcessorSpecificLib.h>
+
+/**
+ Function to build core specific information HOB. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type44.
+
+ @param ParentProcessorGuid Parent processor od this core. ParentProcessorGuid
+ could be the same as CoreGuid if one processor has
+ only one core.
+ @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param HartId Hart ID of this core.
+ @param IsBootHart TRUE means this is the boot HART.
+ @param GuidHobData Pointer to receive EFI_HOB_GUID_TYPE.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51CoreProcessorSpecificDataHob (
+ IN EFI_GUID *ParentProcessorGuid,
+ IN UINTN ParentProcessorUid,
+ IN UINTN HartId,
+ IN BOOLEAN IsBootHart,
+ OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobData
+ )
+{
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob;
+ EFI_GUID *ProcessorSpecDataHobGuid;
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA ProcessorSpecDataHob;
+ struct sbi_scratch *ThisHartSbiScratch;
+ struct sbi_platform *ThisHartSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
+
+ if (GuidHobData == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ThisHartSbiScratch = sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(), (UINT32)HartId);
+ DEBUG ((DEBUG_INFO, " SBI Scratch is at 0x%x.\n", ThisHartSbiScratch));
+ ThisHartSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(ThisHartSbiScratch);
+ DEBUG ((DEBUG_INFO, " SBI platform is at 0x%x.\n", ThisHartSbiPlatform));
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisHartSbiPlatform->firmware_context;
+ DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContext));
+ FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
+ DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", FirmwareContextHartSpecific));
+
+ //
+ // Build up RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
+ //
+ CommonFirmwareContextHartSpecificInfo (
+ FirmwareContextHartSpecific,
+ ParentProcessorGuid,
+ ParentProcessorUid,
+ (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid),
+ HartId,
+ IsBootHart,
+ &ProcessorSpecDataHob
+ );
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_H = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_H = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.HartXlen = RegisterLen64;
+ ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen = RegisterLen64;
+ ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterUnsupported;
+ ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen = RegisterLen64;
+
+ DEBUG ((DEBUG_INFO, " *HartId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *Is Boot Hart? = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.BootHartId));
+ DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported));
+ DEBUG ((DEBUG_INFO, " *MModeExcepDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *HartXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartXlen ));
+ DEBUG ((DEBUG_INFO, " *MachineModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen));
+ DEBUG ((DEBUG_INFO, " *SupervisorModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen));
+ DEBUG ((DEBUG_INFO, " *UserModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen));
+ DEBUG ((DEBUG_INFO, " *InstSetSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.InstSetSupported));
+ DEBUG ((DEBUG_INFO, " *MachineVendorId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineVendorId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineArchId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineArchId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineImplId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineImplId.Value64_L));
+
+ //
+ // Build GUID HOB for E51 core, this is for SMBIOS type 44
+ //
+ ProcessorSpecDataHobGuid = PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid);
+ CoreGuidHob = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA));
+ if (CoreGuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n"));
+ ASSERT (FALSE);
+ }
+ *GuidHobData = CoreGuidHob;
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51ProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
+ )
+{
+ EFI_GUID *GuidPtr;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA L1InstCacheDataHob;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCacheDataHobPtr;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;
+
+ if (SmbiosHobPtr == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Build up SMBIOS type 7 L1 instruction cache record.
+ //
+ ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid));
+ L1InstCacheDataHob.ProcessorUid = ProcessorUid;
+ L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeInstruction;
+ L1InstCacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L1InstCacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ if (L1InstCacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core L1 instruction cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 4 record.
+ //
+ ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
+ CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid));
+ ProcessorDataHob.ProcessorUid = ProcessorUid;
+ ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
+ SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
+ ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
+ ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = 0xffff;
+ ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
+ ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
+ ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
+ if (ProcessorDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+
+ ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
+ SmbiosDataHob.Processor = ProcessorDataHobPtr;
+ SmbiosDataHob.L1InstCache = L1InstCacheDataHobPtr;
+ SmbiosDataHob.L1DataCache = NULL;
+ SmbiosDataHob.L2Cache = NULL;
+ SmbiosDataHob.L3Cache = NULL;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
+ SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
+ if (SmbiosDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+ *SmbiosHobPtr = SmbiosDataHobPtr;
+ return EFI_SUCCESS;
+}
+
+
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 03/18] SiFive/U54: Initial version of SiFive U54 core library.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 01/18] Silicon/SiFive: Initial version of SiFive silicon package Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 02/18] SiFive/E51: Initial version of SiFive E51 core library Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 04/18] SiFive/U54MC: Initial version of SiFive U54MC Coreplex library Abner Chang
` (15 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
SiFive U54 core library for building core information hob data.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 48 ++++
Silicon/SiFive/Include/Library/SiFiveU54.h | 60 +++++
.../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 290 +++++++++++++++++++++
3 files changed, 398 insertions(+)
create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54.h
create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
new file mode 100644
index 0000000..665bf69
--- /dev/null
+++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -0,0 +1,48 @@
+## @file
+# Library instance to create core information HOB
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = SiliconSiFiveU54CoreInfoLib
+ FILE_GUID = 483DE090-267E-4278-A0A1-15D9836780EA
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconSiFiveU54CoreInfoLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ CoreInfoHob.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+ Silicon/SiFive/SiFive.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+ FirmwareContextProcessorSpecificLib
+
+
+[FixedPcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54CoreGuid
+
diff --git a/Silicon/SiFive/Include/Library/SiFiveU54.h b/Silicon/SiFive/Include/Library/SiFiveU54.h
new file mode 100644
index 0000000..9920a55
--- /dev/null
+++ b/Silicon/SiFive/Include/Library/SiFiveU54.h
@@ -0,0 +1,60 @@
+/** @file
+ SiFive U54 Core library definitions.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SIFIVE_U54_CORE_H_
+#define SIFIVE_U54_CORE_H_
+
+#include <PiPei.h>
+
+#include <SmbiosProcessorSpecificData.h>
+#include <ProcessorSpecificHobData.h>
+
+/**
+ Function to build core specific information HOB.
+
+ @param ParentProcessorGuid Parent processor od this core. ParentProcessorGuid
+ could be the same as CoreGuid if one processor has
+ only one core.
+ @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param HartId Hart ID of this core.
+ @param IsBootHart TRUE means this is the boot HART.
+ @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54CoreProcessorSpecificDataHob (
+ IN EFI_GUID *ParentProcessorGuid,
+ IN UINTN ParentProcessorUid,
+ IN UINTN HartId,
+ IN BOOLEAN IsBootHart,
+ OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobdata
+ );
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54ProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
+ );
+
+#endif
diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 0000000..74d1700
--- /dev/null
+++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,290 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/FirmwareContextProcessorSpecificLib.h>
+#include <Library/HobLib.h>
+#include <sbi/sbi.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <RiscVImpl.h>
+#include <SmbiosProcessorSpecificData.h>
+
+/**
+ Function to build core specific information HOB.
+
+ @param ParentProcessorGuid Parent processor od this core. ParentProcessorGuid
+ could be the same as CoreGuid if one processor has
+ only one core.
+ @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param HartId Hart ID of this core.
+ @param IsBootHart TRUE means this is the boot HART.
+ @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54CoreProcessorSpecificDataHob (
+ IN EFI_GUID *ParentProcessorGuid,
+ IN UINTN ParentProcessorUid,
+ IN UINTN HartId,
+ IN BOOLEAN IsBootHart,
+ OUT RISC_V_PROCESSOR_SPECIFIC_HOB_DATA **GuidHobdata
+ )
+{
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *CoreGuidHob;
+ EFI_GUID *ProcessorSpecDataHobGuid;
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA ProcessorSpecDataHob;
+ struct sbi_scratch *ThisHartSbiScratch;
+ struct sbi_platform *ThisHartSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
+
+ if (GuidHobdata == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ThisHartSbiScratch = sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(), (UINT32)HartId);
+ DEBUG ((DEBUG_INFO, " SBI Scratch is at 0x%x.\n", ThisHartSbiScratch));
+ ThisHartSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(ThisHartSbiScratch);
+ DEBUG ((DEBUG_INFO, " SBI platform is at 0x%x.\n", ThisHartSbiPlatform));
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisHartSbiPlatform->firmware_context;
+ DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContext));
+ FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
+ DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", FirmwareContextHartSpecific));
+
+ //
+ // Build up RISC_V_PROCESSOR_SPECIFIC_HOB_DATA.
+ //
+ CommonFirmwareContextHartSpecificInfo (
+ FirmwareContextHartSpecific,
+ ParentProcessorGuid,
+ ParentProcessorUid,
+ (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid),
+ HartId,
+ IsBootHart,
+ &ProcessorSpecDataHob
+ );
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_H = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_H = TO_BE_FILLED;
+ ProcessorSpecDataHob.ProcessorSpecificData.HartXlen = RegisterLen64;
+ ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen = RegisterLen64;
+ ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen = RegisterUnsupported;
+ ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen = RegisterLen64;
+
+ DEBUG ((DEBUG_INFO, " *HartId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *Is Boot Hart? = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.BootHartId));
+ DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported));
+ DEBUG ((DEBUG_INFO, " *MModeExcepDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " *HartXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.HartXlen ));
+ DEBUG ((DEBUG_INFO, " *MachineModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen));
+ DEBUG ((DEBUG_INFO, " *SupervisorModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen));
+ DEBUG ((DEBUG_INFO, " *UserModeXlen = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen));
+ DEBUG ((DEBUG_INFO, " *InstSetSupported = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.InstSetSupported));
+ DEBUG ((DEBUG_INFO, " *MachineVendorId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineVendorId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineArchId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineArchId.Value64_L));
+ DEBUG ((DEBUG_INFO, " *MachineImplId = 0x%x\n", ProcessorSpecDataHob.ProcessorSpecificData.MachineImplId.Value64_L));
+
+ //
+ // Build GUID HOB for U54 core.
+ //
+ ProcessorSpecDataHobGuid = PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid);
+ CoreGuidHob = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)BuildGuidDataHob (ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA));
+ if (CoreGuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n"));
+ ASSERT (FALSE);
+ }
+ *GuidHobdata = CoreGuidHob;
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54ProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
+ )
+{
+ EFI_GUID *GuidPtr;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA L1InstCacheDataHob;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA L1DataCacheDataHob;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCacheDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1DataCacheDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;
+
+ if (SmbiosHobPtr == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Build up SMBIOS type 7 L1 instruction cache record.
+ //
+ ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
+ L1InstCacheDataHob.ProcessorUid = ProcessorUid;
+ L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeInstruction;
+ L1InstCacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L1InstCacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ if (L1InstCacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 instruction cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 7 L1 data cache record.
+ //
+ ZeroMem((VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ CopyGuid (&L1DataCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
+ L1DataCacheDataHob.ProcessorUid = ProcessorUid;
+ L1DataCacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L1DataCacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L1DataCacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L1DataCacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L1DataCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L1DataCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L1DataCacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L1DataCacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L1DataCacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeData;
+ L1DataCacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L1DataCacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ if (L1DataCacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 data cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 7 L2 cache record.
+ //
+ ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ CopyGuid (&L2CacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
+ L2CacheDataHob.ProcessorUid = ProcessorUid;
+ L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L2CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
+ L2CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L2CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ if (L2CacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L2 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 4 record.
+ //
+ ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
+ CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid));
+ ProcessorDataHob.ProcessorUid = ProcessorUid;
+ ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
+ SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
+ ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
+ ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
+ ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount = 1;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
+ ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
+ if (ProcessorDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+
+ ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
+ SmbiosDataHob.Processor = ProcessorDataHobPtr;
+ SmbiosDataHob.L1InstCache = L1InstCacheDataHobPtr;
+ SmbiosDataHob.L1DataCache = L1DataCacheDataHobPtr;
+ SmbiosDataHob.L2Cache = L2CacheDataHobPtr;
+ SmbiosDataHob.L3Cache = NULL;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
+ SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
+ if (SmbiosDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+ *SmbiosHobPtr = SmbiosDataHobPtr;
+ return EFI_SUCCESS;
+}
+
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 04/18] SiFive/U54MC: Initial version of SiFive U54MC Coreplex library.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (2 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 03/18] SiFive/U54: Initial version of SiFive U54 " Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 05/18] U5SeriesPkg/PeiCoreInfoHobLib: Library to create core information Abner Chang
` (14 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
SiFive U54MC Coreplex library for building core information hob data.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 46 ++++++
.../SiFive/Include/Library/SiFiveU54MCCoreplex.h | 55 ++++++
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 184 +++++++++++++++++++++
3 files changed, 285 insertions(+)
create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
new file mode 100644
index 0000000..c5f4478
--- /dev/null
+++ b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -0,0 +1,46 @@
+## @file
+# Library instance to create core information HOB
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = SiliconSiFiveU54MCCoreplexInfoLib
+ FILE_GUID = 483DE090-267E-4278-A0A1-15D9836780EA
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconSiFiveU54MCCoreplexInfoLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ CoreInfoHob.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+ Silicon/SiFive/SiFive.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+ SiliconSiFiveE51CoreInfoLib
+ SiliconSiFiveU54CoreInfoLib
+
+[FixedPcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54MCCoreplexGuid
+
diff --git a/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h b/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
new file mode 100644
index 0000000..0e14b28
--- /dev/null
+++ b/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
@@ -0,0 +1,55 @@
+/** @file
+ SiFive U54 Coreplex library definitions.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SIFIVE_U54MC_COREPLEX_CORE_H_
+#define SIFIVE_U54MC_COREPLEX_CORE_H_
+
+#include <PiPei.h>
+
+#include <SmbiosProcessorSpecificData.h>
+#include <ProcessorSpecificHobData.h>
+
+#define SIFIVE_U54MC_COREPLEX_E51_HART_ID 0
+#define SIFIVE_U54MC_COREPLEX_U54_0_HART_ID 1
+#define SIFIVE_U54MC_COREPLEX_U54_1_HART_ID 2
+#define SIFIVE_U54MC_COREPLEX_U54_2_HART_ID 3
+#define SIFIVE_U54MC_COREPLEX_U54_3_HART_ID 4
+
+/**
+ Build up U54MC coreplex processor core-specific information.
+
+ @param UniqueId U54MC unique ID.
+
+ @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54MCCoreplexProcessorSpecificDataHob (
+ IN UINTN UniqueId
+ );
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54MCProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
+ );
+#endif
diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 0000000..97bed2a
--- /dev/null
+++ b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,184 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/SiFiveE51.h>
+#include <Library/SiFiveU54.h>
+#include <Library/SiFiveU54MCCoreplex.h>
+
+/**
+ Build up processor-specific HOB for U54MC Coreplex
+
+ @param UniqueId Unique ID of this U54MC Coreplex processor
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54MCCoreplexProcessorSpecificDataHob (
+ IN UINTN UniqueId
+ )
+{
+ EFI_STATUS Status;
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ThisGuidHobData;
+ EFI_GUID *ParentProcessorGuid;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__));
+
+ ParentProcessorGuid = PcdGetPtr (PcdSiFiveU54MCCoreplexGuid);
+ Status = CreateE51CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54MC_COREPLEX_E51_HART_ID, FALSE, &ThisGuidHobData);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Faile to build E51 core information HOB for U54 Coreplex.\n", __FUNCTION__));
+ return Status;
+ }
+ Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_0_HART_ID, TRUE, &ThisGuidHobData);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
+ return Status;
+ }
+ Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_1_HART_ID, FALSE, &ThisGuidHobData);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
+ return Status;
+ }
+ Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_2_HART_ID, FALSE, &ThisGuidHobData);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
+ return Status;
+ }
+ Status = CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, UniqueId, SIFIVE_U54_COREPLEX_U54MC_3_HART_ID, FALSE, &ThisGuidHobData);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for U54 Coreplex.\n", __FUNCTION__));
+ return Status;
+ }
+ return Status;
+}
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54MCProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ IN RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
+ )
+{
+ EFI_GUID *GuidPtr;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;
+
+ if (SmbiosHobPtr == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Build up SMBIOS type 7 L2 cache record.
+ //
+ ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ L2CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCCoreplexGuid));
+ L2CacheDataHob.ProcessorUid = ProcessorUid;
+ L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L2CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
+ L2CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L2CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ if (L2CacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreplex L2 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 4 record.
+ //
+ ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
+ ProcessorDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCCoreplexGuid));
+ ProcessorDataHob.ProcessorUid = ProcessorUid;
+ ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
+ SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
+ ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
+ ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
+ ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount = 5;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = 5;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount = 5;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
+ ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
+ if (ProcessorDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreplex RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+
+ ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
+ SmbiosDataHob.Processor = ProcessorDataHobPtr;
+ SmbiosDataHob.L1InstCache = NULL;
+ SmbiosDataHob.L1DataCache = NULL;
+ SmbiosDataHob.L2Cache = L2CacheDataHobPtr;
+ SmbiosDataHob.L3Cache = NULL;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
+ SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
+ if (SmbiosDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54MC Coreplex RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+ *SmbiosHobPtr = SmbiosDataHobPtr;
+ return EFI_SUCCESS;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 05/18] U5SeriesPkg/PeiCoreInfoHobLib: Library to create core information.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (3 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 04/18] SiFive/U54MC: Initial version of SiFive U54MC Coreplex library Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 06/18] U5SeriesPkg/TimerDxe: U5 Series Platform Timer DXE driver Abner Chang
` (13 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
This is the library to create U5MC Coreplex specific information for
U5 series platforms.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 58 ++++++
.../U5SeriesPkg/Include/SiFiveU5MCCoreplex.h | 51 ++++++
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 195 +++++++++++++++++++++
3 files changed, 304 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
new file mode 100644
index 0000000..6e5da5e
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -0,0 +1,58 @@
+## @file
+# Library instance to create core information HOB
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = SiliconSiFiveU5MCCoreplexInfoLib
+ FILE_GUID = 4E397A71-5164-4E69-9884-70CBE2740AAB
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconSiFiveU5MCCoreplexInfoLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ CoreInfoHob.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+ Silicon/SiFive/SiFive.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+ SiliconSiFiveE51CoreInfoLib
+ SiliconSiFiveU54CoreInfoLib
+
+[Guids]
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid
+
+[Ppis]
+
+[FixedPcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU54CoreGuid
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveE51CoreGuid
+ gEfiSiFiveSiliconTokenSpaceGuid.PcdSiFiveU5MCCoreplexGuid
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
diff --git a/Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h b/Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h
new file mode 100644
index 0000000..5d70e26
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h
@@ -0,0 +1,51 @@
+/** @file
+ SiFive U54 Coreplex library definitions.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SIFIVE_U5MC_COREPLEX_H_
+#define SIFIVE_U5MC_COREPLEX_H_
+
+#include <PiPei.h>
+
+#include <SmbiosProcessorSpecificData.h>
+#include <ProcessorSpecificHobData.h>
+
+#define SIFIVE_U5MC_COREPLEX_MC_HART_ID 0
+
+/**
+ Build up U5MC coreplex processor core-specific information.
+
+ @param UniqueId U5MC unique ID.
+
+ @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCCoreplexProcessorSpecificDataHob (
+ IN UINTN UniqueId
+ );
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosDataHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosDataHobPtr
+ );
+#endif
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 0000000..c3bb0c4
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,195 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <SmbiosProcessorSpecificData.h>
+#include <ProcessorSpecificHobData.h>
+#include <SiFiveU5MCCoreplex.h>
+#include <Library/SiFiveE51.h>
+#include <Library/SiFiveU54.h>
+
+/**
+ Build up processor-specific HOB for U5MC Coreplex
+
+ @param UniqueId Unique ID of this U5MC Coreplex processor
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCCoreplexProcessorSpecificDataHob (
+ IN UINTN UniqueId
+ )
+{
+ EFI_STATUS Status;
+ UINT32 HartIdNumber;
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *GuidHobData;
+ EFI_GUID *ParentCoreGuid;
+ BOOLEAN MCSupport;
+
+ DEBUG ((DEBUG_INFO, "Building U5 Coreplex processor information HOB\n"));
+
+ HartIdNumber = 0;
+ ParentCoreGuid = PcdGetPtr(PcdSiFiveU5MCCoreplexGuid);
+ MCSupport = PcdGetBool (PcdE5MCSupported);
+ if (MCSupport == TRUE) {
+ Status = CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, FALSE, &GuidHobData);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\n"));
+ ASSERT (FALSE);
+ }
+ HartIdNumber ++;
+ DEBUG ((DEBUG_INFO, "Support E5 Monitor core on U5 platform, HOB at address 0x%x\n", GuidHobData));
+ }
+ for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + (UINT32)MCSupport); HartIdNumber ++) {
+ Status = CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, (HartIdNumber == FixedPcdGet32 (PcdBootHartId))? TRUE: FALSE, &GuidHobData);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\n"));
+ ASSERT (FALSE);
+ }
+ DEBUG ((DEBUG_INFO, "Support U5 application core on U5 platform, HOB Data at address 0x%x\n", GuidHobData));
+ }
+ DEBUG ((DEBUG_INFO, "Support %d U5 application cores on U5 platform\n", HartIdNumber - (UINT32)MCSupport));
+
+ if (HartIdNumber != FixedPcdGet32 (PcdHartCount)) {
+ DEBUG ((DEBUG_ERROR, "Improper core settings...\n"));
+ DEBUG ((DEBUG_ERROR, " PcdHartCount\n"));
+ DEBUG ((DEBUG_ERROR, " PcdNumberofU5Cores\n"));
+ DEBUG ((DEBUG_ERROR, " PcdE5MCSupported\n\n"));
+ ASSERT (FALSE);
+ }
+ return Status;
+}
+
+/**
+ Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
+ this information and build SMBIOS Type4 and Type7 record.
+
+ @param ProcessorUid Unique ID of pysical processor which owns this core.
+ @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
+ maintained in this structure is only valid before memory is discovered.
+ Access to those pointers after memory is installed will cause unexpected issues.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCProcessorSmbiosDataHob (
+ IN UINTN ProcessorUid,
+ OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
+ )
+{
+ EFI_GUID *GuidPtr;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA ProcessorDataHob;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (SmbiosHobPtr == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Build up SMBIOS type 7 L2 cache record.
+ //
+ ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ L2CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
+ L2CacheDataHob.ProcessorUid = ProcessorUid;
+ L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \
+ RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \
+ RISC_V_CACHE_CONFIGURATION_ENABLED | \
+ RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
+ L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
+ L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
+ L2CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
+ L2CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
+ L2CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
+ L2CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
+ if (L2CacheDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex L2 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Build up SMBIOS type 4 record.
+ //
+ ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
+ ProcessorDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
+ ProcessorDataHob.ProcessorUid = ProcessorUid;
+ ProcessorDataHob.SmbiosType4Processor.Socket = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorType = CentralProcessor;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily = ProcessorFamilyIndicatorFamily2;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture = TO_BE_FILLED_BY_VENDOR;
+ SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, sizeof (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE);
+ ProcessorDataHob.SmbiosType4Processor.ProcessorVersion = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability3_3V = 1;
+ ProcessorDataHob.SmbiosType4Processor.ExternalClock = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.MaxSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CurrentSpeed = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.Status = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.L1CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L2CacheHandle = TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER;
+ ProcessorDataHob.SmbiosType4Processor.L3CacheHandle = 0xffff;
+ ProcessorDataHob.SmbiosType4Processor.SerialNumber = TO_BE_FILLED_BY_CODE;
+ ProcessorDataHob.SmbiosType4Processor.AssetTag = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.PartNumber = TO_BE_FILLED_BY_VENDOR;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount = (UINT8)FixedPcdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported);
+ ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics = (UINT16)(1 << 2); // 64-bit capable
+ ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 = ProcessorFamilyRiscVRV64;
+ ProcessorDataHob.SmbiosType4Processor.CoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 = 0;
+ ProcessorDataHob.SmbiosType4Processor.ThreadCount2 = 0;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid);
+ ProcessorDataHobPtr = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_HOB_DATA));
+ if (ProcessorDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex RISC_V_PROCESSOR_TYPE4_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+
+ ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
+ SmbiosDataHob.Processor = ProcessorDataHobPtr;
+ SmbiosDataHob.L1InstCache = NULL;
+ SmbiosDataHob.L1DataCache = NULL;
+ SmbiosDataHob.L2Cache = L2CacheDataHobPtr;
+ SmbiosDataHob.L3Cache = NULL;
+ GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
+ SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
+ if (SmbiosDataHobPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n"));
+ ASSERT (FALSE);
+ }
+ *SmbiosHobPtr = SmbiosDataHobPtr;
+ DEBUG ((DEBUG_INFO, "%a: Exit\n", __FUNCTION__));
+ return EFI_SUCCESS;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 06/18] U5SeriesPkg/TimerDxe: U5 Series Platform Timer DXE driver.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (4 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 05/18] U5SeriesPkg/PeiCoreInfoHobLib: Library to create core information Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 07/18] U5SeriesPkg/RamFvbServicesRuntimeDxe: Firmware Volume Block service Abner Chang
` (12 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
Timer DXE implementation for U5 series platform.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../Universal/Dxe/TimerDxe/TimerDxe.inf | 53 ++++
.../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.h | 174 ++++++++++++
.../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c | 304 +++++++++++++++++++++
.../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.uni | 14 +
| 12 +
5 files changed, 557 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.h
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.uni
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerExtra.uni
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
new file mode 100644
index 0000000..413f2e5
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
@@ -0,0 +1,53 @@
+## @file
+# RISC-V Timer Arch protocol module for U5 Series platform
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = Timer
+ MODULE_UNI_FILE = Timer.uni
+ FILE_GUID = 3F75D495-23FF-46B6-9D19-0DECC8A4EA91
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = TimerDriverInitialize
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Sources]
+ Timer.h
+ Timer.c
+
+[Protocols]
+ gEfiCpuArchProtocolGuid ## CONSUMES
+ gEfiTimerArchProtocolGuid ## PRODUCES
+
+[Pcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
+
+[Depex]
+ gEfiCpuArchProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ TimerExtra.uni
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.h b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.h
new file mode 100644
index 0000000..8301685
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.h
@@ -0,0 +1,174 @@
+/** @file
+ RISC-V Timer Architectural Protocol definitions for U5 Series platform,
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef U5_SERIES_TIMER_H_
+#define U5_SERIES_TIMER_H_
+
+#include <PiDxe.h>
+
+#include <Protocol/Cpu.h>
+#include <Protocol/Timer.h>
+
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/RiscVCpuLib.h>
+
+//
+// RISC-V use 100us timer.
+// The default timer tick duration is set to 10 ms = 10 * 1000 * 10 100 ns units
+//
+#define DEFAULT_TIMER_TICK_DURATION 100000
+
+extern VOID RiscvSetTimerPeriod (UINT32 TimerPeriod);
+
+//
+// Function Prototypes
+//
+/**
+ Initialize the Timer Architectural Protocol driver
+
+ @param ImageHandle ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Timer Architectural Protocol created
+ @retval EFI_OUT_OF_RESOURCES Not enough resources available to initialize driver.
+ @retval EFI_DEVICE_ERROR A device error occured attempting to initialize the driver.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+;
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverRegisterHandler (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_TIMER_NOTIFY NotifyFunction
+ )
+;
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverSetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod
+ )
+;
+
+/**
+
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+ 0 is returned, then the timer is currently disabled.
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+;
+
+/**
+
+ This function generates a soft timer interrupt. If the platform does not support soft
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+ enabled when this service is called, then the registered handler will be invoked. The
+ registered handler should not be able to distinguish a hardware-generated timer
+ interrupt from a software-generated timer interrupt.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The soft timer interrupt was generated.
+ @retval EFI_UNSUPPORTEDT The platform does not support the generation of soft timer interrupts.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGenerateSoftInterrupt (
+ IN EFI_TIMER_ARCH_PROTOCOL *This
+ )
+;
+
+#endif
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c
new file mode 100644
index 0000000..6217227
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c
@@ -0,0 +1,304 @@
+/** @file
+ RISC-V Timer Architectural Protocol for U5 series platform.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Timer.h"
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi.h>
+#include <sbi/riscv_io.h>
+#include <sbi/riscv_atomic.h>
+#include <U5Clint.h>
+
+STATIC volatile VOID * const p_mtime = (VOID *)CLINT_REG_MTIME;
+#define MTIME (*p_mtime)
+#define MTIMECMP(i) (p_mtimecmp[i])
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+STATIC EFI_HANDLE mTimerHandle = NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL mTimer = {
+ TimerDriverRegisterHandler,
+ TimerDriverSetTimerPeriod,
+ TimerDriverGetTimerPeriod,
+ TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction;
+
+//
+// The current period of the timer interrupt
+//
+STATIC UINT64 mTimerPeriod = 0;
+
+/**
+ U5 Series Timer Interrupt Handler.
+
+ @param InterruptType The type of interrupt that occured
+ @param SystemContext A pointer to the system context when the interrupt occured
+**/
+
+VOID
+EFIAPI
+TimerInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ EFI_TPL OriginalTPL;
+ UINT64 RiscvTimer;
+
+ csr_clear(CSR_SIE, MIP_STIP); // Disable timer int
+ csr_clear(CSR_SIP, MIP_STIP);
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ if (mTimerPeriod == 0) {
+ gBS->RestoreTPL (OriginalTPL);
+ mCpu->DisableInterrupt(mCpu);
+ return;
+ }
+ if (mTimerNotifyFunction != NULL) {
+ mTimerNotifyFunction (mTimerPeriod);
+ }
+ gBS->RestoreTPL (OriginalTPL);
+
+ RiscvTimer = readq_relaxed(p_mtime);
+ sbi_set_timer(RiscvTimer += mTimerPeriod);
+ csr_set(CSR_SIE, MIP_STIP); // enable timer int
+
+}
+
+/**
+
+ This function registers the handler NotifyFunction so it is called every time
+ the timer interrupt fires. It also passes the amount of time since the last
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+ returned. If the CPU does not support registering a timer interrupt handler,
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not registered,
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+ is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires. This
+ function executes at TPL_HIGH_LEVEL. The DXE Core will
+ register a handler for the timer interrupt, so it can know
+ how much time has passed. This information is used to
+ signal timer based events. NULL will unregister the handler.
+
+ @retval EFI_SUCCESS The timer handler was registered.
+ @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+ registered.
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+ previously registered.
+ @retval EFI_DEVICE_ERROR The timer handler could not be registered.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverRegisterHandler (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_TIMER_NOTIFY NotifyFunction
+ )
+{
+ DEBUG ((DEBUG_INFO, "TimerDriverRegisterHandler(0x%lx) called\n", NotifyFunction));
+ mTimerNotifyFunction = NotifyFunction;
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverSetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod
+ )
+{
+ UINT64 RiscvTimer;
+
+ DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod));
+
+ if (TimerPeriod == 0) {
+ mTimerPeriod = 0;
+ mCpu->DisableInterrupt(mCpu);
+ csr_clear(CSR_SIE, MIP_STIP); // disable timer int
+ return EFI_SUCCESS;
+ }
+
+ mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
+
+ RiscvTimer = readq_relaxed(p_mtime);
+ sbi_set_timer(RiscvTimer + mTimerPeriod);
+
+ mCpu->EnableInterrupt(mCpu);
+ csr_set(CSR_SIE, MIP_STIP); // enable timer int
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+ 0 is returned, then the timer is currently disabled.
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+{
+ *TimerPeriod = mTimerPeriod;
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function generates a soft timer interrupt. If the platform does not support soft
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+ enabled when this service is called, then the registered handler will be invoked. The
+ registered handler should not be able to distinguish a hardware-generated timer
+ interrupt from a software-generated timer interrupt.
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The soft timer interrupt was generated.
+ @retval EFI_UNSUPPORTEDT The platform does not support the generation of soft timer interrupts.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGenerateSoftInterrupt (
+ IN EFI_TIMER_ARCH_PROTOCOL *This
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Initialize the Timer Architectural Protocol driver
+
+ @param ImageHandle ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Timer Architectural Protocol created
+ @retval EFI_OUT_OF_RESOURCES Not enough resources available to initialize driver.
+ @retval EFI_DEVICE_ERROR A device error occured attempting to initialize the driver.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Initialize the pointer to our notify function.
+ //
+ mTimerNotifyFunction = NULL;
+
+ //
+ // Make sure the Timer Architectural Protocol is not already installed in the system
+ //
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiTimerArchProtocolGuid);
+
+ //
+ // Find the CPU architectural protocol.
+ //
+ Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **) &mCpu);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Force the timer to be disabled
+ //
+ Status = TimerDriverSetTimerPeriod (&mTimer, 0);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install interrupt handler for RISC-V Timer.
+ //
+ Status = mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_TIMER_INT, TimerInterruptHandler);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Force the timer to be enabled at its default period
+ //
+ Status = TimerDriverSetTimerPeriod (&mTimer, DEFAULT_TIMER_TICK_DURATION);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install the Timer Architectural Protocol onto a new handle
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mTimerHandle,
+ &gEfiTimerArchProtocolGuid, &mTimer,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.uni b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.uni
new file mode 100644
index 0000000..3830224
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.uni
@@ -0,0 +1,14 @@
+// /** @file
+//
+// RISC-V Timer Arch protocol strings.
+//
+// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "RISC-V timer driver that provides Timer Arch protocol"
+
+#string STR_MODULE_DESCRIPTION #language en-US "RISC-V timer driver that provides Timer Arch protocol."
--git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerExtra.uni b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerExtra.uni
new file mode 100644
index 0000000..cf25ff1
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerExtra.uni
@@ -0,0 +1,12 @@
+// /** @file
+// Timer Localized Strings and Content
+//
+// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"RISC-V Timer DXE Driver"
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 07/18] U5SeriesPkg/RamFvbServicesRuntimeDxe: Firmware Volume Block service.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (5 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 06/18] U5SeriesPkg/TimerDxe: U5 Series Platform Timer DXE driver Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 08/18] U5SeriesPkg/RiscVPlatformTimerLib: Platform Timer library Abner Chang
` (11 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
RAM based Firmware Volume Block service runtime driver for U5 series
platforms.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../FvbServicesRuntimeDxe.inf | 80 ++
.../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h | 187 ++++
.../Dxe/RamFvbServicesRuntimeDxe/RamFlash.h | 85 ++
.../Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c | 127 +++
.../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c | 1114 ++++++++++++++++++++
.../RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c | 150 +++
.../Dxe/RamFvbServicesRuntimeDxe/RamFlash.c | 145 +++
.../Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c | 20 +
8 files changed, 1908 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c
create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
new file mode 100644
index 0000000..9db112a
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
@@ -0,0 +1,80 @@
+## @file
+# Component description file for RAM Flash Fimware Volume Block DXE driver
+# module.
+#
+# This DXE runtime driver implements and produces the Fimware Volue Block
+# Protocol for a RAM flash device.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = FvbServicesRuntimeDxe
+ FILE_GUID = B04036D3-4C60-43D6-9850-0FCC090FF054
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = FvbInitialize
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ FvbInfo.c
+ FwBlockService.c
+ FwBlockServiceDxe.c
+ RamFlash.c
+ RamFlashDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DevicePathLib
+ DxeServicesTableLib
+ MemoryAllocationLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeLib
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid # ALWAYS_CONSUMED
+ # gEfiEventVirtualAddressChangeGuid # Create Event: EVENT_GROUP_GUID
+
+[Protocols]
+ gEfiFirmwareVolumeBlockProtocolGuid # PROTOCOL SOMETIMES_PRODUCED
+ gEfiDevicePathProtocolGuid # PROTOCOL SOMETIMES_PRODUCED
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+
+[Depex]
+ TRUE
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h
new file mode 100644
index 0000000..96d0141
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h
@@ -0,0 +1,187 @@
+/**@file
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ Module Name:
+
+ FwBlockService.h
+
+ Abstract:
+
+ Firmware volume block driver for Intel Firmware Hub (FWH) device
+
+**/
+
+#ifndef FW_BLOCK_SERVICE_H_
+#define FW_BLOCK_SERVICE_H_
+
+typedef struct {
+ UINTN FvBase;
+ UINTN NumOfBlocks;
+ EFI_FIRMWARE_VOLUME_HEADER VolumeHeader;
+} EFI_FW_VOL_INSTANCE;
+
+typedef struct {
+ UINT32 NumFv;
+ EFI_FW_VOL_INSTANCE *FvInstance;
+} ESAL_FWB_GLOBAL;
+
+extern ESAL_FWB_GLOBAL *mFvbModuleGlobal;
+
+//
+// Fvb Protocol instance data
+//
+#define FVB_DEVICE_FROM_THIS(a) CR (a, EFI_FW_VOL_BLOCK_DEVICE, \
+ FwVolBlockInstance, FVB_DEVICE_SIGNATURE)
+
+#define FVB_EXTEND_DEVICE_FROM_THIS(a) CR (a, EFI_FW_VOL_BLOCK_DEVICE, \
+ FvbExtension, FVB_DEVICE_SIGNATURE)
+
+#define FVB_DEVICE_SIGNATURE SIGNATURE_32 ('F', 'V', 'B', 'N')
+
+typedef struct {
+ MEDIA_FW_VOL_DEVICE_PATH FvDevPath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevPath;
+} FV_PIWG_DEVICE_PATH;
+
+typedef struct {
+ MEMMAP_DEVICE_PATH MemMapDevPath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevPath;
+} FV_MEMMAP_DEVICE_PATH;
+
+typedef struct {
+ UINTN Signature;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ UINTN Instance;
+ EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL FwVolBlockInstance;
+} EFI_FW_VOL_BLOCK_DEVICE;
+
+EFI_STATUS
+GetFvbInfo (
+ IN UINT64 FvLength,
+ OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo
+ );
+
+EFI_STATUS
+FvbSetVolumeAttributes (
+ IN UINTN Instance,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes,
+ IN ESAL_FWB_GLOBAL *Global
+ );
+
+EFI_STATUS
+FvbGetVolumeAttributes (
+ IN UINTN Instance,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes,
+ IN ESAL_FWB_GLOBAL *Global
+ );
+
+EFI_STATUS
+FvbGetPhysicalAddress (
+ IN UINTN Instance,
+ OUT EFI_PHYSICAL_ADDRESS *Address,
+ IN ESAL_FWB_GLOBAL *Global
+ );
+
+EFI_STATUS
+EFIAPI
+FvbInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+
+VOID
+EFIAPI
+FvbClassAddressChangeEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+
+EFI_STATUS
+FvbGetLbaAddress (
+ IN UINTN Instance,
+ IN EFI_LBA Lba,
+ OUT UINTN *LbaAddress,
+ OUT UINTN *LbaLength,
+ OUT UINTN *NumOfBlocks,
+ IN ESAL_FWB_GLOBAL *Global
+ );
+
+//
+// Protocol APIs
+//
+EFI_STATUS
+EFIAPI
+FvbProtocolGetAttributes (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+FvbProtocolSetAttributes (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+FvbProtocolGetPhysicalAddress (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ );
+
+EFI_STATUS
+EFIAPI
+FvbProtocolGetBlockSize (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ IN CONST EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumOfBlocks
+ );
+
+EFI_STATUS
+EFIAPI
+FvbProtocolRead (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ IN CONST EFI_LBA Lba,
+ IN CONST UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+FvbProtocolWrite (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+FvbProtocolEraseBlocks (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ ...
+ );
+
+//
+// The following functions have different implementations dependent on the
+// module type chosen for building this driver.
+//
+VOID
+InstallProtocolInterfaces (
+ IN EFI_FW_VOL_BLOCK_DEVICE *FvbDevice
+ );
+
+VOID
+InstallVirtualAddressChangeHandler (
+ VOID
+ );
+#endif
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h
new file mode 100644
index 0000000..2c18283
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h
@@ -0,0 +1,85 @@
+/** @file
+ Ram flash device for EFI variable
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RAM_FLASH_H_
+#define RAM_FLASH_H_
+
+#include <Protocol/FirmwareVolumeBlock.h>
+
+extern VOID *mFlashBase;
+
+/**
+ Read from Ram Flash
+
+ @param[in] Lba The starting logical block index to read from.
+ @param[in] Offset Offset into the block at which to begin reading.
+ @param[in] NumBytes On input, indicates the requested read size. On
+ output, indicates the actual number of bytes read
+ @param[in] Buffer Pointer to the buffer to read into.
+
+**/
+EFI_STATUS
+RamFlashRead (
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+
+/**
+ Write to Ram Flash
+
+ @param[in] Lba The starting logical block index to write to.
+ @param[in] Offset Offset into the block at which to begin writing.
+ @param[in] NumBytes On input, indicates the requested write size. On
+ output, indicates the actual number of bytes written
+ @param[in] Buffer Pointer to the data to write.
+
+**/
+EFI_STATUS
+RamFlashWrite (
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+
+/**
+ Erase a Ram Flash block
+
+ @param Lba The logical block index to erase.
+
+**/
+EFI_STATUS
+RamFlashEraseBlock (
+ IN EFI_LBA Lba
+ );
+
+
+/**
+ Initializes Ram flash memory support
+
+ @retval EFI_WRITE_PROTECTED The Ram flash device is not present.
+ @retval EFI_SUCCESS The Ram flash device is supported.
+
+**/
+EFI_STATUS
+RamFlashInitialize (
+ VOID
+ );
+
+
+VOID
+RamFlashConvertPointers (
+ VOID
+ );
+
+#endif
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
new file mode 100644
index 0000000..1ade0d1
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
@@ -0,0 +1,127 @@
+/**@file
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ Module Name:
+
+ FvbInfo.c
+
+ Abstract:
+
+ Defines data structure that is the volume header found.These data is intent
+ to decouple FVB driver with FV header.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <Pi/PiFirmwareVolume.h>
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include <Guid/SystemNvDataGuid.h>
+//
+// The Library classes this module consumes
+//
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+
+typedef struct {
+ UINT64 FvLength;
+ EFI_FIRMWARE_VOLUME_HEADER FvbInfo;
+ //
+ // EFI_FV_BLOCK_MAP_ENTRY ExtraBlockMap[n];//n=0
+ //
+ EFI_FV_BLOCK_MAP_ENTRY End[1];
+} EFI_FVB_MEDIA_INFO;
+
+EFI_FVB_MEDIA_INFO mPlatformFvbMediaInfo[] = {
+ //
+ // Systen NvStorage FVB
+ //
+ {
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+ {
+ {
+ 0,
+ }, // ZeroVector[16]
+ EFI_SYSTEM_NV_DATA_FV_GUID,
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+ EFI_FVH_SIGNATURE,
+ EFI_FVB2_MEMORY_MAPPED |
+ EFI_FVB2_READ_ENABLED_CAP |
+ EFI_FVB2_READ_STATUS |
+ EFI_FVB2_WRITE_ENABLED_CAP |
+ EFI_FVB2_WRITE_STATUS |
+ EFI_FVB2_ERASE_POLARITY |
+ EFI_FVB2_ALIGNMENT_16,
+ sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
+ 0, // CheckSum
+ 0, // ExtHeaderOffset
+ {
+ 0,
+ }, // Reserved[1]
+ 2, // Revision
+ {
+ {
+ (FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)) /
+ FixedPcdGet32 (PcdVariableFdBlockSize),
+ FixedPcdGet32 (PcdVariableFdBlockSize),
+ }
+ } // BlockMap[1]
+ },
+ {
+ {
+ 0,
+ 0
+ }
+ } // End[1]
+ }
+};
+
+EFI_STATUS
+GetFvbInfo (
+ IN UINT64 FvLength,
+ OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo
+ )
+{
+ STATIC BOOLEAN Checksummed = FALSE;
+ UINTN Index;
+
+ if (!Checksummed) {
+ for (Index = 0;
+ Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO);
+ Index += 1) {
+ UINT16 Checksum;
+ mPlatformFvbMediaInfo[Index].FvbInfo.Checksum = 0;
+ Checksum = CalculateCheckSum16 (
+ (UINT16*) &mPlatformFvbMediaInfo[Index].FvbInfo,
+ mPlatformFvbMediaInfo[Index].FvbInfo.HeaderLength
+ );
+ mPlatformFvbMediaInfo[Index].FvbInfo.Checksum = Checksum;
+ }
+ Checksummed = TRUE;
+ }
+
+ for (Index = 0;
+ Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO);
+ Index += 1) {
+ if (mPlatformFvbMediaInfo[Index].FvLength == FvLength) {
+ *FvbInfo = &mPlatformFvbMediaInfo[Index].FvbInfo;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c
new file mode 100644
index 0000000..b695693
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c
@@ -0,0 +1,1114 @@
+/**@file
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ Module Name:
+
+ FWBlockService.c
+
+ Abstract:
+
+ Revision History
+
+**/
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include <Protocol/DevicePath.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include "FwBlockService.h"
+#include "RamFlash.h"
+
+#define EFI_FVB2_STATUS \
+ (EFI_FVB2_READ_STATUS | EFI_FVB2_WRITE_STATUS | EFI_FVB2_LOCK_STATUS)
+
+ESAL_FWB_GLOBAL *mFvbModuleGlobal;
+
+FV_MEMMAP_DEVICE_PATH mFvMemmapDevicePathTemplate = {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_MEMMAP_DP,
+ {
+ (UINT8)(sizeof (MEMMAP_DEVICE_PATH)),
+ (UINT8)(sizeof (MEMMAP_DEVICE_PATH) >> 8)
+ }
+ },
+ EfiMemoryMappedIO,
+ (EFI_PHYSICAL_ADDRESS) 0,
+ (EFI_PHYSICAL_ADDRESS) 0,
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+};
+
+FV_PIWG_DEVICE_PATH mFvPIWGDevicePathTemplate = {
+ {
+ {
+ MEDIA_DEVICE_PATH,
+ MEDIA_PIWG_FW_VOL_DP,
+ {
+ (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH)),
+ (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH) >> 8)
+ }
+ },
+ { 0 }
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+};
+
+EFI_FW_VOL_BLOCK_DEVICE mFvbDeviceTemplate = {
+ FVB_DEVICE_SIGNATURE,
+ NULL,
+ 0,
+ {
+ FvbProtocolGetAttributes,
+ FvbProtocolSetAttributes,
+ FvbProtocolGetPhysicalAddress,
+ FvbProtocolGetBlockSize,
+ FvbProtocolRead,
+ FvbProtocolWrite,
+ FvbProtocolEraseBlocks,
+ NULL
+ }
+};
+
+/*++
+
+ Routine Description:
+ Retrieves the physical address of a memory mapped FV
+
+ Arguments:
+ Instance - The FV instance whose base address is going to be
+ returned
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all
+ instance data
+ FwhInstance - The EFI_FW_VOL_INSTANCE fimrware instance structure
+
+ Returns:
+ EFI_SUCCESS - Successfully returns
+ EFI_INVALID_PARAMETER - Instance not found
+
+--*/
+EFI_STATUS
+GetFvbInstance (
+ IN UINTN Instance,
+ IN ESAL_FWB_GLOBAL *Global,
+ OUT EFI_FW_VOL_INSTANCE **FwhInstance
+)
+{
+ EFI_FW_VOL_INSTANCE *FwhRecord;
+
+ *FwhInstance = NULL;
+ if (Instance >= Global->NumFv) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Find the right instance of the FVB private data
+ //
+ FwhRecord = Global->FvInstance;
+ while (Instance > 0) {
+ FwhRecord = (EFI_FW_VOL_INSTANCE *)
+ (
+ (UINTN)FwhRecord + FwhRecord->VolumeHeader.HeaderLength +
+ (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER))
+ );
+ Instance--;
+ }
+
+ *FwhInstance = FwhRecord;
+
+ return EFI_SUCCESS;
+}
+
+/*++
+
+ Routine Description:
+ Retrieves the physical address of a memory mapped FV
+
+ Arguments:
+ Instance - The FV instance whose base address is going to be
+ returned
+ Address - Pointer to a caller allocated EFI_PHYSICAL_ADDRESS
+ that on successful return, contains the base
+ address of the firmware volume.
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all
+ instance data
+
+ Returns:
+ EFI_SUCCESS - Successfully returns
+ EFI_INVALID_PARAMETER - Instance not found
+
+--*/
+EFI_STATUS
+FvbGetPhysicalAddress (
+ IN UINTN Instance,
+ OUT EFI_PHYSICAL_ADDRESS *Address,
+ IN ESAL_FWB_GLOBAL *Global
+)
+{
+ EFI_FW_VOL_INSTANCE *FwhInstance;
+ EFI_STATUS Status;
+
+ //
+ // Find the right instance of the FVB private data
+ //
+ Status = GetFvbInstance (Instance, Global, &FwhInstance);
+ ASSERT_EFI_ERROR (Status);
+ *Address = FwhInstance->FvBase;
+
+ return EFI_SUCCESS;
+}
+/*++
+
+ Routine Description:
+ Retrieves attributes, insures positive polarity of attribute bits, returns
+ resulting attributes in output parameter
+
+ Arguments:
+ Instance - The FV instance whose attributes is going to be
+ returned
+ Attributes - Output buffer which contains attributes
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all
+ instance data
+
+ Returns:
+ EFI_SUCCESS - Successfully returns
+ EFI_INVALID_PARAMETER - Instance not found
+
+--*/
+EFI_STATUS
+FvbGetVolumeAttributes (
+ IN UINTN Instance,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes,
+ IN ESAL_FWB_GLOBAL *Global
+ )
+{
+ EFI_FW_VOL_INSTANCE *FwhInstance;
+ EFI_STATUS Status;
+
+ //
+ // Find the right instance of the FVB private data
+ //
+ Status = GetFvbInstance (Instance, Global, &FwhInstance);
+ ASSERT_EFI_ERROR (Status);
+ *Attributes = FwhInstance->VolumeHeader.Attributes;
+
+ return EFI_SUCCESS;
+}
+
+/*++
+
+ Routine Description:
+ Retrieves the starting address of an LBA in an FV
+
+ Arguments:
+ Instance - The FV instance which the Lba belongs to
+ Lba - The logical block address
+ LbaAddress - On output, contains the physical starting address
+ of the Lba
+ LbaLength - On output, contains the length of the block
+ NumOfBlocks - A pointer to a caller allocated UINTN in which the
+ number of consecutive blocks starting with Lba is
+ returned. All blocks in this range have a size of
+ BlockSize
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all
+ instance data
+
+ Returns:
+ EFI_SUCCESS - Successfully returns
+ EFI_INVALID_PARAMETER - Instance not found
+
+--*/
+EFI_STATUS
+FvbGetLbaAddress (
+ IN UINTN Instance,
+ IN EFI_LBA Lba,
+ OUT UINTN *LbaAddress,
+ OUT UINTN *LbaLength,
+ OUT UINTN *NumOfBlocks,
+ IN ESAL_FWB_GLOBAL *Global
+ )
+{
+ UINT32 NumBlocks;
+ UINT32 BlockLength;
+ UINTN Offset;
+ EFI_LBA StartLba;
+ EFI_LBA NextLba;
+ EFI_FW_VOL_INSTANCE *FwhInstance;
+ EFI_FV_BLOCK_MAP_ENTRY *BlockMap;
+ EFI_STATUS Status;
+
+ //
+ // Find the right instance of the FVB private data
+ //
+ Status = GetFvbInstance (Instance, Global, &FwhInstance);
+ ASSERT_EFI_ERROR (Status);
+
+ StartLba = 0;
+ Offset = 0;
+ BlockMap = &(FwhInstance->VolumeHeader.BlockMap[0]);
+
+ //
+ // Parse the blockmap of the FV to find which map entry the Lba belongs to
+ //
+ while (TRUE) {
+ NumBlocks = BlockMap->NumBlocks;
+ BlockLength = BlockMap->Length;
+
+ if (NumBlocks == 0 || BlockLength == 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ NextLba = StartLba + NumBlocks;
+
+ //
+ // The map entry found
+ //
+ if (Lba >= StartLba && Lba < NextLba) {
+ Offset = Offset + (UINTN) MultU64x32 ((Lba - StartLba), BlockLength);
+ if (LbaAddress != NULL) {
+ *LbaAddress = FwhInstance->FvBase + Offset;
+ }
+
+ if (LbaLength != NULL) {
+ *LbaLength = BlockLength;
+ }
+
+ if (NumOfBlocks != NULL) {
+ *NumOfBlocks = (UINTN) (NextLba - Lba);
+ }
+
+ return EFI_SUCCESS;
+ }
+
+ StartLba = NextLba;
+ Offset = Offset + NumBlocks * BlockLength;
+ BlockMap++;
+ }
+}
+/*++
+
+ Routine Description:
+ Modifies the current settings of the firmware volume according to the
+ input parameter, and returns the new setting of the volume
+
+ Arguments:
+ Instance - The FV instance whose attributes is going to be
+ modified
+ Attributes - On input, it is a pointer to EFI_FVB_ATTRIBUTES_2
+ containing the desired firmware volume settings.
+ On successful return, it contains the new settings
+ of the firmware volume
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all
+ instance data
+
+ Returns:
+ EFI_SUCCESS - Successfully returns
+ EFI_ACCESS_DENIED - The volume setting is locked and cannot be modified
+ EFI_INVALID_PARAMETER - Instance not found, or The attributes requested are
+ in conflict with the capabilities as declared in
+ the firmware volume header
+
+--*/
+EFI_STATUS
+FvbSetVolumeAttributes (
+ IN UINTN Instance,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes,
+ IN ESAL_FWB_GLOBAL *Global
+ )
+{
+ EFI_FW_VOL_INSTANCE *FwhInstance;
+ EFI_FVB_ATTRIBUTES_2 OldAttributes;
+ EFI_FVB_ATTRIBUTES_2 *AttribPtr;
+ UINT32 Capabilities;
+ UINT32 OldStatus;
+ UINT32 NewStatus;
+ EFI_STATUS Status;
+ EFI_FVB_ATTRIBUTES_2 UnchangedAttributes;
+
+ //
+ // Find the right instance of the FVB private data
+ //
+ Status = GetFvbInstance (Instance, Global, &FwhInstance);
+ ASSERT_EFI_ERROR (Status);
+
+ AttribPtr =
+ (EFI_FVB_ATTRIBUTES_2 *) &(FwhInstance->VolumeHeader.Attributes);
+ OldAttributes = *AttribPtr;
+ Capabilities = OldAttributes & (EFI_FVB2_READ_DISABLED_CAP | \
+ EFI_FVB2_READ_ENABLED_CAP | \
+ EFI_FVB2_WRITE_DISABLED_CAP | \
+ EFI_FVB2_WRITE_ENABLED_CAP | \
+ EFI_FVB2_LOCK_CAP \
+ );
+ OldStatus = OldAttributes & EFI_FVB2_STATUS;
+ NewStatus = *Attributes & EFI_FVB2_STATUS;
+
+ UnchangedAttributes = EFI_FVB2_READ_DISABLED_CAP | \
+ EFI_FVB2_READ_ENABLED_CAP | \
+ EFI_FVB2_WRITE_DISABLED_CAP | \
+ EFI_FVB2_WRITE_ENABLED_CAP | \
+ EFI_FVB2_LOCK_CAP | \
+ EFI_FVB2_STICKY_WRITE | \
+ EFI_FVB2_MEMORY_MAPPED | \
+ EFI_FVB2_ERASE_POLARITY | \
+ EFI_FVB2_READ_LOCK_CAP | \
+ EFI_FVB2_WRITE_LOCK_CAP | \
+ EFI_FVB2_ALIGNMENT;
+
+ //
+ // Some attributes of FV is read only can *not* be set
+ //
+ if ((OldAttributes & UnchangedAttributes) ^
+ (*Attributes & UnchangedAttributes)) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // If firmware volume is locked, no status bit can be updated
+ //
+ if (OldAttributes & EFI_FVB2_LOCK_STATUS) {
+ if (OldStatus ^ NewStatus) {
+ return EFI_ACCESS_DENIED;
+ }
+ }
+ //
+ // Test read disable
+ //
+ if ((Capabilities & EFI_FVB2_READ_DISABLED_CAP) == 0) {
+ if ((NewStatus & EFI_FVB2_READ_STATUS) == 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+ //
+ // Test read enable
+ //
+ if ((Capabilities & EFI_FVB2_READ_ENABLED_CAP) == 0) {
+ if (NewStatus & EFI_FVB2_READ_STATUS) {
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+ //
+ // Test write disable
+ //
+ if ((Capabilities & EFI_FVB2_WRITE_DISABLED_CAP) == 0) {
+ if ((NewStatus & EFI_FVB2_WRITE_STATUS) == 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+ //
+ // Test write enable
+ //
+ if ((Capabilities & EFI_FVB2_WRITE_ENABLED_CAP) == 0) {
+ if (NewStatus & EFI_FVB2_WRITE_STATUS) {
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+ //
+ // Test lock
+ //
+ if ((Capabilities & EFI_FVB2_LOCK_CAP) == 0) {
+ if (NewStatus & EFI_FVB2_LOCK_STATUS) {
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+
+ *AttribPtr = (*AttribPtr) & (0xFFFFFFFF & (~EFI_FVB2_STATUS));
+ *AttribPtr = (*AttribPtr) | NewStatus;
+ *Attributes = *AttribPtr;
+
+ return EFI_SUCCESS;
+}
+/*++
+
+ Routine Description:
+
+ Retrieves the physical address of the device.
+
+ Arguments:
+
+ This - Calling context
+ Address - Output buffer containing the address.
+
+ Returns:
+ EFI_SUCCESS - Successfully returns
+
+--*/
+EFI_STATUS
+EFIAPI
+FvbProtocolGetPhysicalAddress (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ )
+{
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
+
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);
+
+ return FvbGetPhysicalAddress (FvbDevice->Instance, Address,
+ mFvbModuleGlobal);
+}
+
+/*++
+
+ Routine Description:
+ Retrieve the size of a logical block
+
+ Arguments:
+ This - Calling context
+ Lba - Indicates which block to return the size for.
+ BlockSize - A pointer to a caller allocated UINTN in which
+ the size of the block is returned
+ NumOfBlocks - a pointer to a caller allocated UINTN in which the
+ number of consecutive blocks starting with Lba is
+ returned. All blocks in this range have a size of
+ BlockSize
+
+ Returns:
+ EFI_SUCCESS - The firmware volume was read successfully and
+ contents are in Buffer
+
+--*/
+EFI_STATUS
+EFIAPI
+FvbProtocolGetBlockSize (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ IN CONST EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumOfBlocks
+ )
+{
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
+
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);
+
+ return FvbGetLbaAddress (
+ FvbDevice->Instance,
+ Lba,
+ NULL,
+ BlockSize,
+ NumOfBlocks,
+ mFvbModuleGlobal
+ );
+}
+
+/*++
+
+ Routine Description:
+ Retrieves Volume attributes. No polarity translations are done.
+
+ Arguments:
+ This - Calling context
+ Attributes - output buffer which contains attributes
+
+ Returns:
+ EFI_SUCCESS - Successfully returns
+
+--*/
+EFI_STATUS
+EFIAPI
+FvbProtocolGetAttributes (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
+
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);
+
+ return FvbGetVolumeAttributes (FvbDevice->Instance, Attributes,
+ mFvbModuleGlobal);
+}
+
+/*++
+
+ Routine Description:
+ Sets Volume attributes. No polarity translations are done.
+
+ Arguments:
+ This - Calling context
+ Attributes - output buffer which contains attributes
+
+ Returns:
+ EFI_SUCCESS - Successfully returns
+
+--*/
+EFI_STATUS
+EFIAPI
+FvbProtocolSetAttributes (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
+
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);
+
+ return FvbSetVolumeAttributes (FvbDevice->Instance, Attributes,
+ mFvbModuleGlobal);
+}
+
+/*++
+
+ Routine Description:
+
+ The EraseBlock() function erases one or more blocks as denoted by the
+ variable argument list. The entire parameter list of blocks must be
+ verified prior to erasing any blocks. If a block is requested that does
+ not exist within the associated firmware volume (it has a larger index than
+ the last block of the firmware volume), the EraseBlock() function must
+ return EFI_INVALID_PARAMETER without modifying the contents of the firmware
+ volume.
+
+ Arguments:
+ This - Calling context
+ ... - Starting LBA followed by Number of Lba to erase.
+ a -1 to terminate the list.
+
+ Returns:
+ EFI_SUCCESS - The erase request was successfully completed
+ EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state
+ EFI_DEVICE_ERROR - The block device is not functioning correctly and
+ could not be written. Firmware device may have been
+ partially erased
+
+--*/
+EFI_STATUS
+EFIAPI
+FvbProtocolEraseBlocks (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ ...
+ )
+{
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
+ EFI_FW_VOL_INSTANCE *FwhInstance;
+ UINTN NumOfBlocks;
+ VA_LIST args;
+ EFI_LBA StartingLba;
+ UINTN NumOfLba;
+ EFI_STATUS Status;
+
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);
+
+ Status = GetFvbInstance (FvbDevice->Instance, mFvbModuleGlobal,
+ &FwhInstance);
+ ASSERT_EFI_ERROR (Status);
+
+ NumOfBlocks = FwhInstance->NumOfBlocks;
+
+ VA_START (args, This);
+
+ do {
+ StartingLba = VA_ARG (args, EFI_LBA);
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ break;
+ }
+
+ NumOfLba = VA_ARG (args, UINT32);
+
+ //
+ // Check input parameters
+ //
+ if ((NumOfLba == 0) || ((StartingLba + NumOfLba) > NumOfBlocks)) {
+ VA_END (args);
+ return EFI_INVALID_PARAMETER;
+ }
+ } while (1);
+
+ VA_END (args);
+
+ VA_START (args, This);
+ do {
+ StartingLba = VA_ARG (args, EFI_LBA);
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ break;
+ }
+
+ NumOfLba = VA_ARG (args, UINT32);
+
+ while (NumOfLba > 0) {
+ Status = RamFlashEraseBlock (StartingLba);
+ if (EFI_ERROR (Status)) {
+ VA_END (args);
+ return Status;
+ }
+
+ StartingLba++;
+ NumOfLba--;
+ }
+
+ } while (1);
+
+ VA_END (args);
+
+ return EFI_SUCCESS;
+}
+
+/*++
+
+ Routine Description:
+
+ Writes data beginning at Lba:Offset from FV. The write terminates either
+ when *NumBytes of data have been written, or when a block boundary is
+ reached. *NumBytes is updated to reflect the actual number of bytes
+ written. The write opertion does not include erase. This routine will
+ attempt to write only the specified bytes. If the writes do not stick,
+ it will return an error.
+
+ Arguments:
+ This - Calling context
+ Lba - Block in which to begin write
+ Offset - Offset in the block at which to begin write
+ NumBytes - On input, indicates the requested write size. On
+ output, indicates the actual number of bytes
+ written
+ Buffer - Buffer containing source data for the write.
+
+ Returns:
+ EFI_SUCCESS - The firmware volume was written successfully
+ EFI_BAD_BUFFER_SIZE - Write attempted across a LBA boundary. On output,
+ NumBytes contains the total number of bytes
+ actually written
+ EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state
+ EFI_DEVICE_ERROR - The block device is not functioning correctly and
+ could not be written
+ EFI_INVALID_PARAMETER - NumBytes or Buffer are NULL
+
+--*/
+EFI_STATUS
+EFIAPI
+FvbProtocolWrite (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ return RamFlashWrite (Lba, Offset, NumBytes, Buffer);
+}
+
+/*++
+
+ Routine Description:
+
+ Reads data beginning at Lba:Offset from FV. The Read terminates either
+ when *NumBytes of data have been read, or when a block boundary is
+ reached. *NumBytes is updated to reflect the actual number of bytes
+ written. The write opertion does not include erase. This routine will
+ attempt to write only the specified bytes. If the writes do not stick,
+ it will return an error.
+
+ Arguments:
+ This - Calling context
+ Lba - Block in which to begin Read
+ Offset - Offset in the block at which to begin Read
+ NumBytes - On input, indicates the requested write size. On
+ output, indicates the actual number of bytes Read
+ Buffer - Buffer containing source data for the Read.
+
+ Returns:
+ EFI_SUCCESS - The firmware volume was read successfully and
+ contents are in Buffer
+ EFI_BAD_BUFFER_SIZE - Read attempted across a LBA boundary. On output,
+ NumBytes contains the total number of bytes
+ returned in Buffer
+ EFI_ACCESS_DENIED - The firmware volume is in the ReadDisabled state
+ EFI_DEVICE_ERROR - The block device is not functioning correctly and
+ could not be read
+ EFI_INVALID_PARAMETER - NumBytes or Buffer are NULL
+
+--*/
+EFI_STATUS
+EFIAPI
+FvbProtocolRead (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,
+ IN CONST EFI_LBA Lba,
+ IN CONST UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ return RamFlashRead (Lba, Offset, NumBytes, Buffer);
+}
+
+/*++
+
+ Routine Description:
+ Check the integrity of firmware volume header
+
+ Arguments:
+ FwVolHeader - A pointer to a firmware volume header
+
+ Returns:
+ EFI_SUCCESS - The firmware volume is consistent
+ EFI_NOT_FOUND - The firmware volume has corrupted. So it is not an
+ FV
+
+--*/
+EFI_STATUS
+ValidateFvHeader (
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader
+ )
+{
+ UINT16 Checksum;
+
+ //
+ // Verify the header revision, header signature, length
+ // Length of FvBlock cannot be 2**64-1
+ // HeaderLength cannot be an odd number
+ //
+ if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||
+ (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
+ (FwVolHeader->FvLength == ((UINTN) -1)) ||
+ ((FwVolHeader->HeaderLength & 0x01) != 0)
+ ) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Verify the header checksum
+ //
+
+ Checksum = CalculateSum16 ((UINT16 *) FwVolHeader,
+ FwVolHeader->HeaderLength);
+ if (Checksum != 0) {
+ UINT16 Expected;
+
+ Expected =
+ (UINT16) (((UINTN) FwVolHeader->Checksum + 0x10000 - Checksum) & 0xffff);
+
+ DEBUG ((DEBUG_INFO, "FV@%p Checksum is 0x%x, expected 0x%x\n",
+ FwVolHeader, FwVolHeader->Checksum, Expected));
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+MarkMemoryRangeForRuntimeAccess (
+ EFI_PHYSICAL_ADDRESS BaseAddress,
+ UINTN Length
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Mark flash region as runtime memory
+ //
+ Status = gDS->RemoveMemorySpace (
+ BaseAddress,
+ Length
+ );
+
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeSystemMemory,
+ BaseAddress,
+ Length,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->AllocatePages (
+ AllocateAddress,
+ EfiRuntimeServicesData,
+ EFI_SIZE_TO_PAGES (Length),
+ &BaseAddress
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+InitializeVariableFvHeader (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME_HEADER *GoodFwVolHeader;
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
+ UINTN Length;
+ UINTN WriteLength;
+ UINTN BlockSize;
+
+ FwVolHeader =
+ (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN)
+ PcdGet32 (PcdPlatformFlashNvStorageVariableBase);
+
+ Length =
+ (FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize));
+
+ BlockSize = PcdGet32 (PcdVariableFdBlockSize);
+
+ Status = ValidateFvHeader (FwVolHeader);
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "ValidateFvHeader() return ok\n"));
+ if (FwVolHeader->FvLength != Length ||
+ FwVolHeader->BlockMap[0].Length != BlockSize) {
+ Status = EFI_VOLUME_CORRUPTED;
+ DEBUG ((DEBUG_INFO, "FwVolHeader->FvLength(%x) != Length(%x) || FwVolHeader->BlockMap[0].Length(%x) != BlockSize(%x)\n", FwVolHeader->FvLength, Length, FwVolHeader->BlockMap[0].Length, BlockSize));
+ }
+ }
+ else {
+ DEBUG ((DEBUG_INFO, "ValidateFvHeader() return failed\n"));
+ }
+ if (EFI_ERROR (Status)) {
+ UINTN Offset;
+ UINTN Start;
+
+ DEBUG ((DEBUG_INFO,
+ "Variable FV header is not valid. It will be reinitialized.\n"));
+
+ //
+ // Get FvbInfo to provide in FwhInstance.
+ //
+ Status = GetFvbInfo (Length, &GoodFwVolHeader);
+ ASSERT (!EFI_ERROR (Status));
+
+ Start = (UINTN)(UINT8*) FwVolHeader - PcdGet32 (PcdVariableFdBaseAddress);
+ ASSERT (Start % BlockSize == 0 && Length % BlockSize == 0);
+ ASSERT (GoodFwVolHeader->HeaderLength <= BlockSize);
+
+ //
+ // Erase all the blocks
+ //
+ for (Offset = Start; Offset < Start + Length; Offset += BlockSize) {
+ Status = RamFlashEraseBlock (Offset / BlockSize);
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ //
+ // Write good FV header
+ //
+ WriteLength = GoodFwVolHeader->HeaderLength;
+ Status = RamFlashWrite (
+ Start / BlockSize,
+ 0,
+ &WriteLength,
+ (UINT8 *) GoodFwVolHeader);
+ ASSERT_EFI_ERROR (Status);
+ ASSERT (WriteLength == GoodFwVolHeader->HeaderLength);
+ }
+
+ return Status;
+}
+
+/*++
+
+ Routine Description:
+ This function does common initialization for FVB services
+
+ Arguments:
+
+ Returns:
+
+--*/
+EFI_STATUS
+EFIAPI
+FvbInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_FW_VOL_INSTANCE *FwhInstance;
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
+ UINT32 BufferSize;
+ EFI_FV_BLOCK_MAP_ENTRY *PtrBlockMapEntry;
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;
+ UINT32 MaxLbaSize;
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINTN Length;
+ UINTN NumOfBlocks;
+
+ if (EFI_ERROR (RamFlashInitialize ())) {
+ //
+ // Return an error so image will be unloaded
+ //
+ DEBUG ((DEBUG_INFO,
+ "RAM flash was not detected. Writable FVB is not being installed.\n"));
+ return EFI_WRITE_PROTECTED;
+ }
+
+ //
+ // Allocate runtime services data for global variable, which contains
+ // the private data of all firmware volume block instances
+ //
+ mFvbModuleGlobal = AllocateRuntimePool (sizeof (ESAL_FWB_GLOBAL));
+ ASSERT (mFvbModuleGlobal != NULL);
+
+ BaseAddress = (UINTN) PcdGet32 (PcdVariableFdBaseAddress);
+ Length = PcdGet32 (PcdVariableFdSize);
+ DEBUG ((DEBUG_INFO, "FvbInitialize(): BaseAddress: 0x%lx Length:0x%x\n", BaseAddress, Length));
+ Status = InitializeVariableFvHeader ();
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO,
+ "RAM Flash: Unable to initialize variable FV header\n"));
+ return EFI_WRITE_PROTECTED;
+ }
+
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) BaseAddress;
+ Status = ValidateFvHeader (FwVolHeader);
+ if (EFI_ERROR (Status)) {
+ //
+ // Get FvbInfo
+ //
+ DEBUG ((DEBUG_INFO, "FvbInitialize(): ValidateFvHeader() return error(%r)\n", Status));
+
+ Status = GetFvbInfo (Length, &FwVolHeader);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, "FvbInitialize(): GetFvbInfo (Length, &FwVolHeader) return error(%r)\n", Status));
+ return EFI_WRITE_PROTECTED;
+ }
+ }
+
+ BufferSize = (sizeof (EFI_FW_VOL_INSTANCE) +
+ FwVolHeader->HeaderLength -
+ sizeof (EFI_FIRMWARE_VOLUME_HEADER)
+ );
+ mFvbModuleGlobal->FvInstance = AllocateRuntimePool (BufferSize);
+ ASSERT (mFvbModuleGlobal->FvInstance != NULL);
+
+ FwhInstance = mFvbModuleGlobal->FvInstance;
+
+ mFvbModuleGlobal->NumFv = 0;
+ MaxLbaSize = 0;
+
+ FwVolHeader =
+ (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN)
+ PcdGet32 (PcdPlatformFlashNvStorageVariableBase);
+
+ FwhInstance->FvBase = (UINTN) BaseAddress;
+
+ CopyMem ((UINTN *) &(FwhInstance->VolumeHeader), (UINTN *) FwVolHeader,
+ FwVolHeader->HeaderLength);
+ FwVolHeader = &(FwhInstance->VolumeHeader);
+
+ NumOfBlocks = 0;
+
+ for (PtrBlockMapEntry = FwVolHeader->BlockMap;
+ PtrBlockMapEntry->NumBlocks != 0;
+ PtrBlockMapEntry++) {
+ //
+ // Get the maximum size of a block.
+ //
+ if (MaxLbaSize < PtrBlockMapEntry->Length) {
+ MaxLbaSize = PtrBlockMapEntry->Length;
+ }
+
+ NumOfBlocks = NumOfBlocks + PtrBlockMapEntry->NumBlocks;
+ }
+
+ //
+ // The total number of blocks in the FV.
+ //
+ FwhInstance->NumOfBlocks = NumOfBlocks;
+
+ //
+ // Add a FVB Protocol Instance
+ //
+ FvbDevice = AllocateRuntimePool (sizeof (EFI_FW_VOL_BLOCK_DEVICE));
+ ASSERT (FvbDevice != NULL);
+
+ CopyMem (FvbDevice, &mFvbDeviceTemplate, sizeof (EFI_FW_VOL_BLOCK_DEVICE));
+
+ FvbDevice->Instance = mFvbModuleGlobal->NumFv;
+ mFvbModuleGlobal->NumFv++;
+
+ //
+ // Set up the devicepath
+ //
+ if (FwVolHeader->ExtHeaderOffset == 0) {
+ FV_MEMMAP_DEVICE_PATH *FvMemmapDevicePath;
+
+ //
+ // FV does not contains extension header, then produce MEMMAP_DEVICE_PATH
+ //
+ FvMemmapDevicePath = AllocateCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH),
+ &mFvMemmapDevicePathTemplate);
+ FvMemmapDevicePath->MemMapDevPath.StartingAddress = BaseAddress;
+ FvMemmapDevicePath->MemMapDevPath.EndingAddress =
+ BaseAddress + FwVolHeader->FvLength - 1;
+ FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)FvMemmapDevicePath;
+ } else {
+ FV_PIWG_DEVICE_PATH *FvPiwgDevicePath;
+
+ FvPiwgDevicePath = AllocateCopyPool (sizeof (FV_PIWG_DEVICE_PATH),
+ &mFvPIWGDevicePathTemplate);
+ CopyGuid (
+ &FvPiwgDevicePath->FvDevPath.FvName,
+ (GUID *)(UINTN)(BaseAddress + FwVolHeader->ExtHeaderOffset)
+ );
+ FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)FvPiwgDevicePath;
+ }
+
+ //
+ // Module type specific hook.
+ //
+ InstallProtocolInterfaces (FvbDevice);
+
+ MarkMemoryRangeForRuntimeAccess (BaseAddress, Length);
+
+ //
+ // Set several PCD values to point to flash
+ //
+ PcdSet64 (
+ PcdFlashNvStorageVariableBase64,
+ (UINTN) PcdGet32 (PcdPlatformFlashNvStorageVariableBase)
+ );
+ PcdSet32 (
+ PcdFlashNvStorageFtwWorkingBase,
+ PcdGet32 (PcdPlatformFlashNvStorageFtwWorkingBase)
+ );
+ PcdSet32 (
+ PcdFlashNvStorageFtwSpareBase,
+ PcdGet32 (PcdPlatformFlashNvStorageFtwSpareBase)
+ );
+
+ FwhInstance = (EFI_FW_VOL_INSTANCE *)
+ (
+ (UINTN) FwhInstance + FwVolHeader->HeaderLength +
+ (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER))
+ );
+
+ //
+ // Module type specific hook.
+ //
+ InstallVirtualAddressChangeHandler ();
+ return EFI_SUCCESS;
+}
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c
new file mode 100644
index 0000000..ccf8111
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c
@@ -0,0 +1,150 @@
+/**@file
+ Functions related to the Firmware Volume Block service whose
+ implementation is specific to the runtime DXE driver build.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (C) 2015, Red Hat, Inc.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Guid/EventGroup.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+#include "FwBlockService.h"
+#include "RamFlash.h"
+
+VOID
+InstallProtocolInterfaces (
+ IN EFI_FW_VOL_BLOCK_DEVICE *FvbDevice
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE FwbHandle;
+ EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *OldFwbInterface;
+
+ //
+ // Find a handle with a matching device path that has supports FW Block
+ // protocol
+ //
+ Status = gBS->LocateDevicePath (&gEfiFirmwareVolumeBlockProtocolGuid,
+ &FvbDevice->DevicePath, &FwbHandle);
+ if (EFI_ERROR (Status)) {
+ //
+ // LocateDevicePath fails so install a new interface and device path
+ //
+ FwbHandle = NULL;
+ DEBUG ((DEBUG_INFO, "Installing RAM FVB\n"));
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &FwbHandle,
+ &gEfiFirmwareVolumeBlockProtocolGuid,
+ &FvbDevice->FwVolBlockInstance,
+ &gEfiDevicePathProtocolGuid,
+ FvbDevice->DevicePath,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ } else if (IsDevicePathEnd (FvbDevice->DevicePath)) {
+ //
+ // Device already exists, so reinstall the FVB protocol
+ //
+ Status = gBS->HandleProtocol (
+ FwbHandle,
+ &gEfiFirmwareVolumeBlockProtocolGuid,
+ (VOID**)&OldFwbInterface
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "Reinstalling FVB for Ram flash region\n"));
+ Status = gBS->ReinstallProtocolInterface (
+ FwbHandle,
+ &gEfiFirmwareVolumeBlockProtocolGuid,
+ OldFwbInterface,
+ &FvbDevice->FwVolBlockInstance
+ );
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ //
+ // There was a FVB protocol on an End Device Path node
+ //
+ ASSERT (FALSE);
+ }
+}
+
+/*++
+
+ Routine Description:
+
+ Fixup internal data so that EFI and SAL can be call in virtual mode.
+ Call the passed in Child Notify event and convert the mFvbModuleGlobal
+ date items to there virtual address.
+
+ Arguments:
+
+ (Standard EFI notify event - EFI_EVENT_NOTIFY)
+
+ Returns:
+
+ None
+
+--*/
+STATIC
+VOID
+EFIAPI
+FvbVirtualAddressChangeEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_FW_VOL_INSTANCE *FwhInstance;
+ UINTN Index;
+
+ FwhInstance = mFvbModuleGlobal->FvInstance;
+ EfiConvertPointer (0x0, (VOID **) &mFvbModuleGlobal->FvInstance);
+
+ //
+ // Convert the base address of all the instances
+ //
+ Index = 0;
+ while (Index < mFvbModuleGlobal->NumFv) {
+ EfiConvertPointer (0x0, (VOID **) &FwhInstance->FvBase);
+ FwhInstance = (EFI_FW_VOL_INSTANCE *)
+ (
+ (UINTN)FwhInstance +
+ FwhInstance->VolumeHeader.HeaderLength +
+ (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER))
+ );
+ Index++;
+ }
+
+ EfiConvertPointer (0x0, (VOID **) &mFvbModuleGlobal);
+ RamFlashConvertPointers ();
+}
+
+
+VOID
+InstallVirtualAddressChangeHandler (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT VirtualAddressChangeEvent;
+
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ FvbVirtualAddressChangeEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &VirtualAddressChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+}
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c
new file mode 100644
index 0000000..3c9cc9d
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c
@@ -0,0 +1,145 @@
+/** @file
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include "RamFlash.h"
+
+VOID *mFlashBase;
+
+STATIC UINTN mFdBlockSize = 0;
+STATIC UINTN mFdBlockCount = 0;
+
+STATIC
+UINT8*
+RamFlashPtr (
+ IN EFI_LBA Lba,
+ IN UINTN Offset
+ )
+{
+ return mFlashBase + ((UINTN)Lba * mFdBlockSize) + Offset;
+}
+
+/**
+ Read from Ram Flash
+
+ @param[in] Lba The starting logical block index to read from.
+ @param[in] Offset Offset into the block at which to begin reading.
+ @param[in] NumBytes On input, indicates the requested read size. On
+ output, indicates the actual number of bytes read
+ @param[in] Buffer Pointer to the buffer to read into.
+
+**/
+EFI_STATUS
+RamFlashRead (
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ UINT8 *Ptr;
+
+ //
+ // Only write to the first 64k. We don't bother saving the FTW Spare
+ // block into the flash memory.
+ //
+ if (Lba >= mFdBlockCount) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Get flash address
+ //
+ Ptr = (UINT8*) RamFlashPtr (Lba, Offset);
+
+ CopyMem (Buffer, Ptr, *NumBytes);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Write to Ram Flash
+
+ @param[in] Lba The starting logical block index to write to.
+ @param[in] Offset Offset into the block at which to begin writing.
+ @param[in] NumBytes On input, indicates the requested write size. On
+ output, indicates the actual number of bytes written
+ @param[in] Buffer Pointer to the data to write.
+
+**/
+EFI_STATUS
+RamFlashWrite (
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ UINT8 *Ptr;
+ UINTN i;
+
+ //
+ // Only write to the first 64k. We don't bother saving the FTW Spare
+ // block into the flash memory.
+ //
+ if (Lba >= mFdBlockCount) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Program flash
+ //
+ Ptr = RamFlashPtr (Lba, Offset);
+ for (i = 0; i < *NumBytes; i++) {
+ MmioWrite8((UINTN)Ptr, Buffer[i]);
+ Ptr ++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Erase a Ram Flash block
+
+ @param Lba The logical block index to erase.
+
+**/
+EFI_STATUS
+RamFlashEraseBlock (
+ IN EFI_LBA Lba
+ )
+{
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Initializes Ram flash memory support
+
+ @retval EFI_WRITE_PROTECTED The Ram flash device is not present.
+ @retval EFI_SUCCESS The Ram flash device is supported.
+
+**/
+EFI_STATUS
+RamFlashInitialize (
+ VOID
+ )
+{
+ mFlashBase = (UINT8*)(UINTN) PcdGet32 (PcdVariableFdBaseAddress);
+ mFdBlockSize = PcdGet32 (PcdVariableFdBlockSize);
+ ASSERT(PcdGet32 (PcdVariableFdSize) % mFdBlockSize == 0);
+ mFdBlockCount = PcdGet32 (PcdVariableFdSize) / mFdBlockSize;
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c
new file mode 100644
index 0000000..a9d4863
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c
@@ -0,0 +1,20 @@
+/** @file
+ Ram flash device for EFI variable
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/UefiRuntimeLib.h>
+
+#include "RamFlash.h"
+
+VOID
+RamFlashConvertPointers (
+ VOID
+ )
+{
+ EfiConvertPointer (0x0, (VOID **) &mFlashBase);
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 08/18] U5SeriesPkg/RiscVPlatformTimerLib: Platform Timer library
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (6 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 07/18] U5SeriesPkg/RamFvbServicesRuntimeDxe: Firmware Volume Block service Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 09/18] U5SeriesPkg/SerialIoLib: Platform Serial Port library Abner Chang
` (10 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
Timer library used to access to machine mode timer Control Status Registers
for U5 series platforms.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RiscVPlatformTimerLib.inf | 36 ++++++++++++++++
Platform/SiFive/U5SeriesPkg/Include/U5Clint.h | 20 +++++++++
.../RiscVPlatformTimerLib/RiscVPlatformTimerLib.S | 48 ++++++++++++++++++++++
3 files changed, 104 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/Include/U5Clint.h
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S
diff --git a/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
new file mode 100644
index 0000000..777ec98
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
@@ -0,0 +1,36 @@
+## @file
+# RISC-V CPU lib to override timer mechanism for U5 series platform.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformTimerLib
+ FILE_GUID = AFA75BBD-DE9D-4E77-BD88-1EA401BE931D
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformTimerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ RiscVPlatformTimerLib.S
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+
+
diff --git a/Platform/SiFive/U5SeriesPkg/Include/U5Clint.h b/Platform/SiFive/U5SeriesPkg/Include/U5Clint.h
new file mode 100644
index 0000000..26260dc
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Include/U5Clint.h
@@ -0,0 +1,20 @@
+/** @file
+ RISC-V Timer Architectural definition for U500 platform.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef U5_CLINT_H_
+#define U5_CLINT_H_
+
+#define CLINT_REG_BASE_ADDR 0x02000000
+ #define CLINT_REG_MTIME 0x0200BFF8
+ #define CLINT_REG_MTIMECMP0 0x02004000
+ #define CLINT_REG_MTIMECMP1 0x02004008
+ #define CLINT_REG_MTIMECMP2 0x02004010
+ #define CLINT_REG_MTIMECMP3 0x02004018
+ #define CLINT_REG_MTIMECMP4 0x02004020
+
+#endif
diff --git a/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S
new file mode 100644
index 0000000..a49149e
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S
@@ -0,0 +1,48 @@
+//------------------------------------------------------------------------------
+//
+// SiFive U5 Series Timer CSR functions.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+#include <RiscVImpl.h>
+#include <U5Clint.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVReadMachineTimer)
+.global ASM_PFX(RiscVSetMachineTimerCmp)
+.global ASM_PFX(RiscVReadMachineTimerCmp)
+
+//
+// Read machine timer CSR.
+// @retval a0 : 64-bit machine timer.
+//
+ASM_PFX (RiscVReadMachineTimer):
+ li t1, CLINT_REG_MTIME
+ ld a0, (t1)
+ ret
+
+//
+// Set machine timer compare CSR.
+// @param a0 : UINT64
+//
+ASM_PFX (RiscVSetMachineTimerCmp):
+ li t1, CLINT_REG_MTIMECMP0
+ sd a0, (t1)
+ ret
+
+//
+// Read machine timer compare CSR.
+// @param a0 : UINT64
+//
+ASM_PFX (RiscVReadMachineTimerCmp):
+ li t1, CLINT_REG_MTIMECMP0
+ ld a0, (t1)
+ ret
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 09/18] U5SeriesPkg/SerialIoLib: Platform Serial Port library
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (7 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 08/18] U5SeriesPkg/RiscVPlatformTimerLib: Platform Timer library Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-11-19 15:30 ` [edk2-devel] " Mark Salter
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 10/18] FreedomU540HiFiveUnleashedBoard/PlatformPei:Platform PEI Abner Chang
` (9 subsequent siblings)
18 siblings, 1 reply; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
Serial Port library for U5 series platform.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../Library/SerialIoLib/SerialIoLib.inf | 38 ++++
.../Library/SerialIoLib/SerialPortLib.c | 253 +++++++++++++++++++++
.../Library/SerialIoLib/U5SerialPortLib.uni | 16 ++
3 files changed, 307 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/U5SerialPortLib.uni
diff --git a/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf
new file mode 100644
index 0000000..0044f84
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Library instance for SerialIo library class
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = U5SerialPortLib
+ MODULE_UNI_FILE = U5SerialPortLib.uni
+ FILE_GUID = FCC4FD2B-2FF6-4FFA-B363-7C1111E5DCE9
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+ RiscVPkg/RiscVPkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ RiscVOpensbiLib
+
+[FixedPcd]
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
+
+[Sources]
+ SerialPortLib.c
diff --git a/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
new file mode 100644
index 0000000..5e06515
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
@@ -0,0 +1,253 @@
+/** @file
+ UART Serial Port library functions
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/IoLib.h>
+#include <Library/SerialPortLib.h>
+#include <include/sbi_utils/serial/sifive-uart.h> // Reference to header file in opensbi
+
+//---------------------------------------------
+// UART Register Offsets
+//---------------------------------------------
+
+#define UART_REG_IP 5
+#define UART_IP_RXWM 0x02
+
+//---------------------------------------------
+// UART Settings
+//---------------------------------------------
+
+#define UART_BAUDRATE 115200
+#define SYS_CLK 100000000
+
+BOOLEAN Initiated = FALSE;
+
+/**
+ Initialize the serial device hardware.
+
+ If no initialization is required, then return RETURN_SUCCESS.
+ If the serial device was successfuly initialized, then return RETURN_SUCCESS.
+ If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+ @retval RETURN_SUCCESS The serial device was initialized.
+ @retval RETURN_DEVICE_ERROR The serail device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ if (Initiated) {
+ return RETURN_SUCCESS;
+ }
+ if (sifive_uart_init(FixedPcdGet32(PcdU5UartBase), SYS_CLK / 2, UART_BAUDRATE) != 0) {
+ return EFI_DEVICE_ERROR;
+ }
+ Initiated = TRUE;
+ return RETURN_SUCCESS;
+}
+
+/**
+ Write data from buffer to serial device.
+
+ Writes NumberOfBytes data bytes from Buffer to the serial device.
+ The number of bytes actually written to the serial device is returned.
+ If the return value is less than NumberOfBytes, then the write operation failed.
+
+ If Buffer is NULL, then ASSERT().
+
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer Pointer to the data buffer to be written.
+ @param NumberOfBytes Number of bytes to written to the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes written to the serial device.
+ If this value is less than NumberOfBytes, then the write operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINTN Index;
+
+ if (Buffer == NULL || Initiated == FALSE) {
+ return 0;
+ }
+
+ for(Index = 0; Index < NumberOfBytes; Index ++) {
+ sifive_uart_putc (Buffer [Index]);
+ }
+
+ return Index;
+}
+
+/**
+ Reads data from a serial device into a buffer.
+
+ @param Buffer Pointer to the data buffer to store the data read from the serial device.
+ @param NumberOfBytes Number of bytes to read from the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes read from the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINTN Index;
+
+ if (NULL == Buffer || Initiated == FALSE) {
+ return 0;
+ }
+
+ for(Index = 0; Index < NumberOfBytes; Index ++) {
+ Buffer [Index] = (UINT8)sifive_uart_getc ();
+ }
+
+ return Index;
+}
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+
+ Polls aserial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ STATIC volatile UINT32 * const uart = (UINT32 *)FixedPcdGet32(PcdU5UartBase);
+ UINT32 IP;
+
+ if (Initiated == FALSE) {
+ return FALSE;
+ }
+ IP = MmioRead32 ((UINTN)(uart + UART_REG_IP));
+ if(IP & UART_IP_RXWM) {
+ return TRUE;
+ }
+ else {
+ return FALSE;
+ }
+}
+
+/**
+ Sets the control bits on a serial device.
+
+ @param Control Sets the bits of Control that are settable.
+
+ @retval RETURN_SUCCESS The new control bits were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ if (Initiated == FALSE) {
+ return EFI_NOT_READY;
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Retrieve the status of the control bits on a serial device.
+
+ @param Control A pointer to return the current control signals from the serial device.
+
+ @retval RETURN_SUCCESS The control bits were read from the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+ if (Initiated == FALSE) {
+ return EFI_NOT_READY;
+ }
+ *Control = 0;
+ return RETURN_SUCCESS;
+}
+
+/**
+ Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
+ data bits, and stop bits on a serial device.
+
+ @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
+ device's default interface speed.
+ On output, the value actually set.
+ @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
+ serial interface. A ReceiveFifoDepth value of 0 will use
+ the device's default FIFO depth.
+ On output, the value actually set.
+ @param Timeout The requested time out for a single character in microseconds.
+ This timeout applies to both the transmit and receive side of the
+ interface. A Timeout value of 0 will use the device's default time
+ out value.
+ On output, the value actually set.
+ @param Parity The type of parity to use on this serial device. A Parity value of
+ DefaultParity will use the device's default parity value.
+ On output, the value actually set.
+ @param DataBits The number of data bits to use on the serial device. A DataBits
+ vaule of 0 will use the device's default data bit setting.
+ On output, the value actually set.
+ @param StopBits The number of stop bits to use on this serial device. A StopBits
+ value of DefaultStopBits will use the device's default number of
+ stop bits.
+ On output, the value actually set.
+
+ @retval RETURN_SUCCESS The new attributes were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ if (Initiated == FALSE) {
+ return EFI_NOT_READY;
+ }
+ return RETURN_SUCCESS;
+}
diff --git a/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/U5SerialPortLib.uni b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/U5SerialPortLib.uni
new file mode 100644
index 0000000..49163bd
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/U5SerialPortLib.uni
@@ -0,0 +1,16 @@
+// /** @file
+// Library instance for SerialIo library class
+//
+// Library instance for SerialIO library class.
+//
+// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Library instance for SerialIO library class"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Library instance for SerialIO library class."
+
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [edk2-devel] [platform/devel-riscv-v2 PATCHv5 09/18] U5SeriesPkg/SerialIoLib: Platform Serial Port library
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 09/18] U5SeriesPkg/SerialIoLib: Platform Serial Port library Abner Chang
@ 2019-11-19 15:30 ` Mark Salter
0 siblings, 0 replies; 23+ messages in thread
From: Mark Salter @ 2019-11-19 15:30 UTC (permalink / raw)
To: devel, abner.chang
Cc: Michael D Kinney, Ard Biesheuvel, Leif Lindholm, Gilbert Chen,
Palmer Dabbelt
On Mon, 2019-10-28 at 12:20 +0800, Abner Chang wrote:
> Serial Port library for U5 series platform.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../Library/SerialIoLib/SerialIoLib.inf | 38 ++++
> .../Library/SerialIoLib/SerialPortLib.c | 253 +++++++++++++++++++++
> .../Library/SerialIoLib/U5SerialPortLib.uni | 16 ++
> 3 files changed, 307 insertions(+)
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/U5SerialPortLib.uni
>
> diff --git a/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf
> new file mode 100644
> index 0000000..0044f84
> --- /dev/null
> +++ b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf
> @@ -0,0 +1,38 @@
> +## @file
> +# Library instance for SerialIo library class
> +#
> +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = U5SerialPortLib
> + MODULE_UNI_FILE = U5SerialPortLib.uni
> + FILE_GUID = FCC4FD2B-2FF6-4FFA-B363-7C1111E5DCE9
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SerialPortLib
> +#
> +# The following information is for reference only and not required by the build tools.
> +#
> +# VALID_ARCHITECTURES = RISCV64
> +#
> +[Packages]
> + MdePkg/MdePkg.dec
> + RiscVPlatformPkg/RiscVPlatformPkg.dec
> + RiscVPkg/RiscVPkg.dec
> + Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + IoLib
> + RiscVOpensbiLib
> +
> +[FixedPcd]
> + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
> +
> +[Sources]
> + SerialPortLib.c
> diff --git a/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
> new file mode 100644
> index 0000000..5e06515
> --- /dev/null
> +++ b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
> @@ -0,0 +1,253 @@
> +/** @file
> + UART Serial Port library functions
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/IoLib.h>
> +#include <Library/SerialPortLib.h>
> +#include <include/sbi_utils/serial/sifive-uart.h> // Reference to header file in opensbi
> +
> +//---------------------------------------------
> +// UART Register Offsets
> +//---------------------------------------------
> +
> +#define UART_REG_IP 5
> +#define UART_IP_RXWM 0x02
> +
> +//---------------------------------------------
> +// UART Settings
> +//---------------------------------------------
> +
> +#define UART_BAUDRATE 115200
> +#define SYS_CLK 100000000
^^^^^^^^^^
This should be 1000000000
1GHz, not 100MHz
> +
> +BOOLEAN Initiated = FALSE;
> +
> +/**
> + Initialize the serial device hardware.
> +
> + If no initialization is required, then return RETURN_SUCCESS.
> + If the serial device was successfuly initialized, then return RETURN_SUCCESS.
> + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
> +
> + @retval RETURN_SUCCESS The serial device was initialized.
> + @retval RETURN_DEVICE_ERROR The serail device could not be initialized.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortInitialize (
> + VOID
> + )
> +{
> + if (Initiated) {
> + return RETURN_SUCCESS;
> + }
> + if (sifive_uart_init(FixedPcdGet32(PcdU5UartBase), SYS_CLK / 2, UART_BAUDRATE) != 0) {
> + return EFI_DEVICE_ERROR;
> + }
> + Initiated = TRUE;
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Write data from buffer to serial device.
> +
> + Writes NumberOfBytes data bytes from Buffer to the serial device.
> + The number of bytes actually written to the serial device is returned.
> + If the return value is less than NumberOfBytes, then the write operation failed.
> +
> + If Buffer is NULL, then ASSERT().
> +
> + If NumberOfBytes is zero, then return 0.
> +
> + @param Buffer Pointer to the data buffer to be written.
> + @param NumberOfBytes Number of bytes to written to the serial device.
> +
> + @retval 0 NumberOfBytes is 0.
> + @retval >0 The number of bytes written to the serial device.
> + If this value is less than NumberOfBytes, then the write operation failed.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortWrite (
> + IN UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> + )
> +{
> + UINTN Index;
> +
> + if (Buffer == NULL || Initiated == FALSE) {
> + return 0;
> + }
> +
> + for(Index = 0; Index < NumberOfBytes; Index ++) {
> + sifive_uart_putc (Buffer [Index]);
> + }
> +
> + return Index;
> +}
> +
> +/**
> + Reads data from a serial device into a buffer.
> +
> + @param Buffer Pointer to the data buffer to store the data read from the serial device.
> + @param NumberOfBytes Number of bytes to read from the serial device.
> +
> + @retval 0 NumberOfBytes is 0.
> + @retval >0 The number of bytes read from the serial device.
> + If this value is less than NumberOfBytes, then the read operation failed.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortRead (
> + OUT UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> + )
> +{
> + UINTN Index;
> +
> + if (NULL == Buffer || Initiated == FALSE) {
> + return 0;
> + }
> +
> + for(Index = 0; Index < NumberOfBytes; Index ++) {
> + Buffer [Index] = (UINT8)sifive_uart_getc ();
> + }
> +
> + return Index;
> +}
> +
> +/**
> + Polls a serial device to see if there is any data waiting to be read.
> +
> + Polls aserial device to see if there is any data waiting to be read.
> + If there is data waiting to be read from the serial device, then TRUE is returned.
> + If there is no data waiting to be read from the serial device, then FALSE is returned.
> +
> + @retval TRUE Data is waiting to be read from the serial device.
> + @retval FALSE There is no data waiting to be read from the serial device.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +SerialPortPoll (
> + VOID
> + )
> +{
> + STATIC volatile UINT32 * const uart = (UINT32 *)FixedPcdGet32(PcdU5UartBase);
> + UINT32 IP;
> +
> + if (Initiated == FALSE) {
> + return FALSE;
> + }
> + IP = MmioRead32 ((UINTN)(uart + UART_REG_IP));
> + if(IP & UART_IP_RXWM) {
> + return TRUE;
> + }
> + else {
> + return FALSE;
> + }
> +}
> +
> +/**
> + Sets the control bits on a serial device.
> +
> + @param Control Sets the bits of Control that are settable.
> +
> + @retval RETURN_SUCCESS The new control bits were set on the serial device.
> + @retval RETURN_UNSUPPORTED The serial device does not support this operation.
> + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortSetControl (
> + IN UINT32 Control
> + )
> +{
> + if (Initiated == FALSE) {
> + return EFI_NOT_READY;
> + }
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Retrieve the status of the control bits on a serial device.
> +
> + @param Control A pointer to return the current control signals from the serial device.
> +
> + @retval RETURN_SUCCESS The control bits were read from the serial device.
> + @retval RETURN_UNSUPPORTED The serial device does not support this operation.
> + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortGetControl (
> + OUT UINT32 *Control
> + )
> +{
> + if (Initiated == FALSE) {
> + return EFI_NOT_READY;
> + }
> + *Control = 0;
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
> + data bits, and stop bits on a serial device.
> +
> + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
> + device's default interface speed.
> + On output, the value actually set.
> + @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
> + serial interface. A ReceiveFifoDepth value of 0 will use
> + the device's default FIFO depth.
> + On output, the value actually set.
> + @param Timeout The requested time out for a single character in microseconds.
> + This timeout applies to both the transmit and receive side of the
> + interface. A Timeout value of 0 will use the device's default time
> + out value.
> + On output, the value actually set.
> + @param Parity The type of parity to use on this serial device. A Parity value of
> + DefaultParity will use the device's default parity value.
> + On output, the value actually set.
> + @param DataBits The number of data bits to use on the serial device. A DataBits
> + vaule of 0 will use the device's default data bit setting.
> + On output, the value actually set.
> + @param StopBits The number of stop bits to use on this serial device. A StopBits
> + value of DefaultStopBits will use the device's default number of
> + stop bits.
> + On output, the value actually set.
> +
> + @retval RETURN_SUCCESS The new attributes were set on the serial device.
> + @retval RETURN_UNSUPPORTED The serial device does not support this operation.
> + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
> + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortSetAttributes (
> + IN OUT UINT64 *BaudRate,
> + IN OUT UINT32 *ReceiveFifoDepth,
> + IN OUT UINT32 *Timeout,
> + IN OUT EFI_PARITY_TYPE *Parity,
> + IN OUT UINT8 *DataBits,
> + IN OUT EFI_STOP_BITS_TYPE *StopBits
> + )
> +{
> + if (Initiated == FALSE) {
> + return EFI_NOT_READY;
> + }
> + return RETURN_SUCCESS;
> +}
> diff --git a/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/U5SerialPortLib.uni b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/U5SerialPortLib.uni
> new file mode 100644
> index 0000000..49163bd
> --- /dev/null
> +++ b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/U5SerialPortLib.uni
> @@ -0,0 +1,16 @@
> +// /** @file
> +// Library instance for SerialIo library class
> +//
> +// Library instance for SerialIO library class.
> +//
> +// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +//
> +// SPDX-License-Identifier: BSD-2-Clause-Patent
> +//
> +// **/
> +
> +
> +#string STR_MODULE_ABSTRACT #language en-US "Library instance for SerialIO library class"
> +
> +#string STR_MODULE_DESCRIPTION #language en-US "Library instance for SerialIO library class."
> +
^ permalink raw reply [flat|nested] 23+ messages in thread
* [platform/devel-riscv-v2 PATCHv5 10/18] FreedomU540HiFiveUnleashedBoard/PlatformPei:Platform PEI
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (8 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 09/18] U5SeriesPkg/SerialIoLib: Platform Serial Port library Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 11/18] FreedomU540HiFiveUnleashedBoard/OpensbiPlatformLib:OpenSBI platform lib Abner Chang
` (8 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
Platform PEI module for U540 platform initialization.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../Universal/Pei/PlatformPei/PlatformPei.inf | 72 +++++
.../Universal/Pei/PlatformPei/Platform.h | 86 ++++++
.../Universal/Pei/PlatformPei/Fv.c | 51 ++++
.../Universal/Pei/PlatformPei/MemDetect.c | 74 +++++
.../Universal/Pei/PlatformPei/Platform.c | 310 +++++++++++++++++++++
5 files changed, 593 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.h
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Fv.c
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/MemDetect.c
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf
new file mode 100644
index 0000000..32c74c4
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf
@@ -0,0 +1,72 @@
+## @file
+# Platform PEI driver
+#
+# This module provides platform specific function to detect boot mode.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformPei
+ FILE_GUID = 5592FC16-8FEF-4DE3-A6CF-6C59081E4EB7
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializePlatform
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Fv.c
+ MemDetect.c
+ Platform.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+ RiscVPkg/RiscVPkg.dec
+ Silicon/SiFive/SiFive.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Guids]
+ gEfiMemoryTypeInformationGuid
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ IoLib
+ PciLib
+ PeiResourcePublicationLib
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ PeimEntryPoint
+ PcdLib
+ SiliconSiFiveU5MCCoreplexInfoLib
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize
+ gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported
+
+[Ppis]
+ gEfiPeiMasterBootModePpiGuid
+
+[Depex]
+ TRUE
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.h b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.h
new file mode 100644
index 0000000..c2cdd6d
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.h
@@ -0,0 +1,86 @@
+/** @file
+ Platform PEI module include file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_PEI_H_INCLUDED_
+#define PLATFORM_PEI_H_INCLUDED_
+
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddIoMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddUntestedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddReservedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddUntestedMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddressWidthInitialization (
+ VOID
+ );
+
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ );
+
+UINT32
+GetSystemMemorySizeBelow4gb (
+ VOID
+ );
+
+VOID
+InitializeRamRegions (
+ VOID
+ );
+
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ );
+
+EFI_STATUS
+InitializeXen (
+ VOID
+ );
+
+#endif // _PLATFORM_PEI_H_INCLUDED_
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Fv.c b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Fv.c
new file mode 100644
index 0000000..060d662
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Fv.c
@@ -0,0 +1,51 @@
+/** @file
+ Build FV related hobs for platform.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PiPei.h"
+#include "Platform.h"
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+
+/**
+ Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+ and DXE know about them.
+
+ @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.
+
+**/
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
+ //
+ // Let DXE know about the DXE FV
+ //
+ BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
+ DEBUG ((DEBUG_INFO, "Platform builds DXE FV at %x, size %x.\n",
+ PcdGet32 (PcdRiscVDxeFvBase),
+ PcdGet32 (PcdRiscVDxeFvSize)));
+
+ //
+ // Let PEI know about the DXE FV so it can find the DXE Core
+ //
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
+ PcdGet32 (PcdRiscVDxeFvSize),
+ NULL,
+ NULL
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/MemDetect.c b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/MemDetect.c
new file mode 100644
index 0000000..dc99f2e
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/MemDetect.c
@@ -0,0 +1,74 @@
+/**@file
+ Memory Detection for Virtual Machines.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+Module Name:
+
+ MemDetect.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/ResourcePublicationLib.h>
+
+#include "Platform.h"
+
+
+/**
+ Publish PEI core memory
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS MemoryBase;
+ UINT64 MemorySize;
+
+ MemoryBase = 0x80000000UL + 0x1000000UL;
+ MemorySize = 0x40000000UL - 0x1000000UL; //1GB - 16MB
+
+ DEBUG((DEBUG_INFO, "%a: MemoryBase:0x%x MemorySize:%d\n", __FUNCTION__, MemoryBase, MemorySize));
+
+ //
+ // Publish this memory to the PEI Core
+ //
+ Status = PublishSystemMemory(MemoryBase, MemorySize);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Publish system RAM and reserve memory regions
+
+**/
+VOID
+InitializeRamRegions (
+ VOID
+ )
+{
+ AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL);
+
+}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c
new file mode 100644
index 0000000..3d3f67d
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c
@@ -0,0 +1,310 @@
+/**@file
+ Platform PEI driver
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ResourcePublicationLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Ppi/MasterBootMode.h>
+#include <IndustryStandard/Pci22.h>
+
+#include <SiFiveU5MCCoreplex.h>
+
+#include "Platform.h"
+
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIMemoryNVS, 0x004 },
+ { EfiACPIReclaimMemory, 0x008 },
+ { EfiReservedMemoryType, 0x004 },
+ { EfiRuntimeServicesData, 0x024 },
+ { EfiRuntimeServicesCode, 0x030 },
+ { EfiBootServicesCode, 0x180 },
+ { EfiBootServicesData, 0xF00 },
+ { EfiMaxMemoryType, 0x000 }
+};
+
+
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiMasterBootModePpiGuid,
+ NULL
+ }
+};
+
+STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddReservedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_RESERVED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddIoMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+
+VOID
+AddMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+
+VOID
+AddMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+
+VOID
+AddUntestedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddUntestedMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+VOID
+AddPciResource (
+ VOID
+ )
+{
+ //
+ // Platform-specific
+ //
+}
+
+VOID
+MemMapInitialization (
+ VOID
+ )
+{
+ //
+ // Create Memory Type Information HOB
+ //
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ mDefaultMemoryTypeInformation,
+ sizeof(mDefaultMemoryTypeInformation)
+ );
+
+ //
+ // Add PCI IO Port space available for PCI resource allocations.
+ //
+ AddPciResource ();
+}
+
+VOID
+MiscInitialization (
+ VOID
+ )
+{
+ //
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
+ // S3 resume as well, so we build it unconditionally.)
+ //
+ BuildCpuHob (32, 32);
+}
+
+/**
+ Check if system retunrs from S3.
+
+ @return BOOLEAN TRUE, system returned from S3
+ FALSE, system is not returned from S3
+
+**/
+BOOLEAN
+CheckResumeFromS3 (
+ VOID
+ )
+{
+ //
+ //Platform implementation-specific
+ //
+ return FALSE;
+}
+
+
+VOID
+BootModeInitialization (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ if (CheckResumeFromS3 () == TRUE) {
+ DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "This is normal boot\n"));
+ }
+ Status = PeiServicesSetBootMode (mBootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PeiServicesInstallPpi (mPpiBootMode);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Build processor information for U54 Coreplex processor.
+
+ @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildCoreInformationHob (
+ VOID
+)
+{
+ EFI_STATUS Status;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;
+
+ Status = CreateU5MCCoreplexProcessorSpecificDataHob (0);
+ if (EFI_ERROR (Status)) {
+ ASSERT(FALSE);
+ }
+ Status = CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr);
+ if (EFI_ERROR (Status)) {
+ ASSERT(FALSE);
+ }
+
+ DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", SmbiosHobPtr));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Perform Platform PEI initialization.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializePlatform (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
+
+ BootModeInitialization ();
+ DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n"));
+ PublishPeiMemory ();
+ DEBUG ((DEBUG_INFO, "PEI memory published.\n"));
+ InitializeRamRegions ();
+ DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n"));
+
+ if (mBootMode != BOOT_ON_S3_RESUME) {
+ PeiFvInitialization ();
+ MemMapInitialization ();
+ }
+
+ MiscInitialization ();
+ Status = BuildCoreInformationHob ();
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n"));
+ ASSERT(FALSE);
+ }
+ return EFI_SUCCESS;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 11/18] FreedomU540HiFiveUnleashedBoard/OpensbiPlatformLib:OpenSBI platform lib
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (9 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 10/18] FreedomU540HiFiveUnleashedBoard/PlatformPei:Platform PEI Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-11-19 15:30 ` [edk2-devel] " Mark Salter
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 12/18] U5SeriesPkg/FreedomU540HiFiveUnleashedBoard: Add SiFive U540 platform Abner Chang
` (7 subsequent siblings)
18 siblings, 1 reply; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
This is OpenSBI platform code implementation of U540 platform.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 52 +++++
.../Library/OpensbiPlatformLib/Platform.c | 213 +++++++++++++++++++++
2 files changed, 265 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/Platform.c
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
new file mode 100644
index 0000000..21710d4
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -0,0 +1,52 @@
+## @file
+# RISC-V OpenSBI Platform Library
+# This is the the library which provides platform
+# level opensbi functions follow RISC-V OpenSBI implementation.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVOpensbiPlatformLib
+ FILE_GUID = 80C09428-44DD-437F-8252-F7AB64711AA5
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVOpensbiPlatformLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Platform.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DebugAgentLib
+ FdtLib
+ PcdLib
+ PrintLib
+ RiscVCpuLib
+
+[FixedPcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
+
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/Platform.c
new file mode 100644
index 0000000..b9deec6
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/Platform.c
@@ -0,0 +1,213 @@
+/*
+ *
+ * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Atish Patra <atish.patra@wdc.com>
+ */
+
+#include <libfdt.h>
+#include <fdt.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/riscv_io.h>
+#include <sbi_utils/irqchip/plic.h>
+#include <sbi_utils/serial/sifive-uart.h>
+#include <sbi_utils/sys/clint.h>
+#include <U5Clint.h>
+
+#define U540_HART_COUNT FixedPcdGet32(PcdHartCount)
+#define U540_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize)
+#define U540_BOOT_HART_ID FixedPcdGet32(PcdBootHartId)
+
+#define U540_SYS_CLK 100000000
+
+#define U540_PLIC_ADDR 0xc000000
+#define U540_PLIC_NUM_SOURCES 0x35
+#define U540_PLIC_NUM_PRIORITIES 7
+
+#define U540_UART_ADDR FixedPcdGet32(PcdU5UartBase)
+
+#define U540_UART_BAUDRATE 115200
+
+/**
+ * The U540 SoC has 5 HARTs but HART ID 0 has only SMode.
+ * HARTs 1 is selected as boot HART
+ */
+#ifndef U540_ENABLED_HART_MASK
+#define U540_ENABLED_HART_MASK (1 << U540_BOOT_HART_ID)
+#endif
+
+#define U540_HARTID_DISABLED ~(U540_ENABLED_HART_MASK)
+
+/* PRCI clock related macros */
+//TODO: Do we need a separate driver for this ?
+#define U540_PRCI_BASE_ADDR 0x10000000
+#define U540_PRCI_CLKMUXSTATUSREG 0x002C
+#define U540_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
+
+static void U540_modify_dt(void *fdt)
+{
+ u32 i, size;
+ int chosen_offset, err;
+ int cpu_offset;
+ char cpu_node[32] = "";
+ const char *mmu_type;
+
+ for (i = 0; i < U540_HART_COUNT; i++) {
+ sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
+ cpu_offset = fdt_path_offset(fdt, cpu_node);
+ mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL);
+ if (mmu_type && (!AsciiStrCmp(mmu_type, "riscv,sv39") ||
+ !AsciiStrCmp(mmu_type,"riscv,sv48")))
+ continue;
+ else
+ fdt_setprop_string(fdt, cpu_offset, "status", "masked");
+ memset(cpu_node, 0, sizeof(cpu_node));
+ }
+ size = fdt_totalsize(fdt);
+ err = fdt_open_into(fdt, fdt, size + 256);
+ if (err < 0)
+ sbi_printf("Device Tree can't be expanded to accmodate new node");
+
+ chosen_offset = fdt_path_offset(fdt, "/chosen");
+ fdt_setprop_string(fdt, chosen_offset, "stdout-path",
+ "/soc/serial@10010000:115200");
+
+ plic_fdt_fixup(fdt, "riscv,plic0");
+}
+
+static int U540_final_init(bool cold_boot)
+{
+ void *fdt;
+
+ if (!cold_boot)
+ return 0;
+
+ fdt = sbi_scratch_thishart_arg1_ptr();
+ U540_modify_dt(fdt);
+
+ return 0;
+}
+
+static u32 U540_pmp_region_count(u32 hartid)
+{
+ return 1;
+}
+
+static int U540_pmp_region_info(u32 hartid, u32 index,
+ ulong *prot, ulong *addr, ulong *log2size)
+{
+ int ret = 0;
+
+ switch (index) {
+ case 0:
+ *prot = PMP_R | PMP_W | PMP_X;
+ *addr = 0;
+ *log2size = __riscv_xlen;
+ break;
+ default:
+ ret = -1;
+ break;
+ };
+
+ return ret;
+}
+
+static int U540_console_init(void)
+{
+ unsigned long peri_in_freq;
+
+ peri_in_freq = U540_SYS_CLK/2;
+ return sifive_uart_init(U540_UART_ADDR, peri_in_freq, U540_UART_BAUDRATE);
+}
+
+static int U540_irqchip_init(bool cold_boot)
+{
+ int rc;
+ u32 hartid = sbi_current_hartid();
+
+ if (cold_boot) {
+ rc = plic_cold_irqchip_init(U540_PLIC_ADDR,
+ U540_PLIC_NUM_SOURCES,
+ U540_HART_COUNT);
+ if (rc)
+ return rc;
+ }
+
+ return plic_warm_irqchip_init(hartid,
+ (hartid) ? (2 * hartid - 1) : 0,
+ (hartid) ? (2 * hartid) : -1);
+}
+
+static int U540_ipi_init(bool cold_boot)
+{
+ int rc;
+
+ if (cold_boot) {
+ rc = clint_cold_ipi_init(CLINT_REG_BASE_ADDR,
+ U540_HART_COUNT);
+ if (rc)
+ return rc;
+
+ }
+
+ return clint_warm_ipi_init();
+}
+
+static int U540_timer_init(bool cold_boot)
+{
+ int rc;
+
+ if (cold_boot) {
+ rc = clint_cold_timer_init(CLINT_REG_BASE_ADDR,
+ U540_HART_COUNT);
+ if (rc)
+ return rc;
+ }
+
+ return clint_warm_timer_init();
+}
+
+static int U540_system_down(u32 type)
+{
+ /* For now nothing to do. */
+ return 0;
+}
+
+const struct sbi_platform_operations platform_ops = {
+ .pmp_region_count = U540_pmp_region_count,
+ .pmp_region_info = U540_pmp_region_info,
+ .final_init = U540_final_init,
+ .console_putc = sifive_uart_putc,
+ .console_getc = sifive_uart_getc,
+ .console_init = U540_console_init,
+ .irqchip_init = U540_irqchip_init,
+ .ipi_send = clint_ipi_send,
+ .ipi_clear = clint_ipi_clear,
+ .ipi_init = U540_ipi_init,
+ .timer_value = clint_timer_value,
+ .timer_event_stop = clint_timer_event_stop,
+ .timer_event_start = clint_timer_event_start,
+ .timer_init = U540_timer_init,
+ .system_reboot = U540_system_down,
+ .system_shutdown = U540_system_down
+};
+
+const struct sbi_platform platform = {
+ .opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on.
+ .platform_version = SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI Platform version 1.0
+ .name = "SiFive Freedom U540",
+ .features = SBI_PLATFORM_DEFAULT_FEATURES,
+ .hart_count = U540_HART_COUNT,
+ .hart_stack_size = U540_HART_STACK_SIZE,
+ .disabled_hart_mask = U540_HARTID_DISABLED,
+ .platform_ops_addr = (unsigned long)&platform_ops
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [edk2-devel] [platform/devel-riscv-v2 PATCHv5 11/18] FreedomU540HiFiveUnleashedBoard/OpensbiPlatformLib:OpenSBI platform lib
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 11/18] FreedomU540HiFiveUnleashedBoard/OpensbiPlatformLib:OpenSBI platform lib Abner Chang
@ 2019-11-19 15:30 ` Mark Salter
0 siblings, 0 replies; 23+ messages in thread
From: Mark Salter @ 2019-11-19 15:30 UTC (permalink / raw)
To: devel, abner.chang
Cc: Michael D Kinney, Ard Biesheuvel, Leif Lindholm, Gilbert Chen,
Palmer Dabbelt
On Mon, 2019-10-28 at 12:20 +0800, Abner Chang wrote:
> This is OpenSBI platform code implementation of U540 platform.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> ---
> .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 52 +++++
> .../Library/OpensbiPlatformLib/Platform.c | 213 +++++++++++++++++++++
> 2 files changed, 265 insertions(+)
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/Platform.c
>
> diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> new file mode 100644
> index 0000000..21710d4
> --- /dev/null
> +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> @@ -0,0 +1,52 @@
> +## @file
> +# RISC-V OpenSBI Platform Library
> +# This is the the library which provides platform
> +# level opensbi functions follow RISC-V OpenSBI implementation.
> +#
> +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = RiscVOpensbiPlatformLib
> + FILE_GUID = 80C09428-44DD-437F-8252-F7AB64711AA5
> + MODULE_TYPE = SEC
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RiscVOpensbiPlatformLib
> +
> +#
> +# The following information is for reference only and not required by the build tools.
> +#
> +# VALID_ARCHITECTURES = RISCV64
> +#
> +
> +[Sources]
> + Platform.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
> + RiscVPlatformPkg/RiscVPlatformPkg.dec
> + RiscVPkg/RiscVPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DebugLib
> + DebugAgentLib
> + FdtLib
> + PcdLib
> + PrintLib
> + RiscVCpuLib
> +
> +[FixedPcd]
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
> +
> + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
> diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/Platform.c
> b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/Platform.c
> new file mode 100644
> index 0000000..b9deec6
> --- /dev/null
> +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/Platform.c
> @@ -0,0 +1,213 @@
> +/*
> + *
> + * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> + *
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
> + *
> + * Authors:
> + * Atish Patra <atish.patra@wdc.com>
> + */
> +
> +#include <libfdt.h>
> +#include <fdt.h>
> +#include <sbi/riscv_encoding.h>
> +#include <sbi/sbi_const.h>
> +#include <sbi/sbi_hart.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/riscv_io.h>
> +#include <sbi_utils/irqchip/plic.h>
> +#include <sbi_utils/serial/sifive-uart.h>
> +#include <sbi_utils/sys/clint.h>
> +#include <U5Clint.h>
> +
> +#define U540_HART_COUNT FixedPcdGet32(PcdHartCount)
> +#define U540_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize)
> +#define U540_BOOT_HART_ID FixedPcdGet32(PcdBootHartId)
> +
> +#define U540_SYS_CLK 100000000
^^^^^^^^^^
This should be 1000000000
1GHz, not 100MHz
> +
> +#define U540_PLIC_ADDR 0xc000000
> +#define U540_PLIC_NUM_SOURCES 0x35
> +#define U540_PLIC_NUM_PRIORITIES 7
> +
> +#define U540_UART_ADDR FixedPcdGet32(PcdU5UartBase)
> +
> +#define U540_UART_BAUDRATE 115200
> +
> +/**
> + * The U540 SoC has 5 HARTs but HART ID 0 has only SMode.
> + * HARTs 1 is selected as boot HART
> + */
> +#ifndef U540_ENABLED_HART_MASK
> +#define U540_ENABLED_HART_MASK (1 << U540_BOOT_HART_ID)
> +#endif
> +
> +#define U540_HARTID_DISABLED ~(U540_ENABLED_HART_MASK)
> +
> +/* PRCI clock related macros */
> +//TODO: Do we need a separate driver for this ?
> +#define U540_PRCI_BASE_ADDR 0x10000000
> +#define U540_PRCI_CLKMUXSTATUSREG 0x002C
> +#define U540_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
> +
> +static void U540_modify_dt(void *fdt)
> +{
> + u32 i, size;
> + int chosen_offset, err;
> + int cpu_offset;
> + char cpu_node[32] = "";
> + const char *mmu_type;
> +
> + for (i = 0; i < U540_HART_COUNT; i++) {
> + sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
> + cpu_offset = fdt_path_offset(fdt, cpu_node);
> + mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL);
> + if (mmu_type && (!AsciiStrCmp(mmu_type, "riscv,sv39") ||
> + !AsciiStrCmp(mmu_type,"riscv,sv48")))
> + continue;
> + else
> + fdt_setprop_string(fdt, cpu_offset, "status", "masked");
> + memset(cpu_node, 0, sizeof(cpu_node));
> + }
> + size = fdt_totalsize(fdt);
> + err = fdt_open_into(fdt, fdt, size + 256);
> + if (err < 0)
> + sbi_printf("Device Tree can't be expanded to accmodate new node");
> +
> + chosen_offset = fdt_path_offset(fdt, "/chosen");
> + fdt_setprop_string(fdt, chosen_offset, "stdout-path",
> + "/soc/serial@10010000:115200");
> +
> + plic_fdt_fixup(fdt, "riscv,plic0");
> +}
> +
> +static int U540_final_init(bool cold_boot)
> +{
> + void *fdt;
> +
> + if (!cold_boot)
> + return 0;
> +
> + fdt = sbi_scratch_thishart_arg1_ptr();
> + U540_modify_dt(fdt);
> +
> + return 0;
> +}
> +
> +static u32 U540_pmp_region_count(u32 hartid)
> +{
> + return 1;
> +}
> +
> +static int U540_pmp_region_info(u32 hartid, u32 index,
> + ulong *prot, ulong *addr, ulong *log2size)
> +{
> + int ret = 0;
> +
> + switch (index) {
> + case 0:
> + *prot = PMP_R | PMP_W | PMP_X;
> + *addr = 0;
> + *log2size = __riscv_xlen;
> + break;
> + default:
> + ret = -1;
> + break;
> + };
> +
> + return ret;
> +}
> +
> +static int U540_console_init(void)
> +{
> + unsigned long peri_in_freq;
> +
> + peri_in_freq = U540_SYS_CLK/2;
> + return sifive_uart_init(U540_UART_ADDR, peri_in_freq, U540_UART_BAUDRATE);
> +}
> +
> +static int U540_irqchip_init(bool cold_boot)
> +{
> + int rc;
> + u32 hartid = sbi_current_hartid();
> +
> + if (cold_boot) {
> + rc = plic_cold_irqchip_init(U540_PLIC_ADDR,
> + U540_PLIC_NUM_SOURCES,
> + U540_HART_COUNT);
> + if (rc)
> + return rc;
> + }
> +
> + return plic_warm_irqchip_init(hartid,
> + (hartid) ? (2 * hartid - 1) : 0,
> + (hartid) ? (2 * hartid) : -1);
> +}
> +
> +static int U540_ipi_init(bool cold_boot)
> +{
> + int rc;
> +
> + if (cold_boot) {
> + rc = clint_cold_ipi_init(CLINT_REG_BASE_ADDR,
> + U540_HART_COUNT);
> + if (rc)
> + return rc;
> +
> + }
> +
> + return clint_warm_ipi_init();
> +}
> +
> +static int U540_timer_init(bool cold_boot)
> +{
> + int rc;
> +
> + if (cold_boot) {
> + rc = clint_cold_timer_init(CLINT_REG_BASE_ADDR,
> + U540_HART_COUNT);
> + if (rc)
> + return rc;
> + }
> +
> + return clint_warm_timer_init();
> +}
> +
> +static int U540_system_down(u32 type)
> +{
> + /* For now nothing to do. */
> + return 0;
> +}
> +
> +const struct sbi_platform_operations platform_ops = {
> + .pmp_region_count = U540_pmp_region_count,
> + .pmp_region_info = U540_pmp_region_info,
> + .final_init = U540_final_init,
> + .console_putc = sifive_uart_putc,
> + .console_getc = sifive_uart_getc,
> + .console_init = U540_console_init,
> + .irqchip_init = U540_irqchip_init,
> + .ipi_send = clint_ipi_send,
> + .ipi_clear = clint_ipi_clear,
> + .ipi_init = U540_ipi_init,
> + .timer_value = clint_timer_value,
> + .timer_event_stop = clint_timer_event_stop,
> + .timer_event_start = clint_timer_event_start,
> + .timer_init = U540_timer_init,
> + .system_reboot = U540_system_down,
> + .system_shutdown = U540_system_down
> +};
> +
> +const struct sbi_platform platform = {
> + .opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on.
> + .platform_version = SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI Platform version 1.0
> + .name = "SiFive Freedom U540",
> + .features = SBI_PLATFORM_DEFAULT_FEATURES,
> + .hart_count = U540_HART_COUNT,
> + .hart_stack_size = U540_HART_STACK_SIZE,
> + .disabled_hart_mask = U540_HARTID_DISABLED,
> + .platform_ops_addr = (unsigned long)&platform_ops
> +};
^ permalink raw reply [flat|nested] 23+ messages in thread
* [platform/devel-riscv-v2 PATCHv5 12/18] U5SeriesPkg/FreedomU540HiFiveUnleashedBoard: Add SiFive U540 platform.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (10 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 11/18] FreedomU540HiFiveUnleashedBoard/OpensbiPlatformLib:OpenSBI platform lib Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 13/18] FreedomU500VC707Board/PlatformPei: Platform initialization PEI module Abner Chang
` (6 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
Add SiFive U540 platform build metafiles.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../FreedomU540HiFiveUnleashedBoard/U540.dec | 25 +
.../FreedomU540HiFiveUnleashedBoard/U540.dsc | 543 +++++++++++++++++++++
.../FreedomU540HiFiveUnleashedBoard/U540.fdf | 336 +++++++++++++
.../FreedomU540HiFiveUnleashedBoard/U540.fdf.inc | 54 ++
.../VarStore.fdf.inc | 78 +++
.../FreedomU540HiFiveUnleashedBoard/U540.uni | 13 +
| 12 +
7 files changed, 1061 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dec
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.fdf.inc
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.uni
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540PkgExtra.uni
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dec b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dec
new file mode 100644
index 0000000..8ad80a1
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dec
@@ -0,0 +1,25 @@
+## @file U540.dec
+# This Package provides SiFive U540 modules and libraries.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = U540
+ PACKAGE_UNI_FILE = U540.uni
+ PACKAGE_GUID = B6569821-3FC0-4FE8-B98A-67CE1517C747
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+
+[LibraryClasses]
+
+[Guids]
+ gUefiRiscVPlatformU540PkgTokenSpaceGuid = {0xDFD87009, 0x27A1, 0x41DD, { 0x84, 0xB1, 0x35, 0xB4, 0xB9, 0x0D, 0x17, 0x63 }}
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ U540PkgExtra.uni
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
new file mode 100644
index 0000000..55ea52a
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -0,0 +1,543 @@
+## @file
+# RISC-V EFI on SiFive Freedom U540 HiFive Unleashed RISC-V platform
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = FreedomU540HiFiveUnleashed
+ PLATFORM_GUID = 8317E90F-428B-403F-9057-112B0C19008E
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001c
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = RISCV64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
+
+ #
+ # Enable below options may cause build error or may not work on
+ # the initial version of RISC-V package
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ DEFINE SECURE_BOOT_ENABLE = FALSE
+ DEFINE DEBUG_ON_SERIAL_PORT = TRUE
+
+ #
+ # Network definition
+ #
+ DEFINE NETWORK_SNP_ENABLE = FALSE
+ DEFINE NETWORK_IP6_ENABLE = FALSE
+ DEFINE NETWORK_TLS_ENABLE = FALSE
+ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
+ DEFINE NETWORK_ISCSI_ENABLE = FALSE
+
+[BuildOptions]
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable
+!endif
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses]
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ SerialPortLib|Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+ SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+
+# RISC-V Platform Library
+ TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf
+ RealTimeClockLib|EmbeddedPkg//Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+# RISC-V Core Library
+ RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+ DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
+!else
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+!endif
+
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+ TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+ AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+!else
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+!endif
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+!if $(HTTP_BOOT_ENABLE) == TRUE
+ HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+!endif
+
+# ACPI not supported yet.
+ #S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
+ SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
+ OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+
+[LibraryClasses.common]
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+!endif
+ RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
+ RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
+ CpuExceptionHandlerLib|RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+
+[LibraryClasses.common.SEC]
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
+!endif
+
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+#
+# OpenSBi Platform Library
+#
+ RiscVOpensbiPlatformLib|Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+
+[LibraryClasses.common.PEIM]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
+!endif
+ FirmwareContextProcessorSpecificLib|RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
+ RiscVPlatformDxeIplLib|RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
+
+#
+# RISC-V core libraries
+#
+ SiliconSiFiveE51CoreInfoLib|Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+ SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+ SiliconSiFiveU5MCCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+ #CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ PlatformBootManagerLib|RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ PlatformMemoryTestLib|RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
+ PlatformUpdateProgressLib|RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+[PcdsFeatureFlag]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+
+[PcdsFixedAtBuild]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+!endif
+
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
+!endif
+
+ #gUefiPayloadPkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot
+ gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
+ gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
+ gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
+!endif
+
+ #
+ # F2 for UI APP
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+################################################################################
+#
+# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsDynamicDefault]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
+
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0
+
+ # Set video resolution for text setup.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components]
+
+ #
+ # SEC Phase modules
+ #
+ RiscVPlatformPkg/Universal/Sec/SecMain.inf
+
+ #
+ # PEI Phase modules
+ #
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+ MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }
+
+ #
+ # DXE Phase modules
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg//Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ }
+
+ MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
+ <LibraryClasses>
+ NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
+ }
+!else
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+!endif
+
+ #
+ # EBC not supported on RISC-V yet
+ #
+ #MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+ UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+ MdeModulePkg/Universal/Metronome/Metronome.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf {
+ <LibraryClasses>
+ ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf
+ }
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # RISC-V Platform module
+ #
+ Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
+ Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
+
+ #
+ # RISC-V Core module
+ #
+ RiscVPkg/Universal/CpuDxe/CpuDxe.inf
+ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
+
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+# No graphic console supported yet.
+# MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf {
+# <LibraryClasses>
+# PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+# }
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf {
+ <LibraryClasses>
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+ #
+ # ACPI Support
+ # Not support on RISC-V yet
+ #
+ #MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ #MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+
+ #
+ # Network Support
+ #
+ !include NetworkPkg/Network.dsc.inc
+
+ #
+ # Usb Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!endif
+
+ MdeModulePkg/Application/UiApp/UiApp.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
new file mode 100644
index 0000000..0707ad9
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
@@ -0,0 +1,336 @@
+# @file
+# Flash definition file on SiFive Freedom U540 HiFive Unleashed RISC-V platform
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+#
+# Platform definitions
+#
+!include U540.fdf.inc
+
+#
+# Build the variable store and the firmware code as one unified flash device
+# image.
+#
+[FD.U540]
+BaseAddress = $(FW_BASE_ADDRESS)
+Size = $(FW_SIZE)
+ErasePolarity = 1
+BlockSize = $(BLOCK_SIZE)
+NumBlocks = $(FW_BLOCKS)
+
+$(SECFV_OFFSET)|$(SECFV_SIZE)
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize
+FV = SECFV
+
+$(PEIFV_OFFSET)|$(PEIFV_SIZE)
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize
+FV = PEIFV
+
+$(FVMAIN_OFFSET)|$(FVMAIN_SIZE)
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
+FV = FVMAIN_COMPACT
+
+!include VarStore.fdf.inc
+
+################################################################################
+
+[FV.SECFV]
+BlockSize = 0x1000
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+#
+# SEC Phase modules
+#
+# The code in this FV handles the initial firmware startup, and
+# decompresses the PEI and DXE FVs which handles the rest of the boot sequence.
+#
+INF RiscVPlatformPkg/Universal/Sec/SecMain.inf
+
+################################################################################
+[FV.PEIFV]
+BlockSize = 0x10000
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+APRIORI PEI {
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+}
+
+#
+# PEI Phase modules
+#
+INF MdeModulePkg/Core/Pei/PeiMain.inf
+INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
+INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+# RISC-V Platform PEI Driver
+INF Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf
+
+################################################################################
+
+[FV.DXEFV]
+BlockSize = 0x10000
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+APRIORI DXE {
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
+}
+
+#
+# DXE Phase modules
+#
+INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+INF MdeModulePkg/Universal/Metronome/Metronome.inf
+INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+# RISC-V Platform Drivers
+INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
+
+# RISC-V Core Drivers
+INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
+INF RiscVPkg/Universal/CpuDxe/CpuDxe.inf
+INF RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
+
+INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!endif
+
+INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+#INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
+INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+
+!ifndef $(SOURCE_DEBUG_ENABLE)
+INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+!endif
+
+INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+#
+# ACPI is not supported yet on RISC-V package.
+#
+#INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+#INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+#INF PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf
+
+#INF RuleOverride = BINARY FatBinPkg/EnhancedFatDxe/Fat.inf
+
+INF ShellPkg/Application/Shell/Shell.inf
+
+#
+# Network modules
+#
+!if $(E1000_ENABLE)
+ FILE DRIVER = 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 {
+ SECTION PE32 = Intel3.5/EFIX64/E3507X2.EFI
+ }
+!endif
+
+!include NetworkPkg/Network.fdf.inc
+
+#
+# Usb Support
+#
+INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+################################################################################
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 27A72E80-3118-4c0c-8673-AA5B4EFA9613
+
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ #
+ # These firmware volumes will have files placed in them uncompressed,
+ # and then both firmware volumes will be compressed in a single
+ # compression operation in order to achieve better overall compression.
+ #
+ SECTION FV_IMAGE = DXEFV
+ }
+ }
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 Align=4K |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 Align=4K |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ }
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
new file mode 100644
index 0000000..00a2315
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
@@ -0,0 +1,54 @@
+## @file
+# Definitions of Flash definition file on SiFive Freedom U540 HiFive Unleashed RISC-V platform
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+[Defines]
+DEFINE BLOCK_SIZE = 0x1000
+
+DEFINE FW_BASE_ADDRESS = 0x80000000
+DEFINE FW_SIZE = 0x00800000
+DEFINE FW_BLOCKS = 0x800
+
+#
+# 0x000000-0x7DFFFF code
+# 0x7E0000-0x800000 variables
+#
+DEFINE CODE_BASE_ADDRESS = 0x80000000
+DEFINE CODE_SIZE = 0x007E0000
+DEFINE CODE_BLOCKS = 0x7E0
+DEFINE VARS_BLOCKS = 0x20
+
+DEFINE SECFV_OFFSET = 0x00000000
+DEFINE SECFV_SIZE = 0x00020000
+DEFINE PEIFV_OFFSET = 0x00020000
+DEFINE PEIFV_SIZE = 0x00080000
+DEFINE SCRATCH_OFFSET = 0x000a0000
+DEFINE SCRATCH_SIZE = 0x00010000
+DEFINE FVMAIN_OFFSET = 0x00100000 # Must be power of 2 for PMP setting
+DEFINE FVMAIN_SIZE = 0x0018C000
+DEFINE VARS_OFFSET = 0x007E0000
+DEFINE VARS_SIZE = 0x00020000
+
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress = $(FW_BASE_ADDRESS) + $(VARS_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize = $(VARS_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize = $(BLOCK_SIZE)
+
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress = $(CODE_BASE_ADDRESS)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress = $(CODE_BASE_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize = 8192
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase = $(CODE_BASE_ADDRESS) + $(SCRATCH_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize = $(SCRATCH_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase = $(CODE_BASE_ADDRESS) + $(FW_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize = 0x10000
+
+
+SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz = 1000000
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount = 5 # Total cores on U540 platform
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId = 1 # Boot hart ID
+SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores = 4 # Total U5 cores enabled on U540 platform
+SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported = True # E51 MC exists.
+SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase = 0x10010000 # Serial port base address
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.fdf.inc
new file mode 100644
index 0000000..c287bb4
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.fdf.inc
@@ -0,0 +1,78 @@
+## @file
+# FDF include file with Layout Regions that define an empty variable store.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+$(VARS_OFFSET)|0x00007000
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#
+# NV_VARIABLE_STORE
+#
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x20000
+ 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x39, 0xF1, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block
+ 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ # Signature: gEfiAuthenticatedVariableGuid =
+ # { 0xaaf32c78, 0x947b, 0x439a,
+ # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+!else
+ # Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164,
+ # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+!endif
+ # Size: 0x7000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x6fb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0x6F, 0x00, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x007e7000|0x00001000
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#
+#NV_FTW_WROK
+#
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x007e8000|0x00018000
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#
+#NV_FTW_SPARE
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.uni b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.uni
new file mode 100644
index 0000000..49e527b
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.uni
@@ -0,0 +1,13 @@
+// /** @file
+// SiFive U540 HiFive Unleashed Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_PACKAGE_ABSTRACT #language en-US "Provides SiFIve Freedom U540 HiFive Unleashed platform modules and libraries"
+
+#string STR_PACKAGE_DESCRIPTION #language en-US "This Package SiFIve Freedom U540 HiFive Unleashed platform modules and libraries."
--git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540PkgExtra.uni b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540PkgExtra.uni
new file mode 100644
index 0000000..dc18f91
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540PkgExtra.uni
@@ -0,0 +1,12 @@
+// /** @file
+// SiFive U540 Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_PACKAGE_NAME
+#language en-US
+"SiFive Freedom U540 HiFive Unleashed board package"
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 13/18] FreedomU500VC707Board/PlatformPei: Platform initialization PEI module.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (11 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 12/18] U5SeriesPkg/FreedomU540HiFiveUnleashedBoard: Add SiFive U540 platform Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 14/18] FreedomU500VC707Board/OpensbiPlatformLib: OpenSBI platform interface Abner Chang
` (5 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
PEI module for U500 platform initialization.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../Universal/Pei/PlatformPei/PlatformPei.inf | 73 +++++
.../Universal/Pei/PlatformPei/Platform.h | 86 ++++++
.../Universal/Pei/PlatformPei/Fv.c | 51 ++++
.../Universal/Pei/PlatformPei/MemDetect.c | 74 +++++
.../Universal/Pei/PlatformPei/Platform.c | 310 +++++++++++++++++++++
5 files changed, 594 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.h
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Fv.c
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/MemDetect.c
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf
new file mode 100644
index 0000000..92ee054
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf
@@ -0,0 +1,73 @@
+## @file
+# Platform PEI driver
+#
+# This module provides platform specific function to detect boot mode.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformPei
+ FILE_GUID = 222c386d-5abc-4fb4-b124-fbb82488acf4
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializePlatform
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Fv.c
+ MemDetect.c
+ Platform.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+ RiscVPkg/RiscVPkg.dec
+ Silicon/SiFive/SiFive.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Guids]
+ gEfiMemoryTypeInformationGuid
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ IoLib
+ PciLib
+ PeiResourcePublicationLib
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ PeimEntryPoint
+ PcdLib
+ SiliconSiFiveU5MCCoreplexInfoLib
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize
+ gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported
+
+
+[Ppis]
+ gEfiPeiMasterBootModePpiGuid
+
+[Depex]
+ TRUE
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.h b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.h
new file mode 100644
index 0000000..c2cdd6d
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.h
@@ -0,0 +1,86 @@
+/** @file
+ Platform PEI module include file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_PEI_H_INCLUDED_
+#define PLATFORM_PEI_H_INCLUDED_
+
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddIoMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddUntestedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddReservedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ );
+
+VOID
+AddUntestedMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ );
+
+VOID
+AddressWidthInitialization (
+ VOID
+ );
+
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ );
+
+UINT32
+GetSystemMemorySizeBelow4gb (
+ VOID
+ );
+
+VOID
+InitializeRamRegions (
+ VOID
+ );
+
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ );
+
+EFI_STATUS
+InitializeXen (
+ VOID
+ );
+
+#endif // _PLATFORM_PEI_H_INCLUDED_
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Fv.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Fv.c
new file mode 100644
index 0000000..060d662
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Fv.c
@@ -0,0 +1,51 @@
+/** @file
+ Build FV related hobs for platform.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PiPei.h"
+#include "Platform.h"
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+
+/**
+ Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+ and DXE know about them.
+
+ @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.
+
+**/
+EFI_STATUS
+PeiFvInitialization (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
+ //
+ // Let DXE know about the DXE FV
+ //
+ BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
+ DEBUG ((DEBUG_INFO, "Platform builds DXE FV at %x, size %x.\n",
+ PcdGet32 (PcdRiscVDxeFvBase),
+ PcdGet32 (PcdRiscVDxeFvSize)));
+
+ //
+ // Let PEI know about the DXE FV so it can find the DXE Core
+ //
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
+ PcdGet32 (PcdRiscVDxeFvSize),
+ NULL,
+ NULL
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/MemDetect.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/MemDetect.c
new file mode 100644
index 0000000..dc99f2e
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/MemDetect.c
@@ -0,0 +1,74 @@
+/**@file
+ Memory Detection for Virtual Machines.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+Module Name:
+
+ MemDetect.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/ResourcePublicationLib.h>
+
+#include "Platform.h"
+
+
+/**
+ Publish PEI core memory
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+PublishPeiMemory (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS MemoryBase;
+ UINT64 MemorySize;
+
+ MemoryBase = 0x80000000UL + 0x1000000UL;
+ MemorySize = 0x40000000UL - 0x1000000UL; //1GB - 16MB
+
+ DEBUG((DEBUG_INFO, "%a: MemoryBase:0x%x MemorySize:%d\n", __FUNCTION__, MemoryBase, MemorySize));
+
+ //
+ // Publish this memory to the PEI Core
+ //
+ Status = PublishSystemMemory(MemoryBase, MemorySize);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Publish system RAM and reserve memory regions
+
+**/
+VOID
+InitializeRamRegions (
+ VOID
+ )
+{
+ AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL);
+
+}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c
new file mode 100644
index 0000000..3d3f67d
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c
@@ -0,0 +1,310 @@
+/**@file
+ Platform PEI driver
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ResourcePublicationLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Ppi/MasterBootMode.h>
+#include <IndustryStandard/Pci22.h>
+
+#include <SiFiveU5MCCoreplex.h>
+
+#include "Platform.h"
+
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIMemoryNVS, 0x004 },
+ { EfiACPIReclaimMemory, 0x008 },
+ { EfiReservedMemoryType, 0x004 },
+ { EfiRuntimeServicesData, 0x024 },
+ { EfiRuntimeServicesCode, 0x030 },
+ { EfiBootServicesCode, 0x180 },
+ { EfiBootServicesData, 0xF00 },
+ { EfiMaxMemoryType, 0x000 }
+};
+
+
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiMasterBootModePpiGuid,
+ NULL
+ }
+};
+
+STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+VOID
+AddIoMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddReservedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_RESERVED,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddIoMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+
+VOID
+AddMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+
+VOID
+AddMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+
+VOID
+AddUntestedMemoryBaseSizeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ UINT64 MemorySize
+ )
+{
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
+ MemoryBase,
+ MemorySize
+ );
+}
+
+VOID
+AddUntestedMemoryRangeHob (
+ EFI_PHYSICAL_ADDRESS MemoryBase,
+ EFI_PHYSICAL_ADDRESS MemoryLimit
+ )
+{
+ AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
+}
+
+VOID
+AddPciResource (
+ VOID
+ )
+{
+ //
+ // Platform-specific
+ //
+}
+
+VOID
+MemMapInitialization (
+ VOID
+ )
+{
+ //
+ // Create Memory Type Information HOB
+ //
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ mDefaultMemoryTypeInformation,
+ sizeof(mDefaultMemoryTypeInformation)
+ );
+
+ //
+ // Add PCI IO Port space available for PCI resource allocations.
+ //
+ AddPciResource ();
+}
+
+VOID
+MiscInitialization (
+ VOID
+ )
+{
+ //
+ // Build the CPU HOB with guest RAM size dependent address width and 16-bits
+ // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
+ // S3 resume as well, so we build it unconditionally.)
+ //
+ BuildCpuHob (32, 32);
+}
+
+/**
+ Check if system retunrs from S3.
+
+ @return BOOLEAN TRUE, system returned from S3
+ FALSE, system is not returned from S3
+
+**/
+BOOLEAN
+CheckResumeFromS3 (
+ VOID
+ )
+{
+ //
+ //Platform implementation-specific
+ //
+ return FALSE;
+}
+
+
+VOID
+BootModeInitialization (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ if (CheckResumeFromS3 () == TRUE) {
+ DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "This is normal boot\n"));
+ }
+ Status = PeiServicesSetBootMode (mBootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PeiServicesInstallPpi (mPpiBootMode);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Build processor information for U54 Coreplex processor.
+
+ @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildCoreInformationHob (
+ VOID
+)
+{
+ EFI_STATUS Status;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;
+
+ Status = CreateU5MCCoreplexProcessorSpecificDataHob (0);
+ if (EFI_ERROR (Status)) {
+ ASSERT(FALSE);
+ }
+ Status = CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr);
+ if (EFI_ERROR (Status)) {
+ ASSERT(FALSE);
+ }
+
+ DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", SmbiosHobPtr));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Perform Platform PEI initialization.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializePlatform (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
+
+ BootModeInitialization ();
+ DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n"));
+ PublishPeiMemory ();
+ DEBUG ((DEBUG_INFO, "PEI memory published.\n"));
+ InitializeRamRegions ();
+ DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n"));
+
+ if (mBootMode != BOOT_ON_S3_RESUME) {
+ PeiFvInitialization ();
+ MemMapInitialization ();
+ }
+
+ MiscInitialization ();
+ Status = BuildCoreInformationHob ();
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n"));
+ ASSERT(FALSE);
+ }
+ return EFI_SUCCESS;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 14/18] FreedomU500VC707Board/OpensbiPlatformLib: OpenSBI platform interface.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (12 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 13/18] FreedomU500VC707Board/PlatformPei: Platform initialization PEI module Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 15/18] U5SeriesPkg/FreedomU500VC707Board: Add SiFive U500 platform Abner Chang
` (4 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
This is OpenSBI platform code implementation of U500 platform.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 52 +++++
.../Library/OpensbiPlatformLib/Platform.c | 213 +++++++++++++++++++++
2 files changed, 265 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
new file mode 100644
index 0000000..60aec6d
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -0,0 +1,52 @@
+## @file
+# RISC-V OpenSBI Platform Library
+# This is the the library which provides platform
+# level opensbi functions follow RISC-V OpenSBI implementation.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVOpensbiPlatformLib
+ FILE_GUID = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVOpensbiPlatformLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Platform.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DebugAgentLib
+ FdtLib
+ PcdLib
+ PrintLib
+ RiscVCpuLib
+
+[FixedPcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
+
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c
new file mode 100644
index 0000000..bcdb643
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c
@@ -0,0 +1,213 @@
+/*
+ *
+ * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Atish Patra <atish.patra@wdc.com>
+ */
+
+#include <libfdt.h>
+#include <fdt.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/riscv_io.h>
+#include <sbi_utils/irqchip/plic.h>
+#include <sbi_utils/serial/sifive-uart.h>
+#include <sbi_utils/sys/clint.h>
+#include <U5Clint.h>
+
+#define U500_HART_COUNT FixedPcdGet32(PcdHartCount)
+#define U500_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize)
+#define U500_BOOT_HART_ID FixedPcdGet32(PcdBootHartId)
+
+#define U500_SYS_CLK 100000000
+
+#define U500_PLIC_ADDR 0xc000000
+#define U500_PLIC_NUM_SOURCES 0x35
+#define U500_PLIC_NUM_PRIORITIES 7
+
+#define U500_UART_ADDR FixedPcdGet32(PcdU5UartBase)
+
+#define U500_UART_BAUDRATE 115200
+
+/**
+ * The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode.
+ * HARTs 1 is selected as boot HART
+ */
+#ifndef U500_ENABLED_HART_MASK
+#define U500_ENABLED_HART_MASK (1 << U500_BOOT_HART_ID)
+#endif
+
+#define U500_HARTID_DISABLED ~(U500_ENABLED_HART_MASK)
+
+/* PRCI clock related macros */
+//TODO: Do we need a separate driver for this ?
+#define U500_PRCI_BASE_ADDR 0x10000000
+#define U500_PRCI_CLKMUXSTATUSREG 0x002C
+#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
+
+static void U500_modify_dt(void *fdt)
+{
+ u32 i, size;
+ int chosen_offset, err;
+ int cpu_offset;
+ char cpu_node[32] = "";
+ const char *mmu_type;
+
+ for (i = 0; i < U500_HART_COUNT; i++) {
+ sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
+ cpu_offset = fdt_path_offset(fdt, cpu_node);
+ mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL);
+ if (mmu_type && (!AsciiStrCmp(mmu_type, "riscv,sv39") ||
+ !AsciiStrCmp(mmu_type,"riscv,sv48")))
+ continue;
+ else
+ fdt_setprop_string(fdt, cpu_offset, "status", "masked");
+ memset(cpu_node, 0, sizeof(cpu_node));
+ }
+ size = fdt_totalsize(fdt);
+ err = fdt_open_into(fdt, fdt, size + 256);
+ if (err < 0)
+ sbi_printf("Device Tree can't be expanded to accmodate new node");
+
+ chosen_offset = fdt_path_offset(fdt, "/chosen");
+ fdt_setprop_string(fdt, chosen_offset, "stdout-path",
+ "/soc/serial@10010000:115200");
+
+ plic_fdt_fixup(fdt, "riscv,plic0");
+}
+
+static int U500_final_init(bool cold_boot)
+{
+ void *fdt;
+
+ if (!cold_boot)
+ return 0;
+
+ fdt = sbi_scratch_thishart_arg1_ptr();
+ U500_modify_dt(fdt);
+
+ return 0;
+}
+
+static u32 U500_pmp_region_count(u32 hartid)
+{
+ return 1;
+}
+
+static int U500_pmp_region_info(u32 hartid, u32 index,
+ ulong *prot, ulong *addr, ulong *log2size)
+{
+ int ret = 0;
+
+ switch (index) {
+ case 0:
+ *prot = PMP_R | PMP_W | PMP_X;
+ *addr = 0;
+ *log2size = __riscv_xlen;
+ break;
+ default:
+ ret = -1;
+ break;
+ };
+
+ return ret;
+}
+
+static int U500_console_init(void)
+{
+ unsigned long peri_in_freq;
+
+ peri_in_freq = U500_SYS_CLK/2;
+ return sifive_uart_init(U500_UART_ADDR, peri_in_freq, U500_UART_BAUDRATE);
+}
+
+static int U500_irqchip_init(bool cold_boot)
+{
+ int rc;
+ u32 hartid = sbi_current_hartid();
+
+ if (cold_boot) {
+ rc = plic_cold_irqchip_init(U500_PLIC_ADDR,
+ U500_PLIC_NUM_SOURCES,
+ U500_HART_COUNT);
+ if (rc)
+ return rc;
+ }
+
+ return plic_warm_irqchip_init(hartid,
+ (hartid) ? (2 * hartid - 1) : 0,
+ (hartid) ? (2 * hartid) : -1);
+}
+
+static int U500_ipi_init(bool cold_boot)
+{
+ int rc;
+
+ if (cold_boot) {
+ rc = clint_cold_ipi_init(CLINT_REG_BASE_ADDR,
+ U500_HART_COUNT);
+ if (rc)
+ return rc;
+
+ }
+
+ return clint_warm_ipi_init();
+}
+
+static int U500_timer_init(bool cold_boot)
+{
+ int rc;
+
+ if (cold_boot) {
+ rc = clint_cold_timer_init(CLINT_REG_BASE_ADDR,
+ U500_HART_COUNT);
+ if (rc)
+ return rc;
+ }
+
+ return clint_warm_timer_init();
+}
+
+static int U500_system_down(u32 type)
+{
+ /* For now nothing to do. */
+ return 0;
+}
+
+const struct sbi_platform_operations platform_ops = {
+ .pmp_region_count = U500_pmp_region_count,
+ .pmp_region_info = U500_pmp_region_info,
+ .final_init = U500_final_init,
+ .console_putc = sifive_uart_putc,
+ .console_getc = sifive_uart_getc,
+ .console_init = U500_console_init,
+ .irqchip_init = U500_irqchip_init,
+ .ipi_send = clint_ipi_send,
+ .ipi_clear = clint_ipi_clear,
+ .ipi_init = U500_ipi_init,
+ .timer_value = clint_timer_value,
+ .timer_event_stop = clint_timer_event_stop,
+ .timer_event_start = clint_timer_event_start,
+ .timer_init = U500_timer_init,
+ .system_reboot = U500_system_down,
+ .system_shutdown = U500_system_down
+};
+
+const struct sbi_platform platform = {
+ .opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on.
+ .platform_version = SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI Platform version 1.0
+ .name = "SiFive Freedom U500",
+ .features = SBI_PLATFORM_DEFAULT_FEATURES,
+ .hart_count = U500_HART_COUNT,
+ .hart_stack_size = U500_HART_STACK_SIZE,
+ .disabled_hart_mask = U500_HARTID_DISABLED,
+ .platform_ops_addr = (unsigned long)&platform_ops
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 15/18] U5SeriesPkg/FreedomU500VC707Board: Add SiFive U500 platform.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (13 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 14/18] FreedomU500VC707Board/OpensbiPlatformLib: OpenSBI platform interface Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 16/18] SiFive/U5SeriesPkg Add U5SeriesPkg Abner Chang
` (3 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
Initial version of SiFive U500 VC707 platform.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../U5SeriesPkg/FreedomU500VC707Board/U500.dec | 25 +
.../U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 543 +++++++++++++++++++++
.../U5SeriesPkg/FreedomU500VC707Board/U500.fdf | 336 +++++++++++++
.../U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc | 55 +++
.../FreedomU500VC707Board/VarStore.fdf.inc | 78 +++
.../U5SeriesPkg/FreedomU500VC707Board/U500.uni | 13 +
| 12 +
7 files changed, 1062 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dec
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.uni
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500PkgExtra.uni
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dec b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dec
new file mode 100644
index 0000000..706e086
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dec
@@ -0,0 +1,25 @@
+## @file U500.dec
+# This Package provides SiFive U500 modules and libraries.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = U500
+ PACKAGE_UNI_FILE = U500.uni
+ PACKAGE_GUID = D11E9DB9-5940-4642-979D-2114342140D2
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+
+[LibraryClasses]
+
+[Guids]
+ gUefiRiscVPlatformU500PkgTokenSpaceGuid = {0xDFD87009, 0x27A1, 0x41DD, { 0x84, 0xB1, 0x35, 0xB4, 0xB9, 0x0D, 0x17, 0x63 }}
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ U500PkgExtra.uni
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
new file mode 100644
index 0000000..231e15a
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -0,0 +1,543 @@
+## @file
+# RISC-V EFI on SiFive VC707 (U500) RISC-V platform
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = FreedomU500VC707
+ PLATFORM_GUID = 0955581C-2A6A-48F7-8690-9D275AE884F8
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001c
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = RISCV64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
+
+ #
+ # Enable below options may cause build error or may not work on
+ # the initial version of RISC-V package
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ DEFINE SECURE_BOOT_ENABLE = FALSE
+ DEFINE DEBUG_ON_SERIAL_PORT = TRUE
+
+ #
+ # Network definition
+ #
+ DEFINE NETWORK_SNP_ENABLE = FALSE
+ DEFINE NETWORK_IP6_ENABLE = FALSE
+ DEFINE NETWORK_TLS_ENABLE = FALSE
+ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
+ DEFINE NETWORK_ISCSI_ENABLE = FALSE
+
+[BuildOptions]
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable
+!endif
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses]
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ SerialPortLib|Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+ SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+
+# RISC-V Platform Library
+ TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf
+ RealTimeClockLib|EmbeddedPkg//Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
+
+# RISC-V Core Library
+ RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+ DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
+!else
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+!endif
+
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+ TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+ AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+!else
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+!endif
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+!if $(HTTP_BOOT_ENABLE) == TRUE
+ HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
+!endif
+
+# ACPI not supported yet.
+ #S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
+ SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
+ OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+
+[LibraryClasses.common]
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+!endif
+ RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
+ RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
+ CpuExceptionHandlerLib|RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+
+[LibraryClasses.common.SEC]
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
+!endif
+
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+#
+# OpenSBi Platform Library
+#
+ RiscVOpensbiPlatformLib|Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+
+[LibraryClasses.common.PEIM]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
+!endif
+ FirmwareContextProcessorSpecificLib|RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
+ RiscVPlatformDxeIplLib|RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
+
+#
+# RISC-V core libraries
+#
+ SiliconSiFiveE51CoreInfoLib|Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+ SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+ SiliconSiFiveU5MCCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+ #CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ PlatformBootManagerLib|RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ PlatformMemoryTestLib|RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
+ PlatformUpdateProgressLib|RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+!ifdef $(DEBUG_ON_SERIAL_PORT)
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+[PcdsFeatureFlag]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+
+[PcdsFixedAtBuild]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+!endif
+
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
+!endif
+
+ #gUefiPayloadPkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot
+ gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
+ gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
+ gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
+!endif
+
+ #
+ # F2 for UI APP
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+################################################################################
+#
+# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsDynamicDefault]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
+
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0
+
+ # Set video resolution for text setup.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components]
+
+ #
+ # SEC Phase modules
+ #
+ RiscVPlatformPkg/Universal/Sec/SecMain.inf
+
+ #
+ # PEI Phase modules
+ #
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+ MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ }
+
+ #
+ # DXE Phase modules
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg//Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ }
+
+ MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
+ <LibraryClasses>
+ NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
+ }
+!else
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+!endif
+
+ #
+ # EBC not supported on RISC-V yet
+ #
+ #MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
+
+ UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
+ MdeModulePkg/Universal/Metronome/Metronome.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf {
+ <LibraryClasses>
+ ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf
+ }
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # RISC-V Platform module
+ #
+ Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
+ Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
+
+ #
+ # RISC-V Core module
+ #
+ RiscVPkg/Universal/CpuDxe/CpuDxe.inf
+ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
+
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+
+# No graphic console supported yet.
+# MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf {
+# <LibraryClasses>
+# PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+# }
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf {
+ <LibraryClasses>
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+ #
+ # ACPI Support
+ # Not support on RISC-V yet
+ #
+ #MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ #MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+
+ #
+ # Network Support
+ #
+ !include NetworkPkg/Network.dsc.inc
+
+ #
+ # Usb Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!endif
+
+ MdeModulePkg/Application/UiApp/UiApp.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
new file mode 100644
index 0000000..5f52c03
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
@@ -0,0 +1,336 @@
+# @file
+# Flash definition file on SiFive VC707 (U500) RISC-V platform
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+#
+# Platform definitions
+#
+!include U500.fdf.inc
+
+#
+# Build the variable store and the firmware code as one unified flash device
+# image.
+#
+[FD.U500]
+BaseAddress = $(FW_BASE_ADDRESS)
+Size = $(FW_SIZE)
+ErasePolarity = 1
+BlockSize = $(BLOCK_SIZE)
+NumBlocks = $(FW_BLOCKS)
+
+$(SECFV_OFFSET)|$(SECFV_SIZE)
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize
+FV = SECFV
+
+$(PEIFV_OFFSET)|$(PEIFV_SIZE)
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize
+FV = PEIFV
+
+$(FVMAIN_OFFSET)|$(FVMAIN_SIZE)
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
+FV = FVMAIN_COMPACT
+
+!include VarStore.fdf.inc
+
+################################################################################
+
+[FV.SECFV]
+BlockSize = 0x1000
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+#
+# SEC Phase modules
+#
+# The code in this FV handles the initial firmware startup, and
+# decompresses the PEI and DXE FVs which handles the rest of the boot sequence.
+#
+INF RiscVPlatformPkg/Universal/Sec/SecMain.inf
+
+################################################################################
+[FV.PEIFV]
+BlockSize = 0x10000
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+APRIORI PEI {
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+}
+
+#
+# PEI Phase modules
+#
+INF MdeModulePkg/Core/Pei/PeiMain.inf
+INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
+INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+# RISC-V Platform PEI Driver
+INF Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf
+
+################################################################################
+
+[FV.DXEFV]
+BlockSize = 0x10000
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+APRIORI DXE {
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
+}
+
+#
+# DXE Phase modules
+#
+INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+INF MdeModulePkg/Universal/Metronome/Metronome.inf
+INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+# RISC-V Platform Drivers
+INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
+
+# RISC-V Core Drivers
+INF Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
+INF RiscVPkg/Universal/CpuDxe/CpuDxe.inf
+INF RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
+
+INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!endif
+
+INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+#INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
+INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+
+!ifndef $(SOURCE_DEBUG_ENABLE)
+INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+!endif
+
+INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+#
+# ACPI is not supported yet on RISC-V package.
+#
+#INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+#INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+#INF PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf
+
+#INF RuleOverride = BINARY FatBinPkg/EnhancedFatDxe/Fat.inf
+
+INF ShellPkg/Application/Shell/Shell.inf
+
+#
+# Network modules
+#
+!if $(E1000_ENABLE)
+ FILE DRIVER = 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 {
+ SECTION PE32 = Intel3.5/EFIX64/E3507X2.EFI
+ }
+!endif
+
+!include NetworkPkg/Network.fdf.inc
+
+#
+# Usb Support
+#
+INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+################################################################################
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = 27A72E80-3118-4c0c-8673-AA5B4EFA9613
+
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ #
+ # These firmware volumes will have files placed in them uncompressed,
+ # and then both firmware volumes will be compressed in a single
+ # compression operation in order to achieve better overall compression.
+ #
+ SECTION FV_IMAGE = DXEFV
+ }
+ }
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 Align=4K |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 Align=4K |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ }
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
new file mode 100644
index 0000000..936ff22
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
@@ -0,0 +1,55 @@
+## @file
+# Definitions of Flash definition file on SiFive VC707 (U500) RISC-V platform
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+[Defines]
+DEFINE BLOCK_SIZE = 0x1000
+
+DEFINE FW_BASE_ADDRESS = 0x80000000
+DEFINE FW_SIZE = 0x00800000
+DEFINE FW_BLOCKS = 0x800
+
+#
+# 0x000000-0x7DFFFF code
+# 0x7E0000-0x800000 variables
+#
+DEFINE CODE_BASE_ADDRESS = 0x80000000
+DEFINE CODE_SIZE = 0x007E0000
+DEFINE CODE_BLOCKS = 0x7E0
+DEFINE VARS_BLOCKS = 0x20
+
+DEFINE SECFV_OFFSET = 0x00000000
+DEFINE SECFV_SIZE = 0x00020000
+DEFINE PEIFV_OFFSET = 0x00020000
+DEFINE PEIFV_SIZE = 0x00080000
+DEFINE SCRATCH_OFFSET = 0x000a0000
+DEFINE SCRATCH_SIZE = 0x00010000
+DEFINE FVMAIN_OFFSET = 0x00100000 # Must be power of 2 for PMP setting
+DEFINE FVMAIN_SIZE = 0x0018C000
+DEFINE VARS_OFFSET = 0x007E0000
+DEFINE VARS_SIZE = 0x00020000
+
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress = $(FW_BASE_ADDRESS) + $(VARS_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize = $(VARS_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize = $(BLOCK_SIZE)
+
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress = $(CODE_BASE_ADDRESS)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress = $(CODE_BASE_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize = 8192
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase = $(CODE_BASE_ADDRESS) + $(SCRATCH_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize = $(SCRATCH_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase = $(CODE_BASE_ADDRESS) + $(FW_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize = 0x10000
+
+
+SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz = 1000000
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount = 4 # Total cores on U500 platform
+SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores = 4 # Total U5 cores enabled on U500 platform
+SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported = False # Enable optional E51 MC core?
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId = 0 # Boot hart ID
+
+SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase = 0x54000000
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
new file mode 100644
index 0000000..c287bb4
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
@@ -0,0 +1,78 @@
+## @file
+# FDF include file with Layout Regions that define an empty variable store.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+$(VARS_OFFSET)|0x00007000
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#
+# NV_VARIABLE_STORE
+#
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0x20000
+ 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0x39, 0xF1, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block
+ 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ # Signature: gEfiAuthenticatedVariableGuid =
+ # { 0xaaf32c78, 0x947b, 0x439a,
+ # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+!else
+ # Signature: gEfiVariableGuid =
+ # { 0xddcf3616, 0x3275, 0x4164,
+ # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+!endif
+ # Size: 0x7000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x6fb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0x6F, 0x00, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x007e7000|0x00001000
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#
+#NV_FTW_WROK
+#
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x007e8000|0x00018000
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#
+#NV_FTW_SPARE
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.uni b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.uni
new file mode 100644
index 0000000..7ac1096
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.uni
@@ -0,0 +1,13 @@
+// /** @file
+// SiFive U500 Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_PACKAGE_ABSTRACT #language en-US "Provides SiFIve RISC-V U500 platform modules and libraries"
+
+#string STR_PACKAGE_DESCRIPTION #language en-US "This Package SiFIve RISC-V U500 platform modules and libraries."
--git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500PkgExtra.uni b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500PkgExtra.uni
new file mode 100644
index 0000000..6b68fb4
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500PkgExtra.uni
@@ -0,0 +1,12 @@
+// /** @file
+// SiFive U500 Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_PACKAGE_NAME
+#language en-US
+"SiFive U500 package"
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 16/18] SiFive/U5SeriesPkg Add U5SeriesPkg.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (14 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 15/18] U5SeriesPkg/FreedomU500VC707Board: Add SiFive U500 platform Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 17/18] edk2-platforms: Update Readme.md for RISC-V platform Abner Chang
` (2 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 8624 bytes --]
Initial U5SeriesPkg for U5 series platforms.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec | 33 +++++++
Platform/SiFive/U5SeriesPkg/Readme.md | 110 +++++++++++++++++++++++
Platform/SiFive/U5SeriesPkg/U5SeriesPkg.uni | 13 +++
| 12 +++
4 files changed, 168 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
create mode 100644 Platform/SiFive/U5SeriesPkg/Readme.md
create mode 100644 Platform/SiFive/U5SeriesPkg/U5SeriesPkg.uni
create mode 100644 Platform/SiFive/U5SeriesPkg/U5SeriesPkgExtra.uni
diff --git a/Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec b/Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
new file mode 100644
index 0000000..a01135b
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
@@ -0,0 +1,33 @@
+## @file U5SeriesPkg.dec
+# This Package provides modules and libraries.for SiFive U5 series platforms.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = U5SeriesPkg
+ PACKAGE_UNI_FILE = U5SeriesPkg.uni
+ PACKAGE_GUID = AD6E43CA-7FED-4CEA-8151-68B2C5F12B3A
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+ Include
+
+[LibraryClasses]
+
+[Guids]
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid = {0x725B804B, 0x10B5, 0x4326, { 0xAD, 0xFF, 0x59, 0xCE, 0x6E, 0xFD, 0x5B, 0x36 }}
+
+[PcdsFixedAtBuild]
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores|0x8|UINT32|0x00001000
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported|TRUE|BOOLEAN|0x00001001
+ gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase|0x0|UINT32|0x00001002
+
+[PcdsPatchableInModule]
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ U5SeriesPkg.uni
diff --git a/Platform/SiFive/U5SeriesPkg/Readme.md b/Platform/SiFive/U5SeriesPkg/Readme.md
new file mode 100644
index 0000000..535fa9d
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Readme.md
@@ -0,0 +1,110 @@
+# Introduction
+U5SeriesPkg provides the common EFI library and driver modules for SiFive
+U5 series core platforms. Currently the supported platforms are Freedom
+U500 VC707 platform and Freedom U540 HiFive Unleashed platform.
+
+Both platforms are built with below common packages,
+- **U5SeriesPkg**, edk2 platform branch
+ (Currently is in edk2-platforms/devel-riscv-v2-PATCHv5 branch)
+- **RiscVPlatformPkg**, edk2 master branch
+ (Currently is in edk2-staging/RISC-V-V2 branch)
+- **RiscVPkg**, edk2 master branch
+ (Currently is in edk2-staging/RISC-V-V2 branch)
+
+## U500 Platform
+This is a sample RISC-V EDK2 platform package used agaist SiFive Freedom U500
+VC707 FPGA Dev Kit, please refer to "SiFive Freedom U500 VC707 FPGA Getting
+Started Guide" on https://www.sifive.com/documentation.
+
+## U540 Platform
+This is a sample RISC-V EDK2 platform package used agaist SiFive Freedom U540
+HiFive Unleashed development board, please refer to "SiFive Freedom U540-C000
+Manual" on https://www.sifive.com.
+The binary built from Platform/SiFive/FreedomU540HiFiveUnleashedBoard can run
+on main stream [QEMU](https://git.qemu.org/?p=qemu.git;a=summary)
+using qemu-system-riscv64 under riscv64-softmmu. Launch the binary with
+
+```
+-cpu sifive-u54 -machine sifive_u
+```
+
+## Download the sources
+```
+git clone https://github.com/tianocore/edk2-staging.git
+# Checkout RISC-V-V2 branch
+git clone https://github.com/tianocore/edk2-platforms.git
+# Checkout devel-riscv-v2-PATCHv5 branch
+git clone https://github.com/tianocore/edk2-non-osi.git
+```
+
+## Platform Owners
+Chang, Abner <abner.chang@hpe.com>
+Chen, Gilbert <gilbert.chen@hpe.com>
+
+## Platform Status
+Currently the binary built from U500Pkg can boot SiFive Freedom U500 VC707
+FPGA to EFI shell with console in/out enabled.
+
+## Linux Build Instructions
+You can build the RISC-V platform using below script,
+`build -a RISCV64 -t GCC5 -p Platform/SiFive/FreedomU500VC707Board/U500.dsc`
+
+## Supported Operating Systems
+Only support to boot to EFI Shell so far.
+
+## Known Issues and Limitations
+Only RISC-V RV64 is verified on this platform.
+
+## Related Materials
+- [RISC-V OpenSbi](https://github.com/riscv/opensbi)
+- [SiFive U500 VC707 FPGA Getting Started Guide](https://sifive.cdn.prismic.io/sifive%2Fc248fabc-5e44-4412-b1c3-6bb6aac73a2c_sifive-u500-vc707-gettingstarted-v0.2.pdf)
+- [SiFive Freedom U540-C000 Manual](https://sifive.cdn.prismic.io/sifive%2F834354f0-08e6-423c-bf1f-0cb58ef14061_fu540-c000-v1.0.pdf)
+- [SiFive RISC-V Core Document](https://www.sifive.com/documentation)
+
+## U5SeriesPkg Libraries and Drivers
+### PeiCoreInfoHobLib
+This is the library to create RISC-V core characteristics for building up
+RISC-V related SMBIOS records to support the unified boot loader and OS image.
+This library leverage the silicon libraries provided in Silicon/SiFive.
+
+### RiscVPlatformTimerLib
+This is common U5 series platform timer library which has the
+platform-specific timer implementation.
+
+### TimerDxe
+This is U5 series platform timer DXE driver whcih has the platform-specific
+timer implementation.
+
+## U500 Platform Libraries and Drivers
+### RiscVOpnesbiPlatformLib
+In order to reduce the dependencies with RISC-V OpenSBI project
+(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the
+implementation of RISC-V EDK2 platform is leverage platform source code from
+OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from
+RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build
+environment.
+
+### PlatformPei
+This is the platform-implementation specific library which is executed in early
+PEI phase for U500 platform initialization.
+
+## U540 Platform Libraries and Drivers
+### RiscVOpnesbiPlatformLib
+In order to reduce the dependencies with RISC-V OpenSBI project
+(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the
+implementation of RISC-V EDK2 platform is leverage platform source code from
+OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from
+RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build
+environment.
+
+### PlatformPei
+This is the platform-implementation specific library which is executed in early
+PEI phase for U540 platform initialization.
+
+## U5SeriesPkg Platform PCD settings
+
+| **PCD name** |**Usage**|
+|----------------|----------|
+|PcdNumberofU5Cores| Number of U5 core enabled on U5 series platform|
+|PcdE5MCSupported| Indicates whether the Monitor Core (E5) is supported on U5 series platform|
+|PcdU5UartBase|Platform serial port base address|
diff --git a/Platform/SiFive/U5SeriesPkg/U5SeriesPkg.uni b/Platform/SiFive/U5SeriesPkg/U5SeriesPkg.uni
new file mode 100644
index 0000000..12e8c15
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/U5SeriesPkg.uni
@@ -0,0 +1,13 @@
+// /** @file
+// SiFive U5 Series Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_PACKAGE_ABSTRACT #language en-US "Provides SiFIve RISC-V U5 series platform modules and libraries"
+
+#string STR_PACKAGE_DESCRIPTION #language en-US "This Package SiFIve RISC-V U5 series platform modules and libraries."
--git a/Platform/SiFive/U5SeriesPkg/U5SeriesPkgExtra.uni b/Platform/SiFive/U5SeriesPkg/U5SeriesPkgExtra.uni
new file mode 100644
index 0000000..244595a
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/U5SeriesPkgExtra.uni
@@ -0,0 +1,12 @@
+// /** @file
+// SiFive U5 Series Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_PACKAGE_NAME
+#language en-US
+"SiFive U5 series platform package"
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 17/18] edk2-platforms: Update Readme.md for RISC-V platform.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (15 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 16/18] SiFive/U5SeriesPkg Add U5SeriesPkg Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 18/18] edk2-platforms: Update Maintainers file Abner Chang
2019-11-26 15:22 ` [edk2-devel] [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Leif Lindholm
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
Update Readme.md for RISC-V platforms.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Readme.md | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Readme.md b/Readme.md
index efdbe85..64f2a29 100644
--- a/Readme.md
+++ b/Readme.md
@@ -52,6 +52,7 @@ ARM | arm-linux-gnueabihf-
IA32 | i?86-linux-gnu-* _or_ x86_64-linux-gnu-
IPF | ia64-linux-gnu
X64 | x86_64-linux-gnu-
+RISCV64 | riscv64-unknown-elf-
\* i386, i486, i586 or i686
@@ -62,6 +63,12 @@ and [arm-linux-gnueabihf](https://releases.linaro.org/components/toolchain/binar
compiled to run on x86_64/i686 Linux and i686 Windows. Some Linux distributions
provide their own packaged cross-toolchains.
+### GCC for RISC-V
+RISC-V open source community provides GCC toolchains for
+[riscv64-unknown-elf](https://github.com/riscv/riscv-gnu-toolchain)
+compiled to run on x86 Linux. The commit ID 64879b24 is verified to build RISC-V EDK2 platform and boot to EFI
+SHELL successfully.
+
### clang
Clang does not require separate cross compilers, but it does need a
target-specific binutils. These are included with any prepackaged GCC toolchain
@@ -243,6 +250,12 @@ For more information, see the
## Raspberry Pi
* [Pi 3](Platform/RaspberryPi/RPi3)
+## RISC-V
+### SiFive
+* [Sifive U5 Series](Platform/SiFive/U5SeriesPkg) Refer to Platform/SiFive/U5Series/Readme.md on edk2-platform repository.
+* [Freedom U500 VC707 FPGA](Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board)
+* [Freedom U540 HiFive Unleashed](Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard)
+
## Socionext
* [SynQuacer](Platform/Socionext/DeveloperBox)
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [platform/devel-riscv-v2 PATCHv5 18/18] edk2-platforms: Update Maintainers file.
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (16 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 17/18] edk2-platforms: Update Readme.md for RISC-V platform Abner Chang
@ 2019-10-28 4:20 ` Abner Chang
2019-11-26 15:22 ` [edk2-devel] [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Leif Lindholm
18 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-10-28 4:20 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Ard Biesheuvel, Leif Lindholm,
Gilbert Chen, Palmer Dabbelt
Update Maintainers.txt for RISC-V platform.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Maintainers.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Maintainers.txt b/Maintainers.txt
index 1260c8d..8fa695c 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -120,6 +120,18 @@ R: Marcin Wojtas <mw@semihalf.com>
Platform/SolidRun/Armada80x0McBin
R: Marcin Wojtas <mw@semihalf.com>
+Platform/SiFive/U5Series
+F: Abner Chang <abner.chang@hpe.com>
+F: Gilbert Chen <gilbert.chen@hpe.com>
+
+Platform/SiFive/U5Series/FreedomU500VC707Board
+F: Abner Chang <abner.chang@hpe.com>
+F: Gilbert Chen <gilbert.chen@hpe.com>
+
+Platform/SiFive/U5Series/FreedomU540HiFiveUnleashedBoard
+F: Abner Chang <abner.chang@hpe.com>
+F: Gilbert Chen <gilbert.chen@hpe.com>
+
Silicon
M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
M: Leif Lindholm <leif.lindholm@linaro.org>
@@ -176,3 +188,7 @@ M: Liming Gao <liming.gao@intel.com>
Silicon/Marvell
R: Marcin Wojtas <mw@semihalf.com>
+
+Silicon/SiFive
+F: Abner Chang <abner.chang@hpe.com>
+F: Gilbert Chen <gilbert.chen@hpe.com>
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [edk2-devel] [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V
2019-10-28 4:20 [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Abner Chang
` (17 preceding siblings ...)
2019-10-28 4:20 ` [platform/devel-riscv-v2 PATCHv5 18/18] edk2-platforms: Update Maintainers file Abner Chang
@ 2019-11-26 15:22 ` Leif Lindholm
2019-12-22 6:09 ` Abner Chang
18 siblings, 1 reply; 23+ messages in thread
From: Leif Lindholm @ 2019-11-26 15:22 UTC (permalink / raw)
To: devel, abner.chang
Apart from the minor comments I've made, and the fallout from header
wrapper changes, I think this is ready to go into a -devel branch.
I still think the SMBIOS generation code needs to be consolidated, but
sure, let's do that once the code is in the branch.
Regards,
Leif
On Mon, Oct 28, 2019 at 12:20:15 +0800, Abner Chang wrote:
> The is the set of patches for belwo two platforms,
> - SiFive Freedom U500 VC707 FPGA Dev Kit
> - SiFive Freedom U540 HiFive Unleashed development board
> Refer to Readme.md under platforms/SiFive/U5SeriesPkg.
>
> These patches have to be incorporated with RISC-V-V2 pacth v3 of edk2-staging.
>
> Besides of patches, you can also get code from belwo git repository.
> - edk2-platforms for RISC-V platform,
> https://github.com/gilbert225/edk2-platforms/tree/devel-riscv-v2-PATCHv5
> - edk2-staging for RISC-V,
> https://github.com/changab/edk2-staging-riscv/tree/RISC-V-V2-v3
>
> Abner Chang (18):
> Silicon/SiFive: Initial version of SiFive silicon package.
> SiFive/E51: Initial version of SiFive E51 core library.
> SiFive/U54: Initial version of SiFive U54 core library.
> SiFive/U54MC: Initial version of SiFive U54MC Coreplex library.
> U5SeriesPkg/PeiCoreInfoHobLib: Library to create core information.
> U5SeriesPkg/TimerDxe: U5 Series Platform Timer DXE driver.
> U5SeriesPkg/RamFvbServicesRuntimeDxe: Firmware Volume Block service.
> U5SeriesPkg/RiscVPlatformTimerLib: Platform Timer library
> U5SeriesPkg/SerialIoLib: Platform Serial Port library
> FreedomU540HiFiveUnleashedBoard/PlatformPei: Platform PEI for U540
> platform.
> FreedomU540HiFiveUnleashedBoard/OpensbiPlatformLib: OpenSBI platform
> library for U540 platform.
> U5SeriesPkg/FreedomU540HiFiveUnleashedBoard: Add SiFive U540 platform.
> FreedomU500VC707Board/PlatformPei: Platform initialization PEI module.
> FreedomU500VC707Board/OpensbiPlatformLib: OpenSBI platform interface.
> U5SeriesPkg/FreedomU500VC707Board: Add SiFive U500 platform.
> SiFive/U5SeriesPkg Add U5SeriesPkg.
> edk2-platforms: Update Readme.md for RISC-V platform.
> edk2-platforms: Update Maintainers file.
>
> .../U5SeriesPkg/FreedomU500VC707Board/U500.dec | 25 +
> .../FreedomU540HiFiveUnleashedBoard/U540.dec | 25 +
> Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec | 33 +
> Silicon/SiFive/SiFive.dec | 39 +
> .../U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 543 ++++++++++
> .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 543 ++++++++++
> .../U5SeriesPkg/FreedomU500VC707Board/U500.fdf | 336 ++++++
> .../FreedomU540HiFiveUnleashedBoard/U540.fdf | 336 ++++++
> .../U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc | 55 +
> .../FreedomU500VC707Board/VarStore.fdf.inc | 78 ++
> .../FreedomU540HiFiveUnleashedBoard/U540.fdf.inc | 54 +
> .../VarStore.fdf.inc | 78 ++
> .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 52 +
> .../Universal/Pei/PlatformPei/PlatformPei.inf | 73 ++
> .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 52 +
> .../Universal/Pei/PlatformPei/PlatformPei.inf | 72 ++
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 58 +
> .../RiscVPlatformTimerLib.inf | 36 +
> .../Library/SerialIoLib/SerialIoLib.inf | 38 +
> .../FvbServicesRuntimeDxe.inf | 80 ++
> .../Universal/Dxe/TimerDxe/TimerDxe.inf | 53 +
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 47 +
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 48 +
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 46 +
> .../Universal/Pei/PlatformPei/Platform.h | 86 ++
> .../Universal/Pei/PlatformPei/Platform.h | 86 ++
> .../U5SeriesPkg/Include/SiFiveU5MCCoreplex.h | 51 +
> Platform/SiFive/U5SeriesPkg/Include/U5Clint.h | 20 +
> .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h | 187 ++++
> .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.h | 85 ++
> .../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.h | 174 +++
> Silicon/SiFive/Include/Library/SiFiveE51.h | 60 ++
> Silicon/SiFive/Include/Library/SiFiveU54.h | 60 ++
> .../SiFive/Include/Library/SiFiveU54MCCoreplex.h | 55 +
> .../Library/OpensbiPlatformLib/Platform.c | 213 ++++
> .../Universal/Pei/PlatformPei/Fv.c | 51 +
> .../Universal/Pei/PlatformPei/MemDetect.c | 74 ++
> .../Universal/Pei/PlatformPei/Platform.c | 310 ++++++
> .../Library/OpensbiPlatformLib/Platform.c | 213 ++++
> .../Universal/Pei/PlatformPei/Fv.c | 51 +
> .../Universal/Pei/PlatformPei/MemDetect.c | 74 ++
> .../Universal/Pei/PlatformPei/Platform.c | 310 ++++++
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 195 ++++
> .../Library/SerialIoLib/SerialPortLib.c | 253 +++++
> .../Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c | 127 +++
> .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c | 1114 ++++++++++++++++++++
> .../RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c | 150 +++
> .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.c | 145 +++
> .../Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c | 20 +
> .../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c | 304 ++++++
> .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 242 +++++
> .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 290 +++++
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 184 ++++
> Platform/SiFive/U5SeriesPkg/Readme.md | 110 ++
> Readme.md | 13 +
> Maintainers.txt | 16 +
> .../U5SeriesPkg/FreedomU500VC707Board/U500.uni | 13 +
> .../FreedomU500VC707Board/U500PkgExtra.uni | 12 +
> .../FreedomU540HiFiveUnleashedBoard/U540.uni | 13 +
> .../U540PkgExtra.uni | 12 +
> .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.S | 48 +
> .../Library/SerialIoLib/U5SerialPortLib.uni | 16 +
> Platform/SiFive/U5SeriesPkg/U5SeriesPkg.uni | 13 +
> Platform/SiFive/U5SeriesPkg/U5SeriesPkgExtra.uni | 12 +
> .../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.uni | 14 +
> .../Universal/Dxe/TimerDxe/TimerExtra.uni | 12 +
> 66 files changed, 8288 insertions(+)
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dec
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dec
> create mode 100644 Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
> create mode 100644 Silicon/SiFive/SiFive.dec
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.fdf.inc
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
> create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.h
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.h
> create mode 100644 Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h
> create mode 100644 Platform/SiFive/U5SeriesPkg/Include/U5Clint.h
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.h
> create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h
> create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54.h
> create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Fv.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/MemDetect.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/OpensbiPlatformLib/Platform.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Fv.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/MemDetect.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c
> create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> create mode 100644 Platform/SiFive/U5SeriesPkg/Readme.md
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.uni
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500PkgExtra.uni
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.uni
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540PkgExtra.uni
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.S
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/U5SerialPortLib.uni
> create mode 100644 Platform/SiFive/U5SeriesPkg/U5SeriesPkg.uni
> create mode 100644 Platform/SiFive/U5SeriesPkg/U5SeriesPkgExtra.uni
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.uni
> create mode 100644 Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerExtra.uni
>
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [edk2-devel] [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V
2019-11-26 15:22 ` [edk2-devel] [platform/devel-riscv-v2 PATCHv5 00/18] Initial version of RISC-V Leif Lindholm
@ 2019-12-22 6:09 ` Abner Chang
0 siblings, 0 replies; 23+ messages in thread
From: Abner Chang @ 2019-12-22 6:09 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
Hi Leif,
Thanks for reviewing all patches for edk2 and edk2-platform. I already addressed all comments and ready to rebase all changes and consolidate commits.
I already rebased edk2 repo (private one) to edk2-stable201911, will do the same thing on edk2-platform.
Will let open source community knows when I am ready to push those to edk2-staing and edk2-paltform on Tianocore Github.
Thanks and happy holidays to all.
Abner
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Tuesday, November 26, 2019 11:22 PM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Subject: Re: [edk2-devel] [platform/devel-riscv-v2 PATCHv5 00/18] Initial
> version of RISC-V
>
> Apart from the minor comments I've made, and the fallout from header
> wrapper changes, I think this is ready to go into a -devel branch.
>
> I still think the SMBIOS generation code needs to be consolidated, but sure,
> let's do that once the code is in the branch.
>
> Regards,
>
> Leif
>
> On Mon, Oct 28, 2019 at 12:20:15 +0800, Abner Chang wrote:
> > The is the set of patches for belwo two platforms,
> > - SiFive Freedom U500 VC707 FPGA Dev Kit
> > - SiFive Freedom U540 HiFive Unleashed development board Refer to
> > Readme.md under platforms/SiFive/U5SeriesPkg.
> >
> > These patches have to be incorporated with RISC-V-V2 pacth v3 of edk2-
> staging.
> >
> > Besides of patches, you can also get code from belwo git repository.
> > - edk2-platforms for RISC-V platform,
> > https://github.com/gilbert225/edk2-platforms/tree/devel-riscv-v2-PATCH
> > v5
> > - edk2-staging for RISC-V,
> > https://github.com/changab/edk2-staging-riscv/tree/RISC-V-V2-v3
> >
> > Abner Chang (18):
> > Silicon/SiFive: Initial version of SiFive silicon package.
> > SiFive/E51: Initial version of SiFive E51 core library.
> > SiFive/U54: Initial version of SiFive U54 core library.
> > SiFive/U54MC: Initial version of SiFive U54MC Coreplex library.
> > U5SeriesPkg/PeiCoreInfoHobLib: Library to create core information.
> > U5SeriesPkg/TimerDxe: U5 Series Platform Timer DXE driver.
> > U5SeriesPkg/RamFvbServicesRuntimeDxe: Firmware Volume Block
> service.
> > U5SeriesPkg/RiscVPlatformTimerLib: Platform Timer library
> > U5SeriesPkg/SerialIoLib: Platform Serial Port library
> > FreedomU540HiFiveUnleashedBoard/PlatformPei: Platform PEI for U540
> > platform.
> > FreedomU540HiFiveUnleashedBoard/OpensbiPlatformLib: OpenSBI
> platform
> > library for U540 platform.
> > U5SeriesPkg/FreedomU540HiFiveUnleashedBoard: Add SiFive U540
> platform.
> > FreedomU500VC707Board/PlatformPei: Platform initialization PEI module.
> > FreedomU500VC707Board/OpensbiPlatformLib: OpenSBI platform
> interface.
> > U5SeriesPkg/FreedomU500VC707Board: Add SiFive U500 platform.
> > SiFive/U5SeriesPkg Add U5SeriesPkg.
> > edk2-platforms: Update Readme.md for RISC-V platform.
> > edk2-platforms: Update Maintainers file.
> >
> > .../U5SeriesPkg/FreedomU500VC707Board/U500.dec | 25 +
> > .../FreedomU540HiFiveUnleashedBoard/U540.dec | 25 +
> > Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec | 33 +
> > Silicon/SiFive/SiFive.dec | 39 +
> > .../U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 543 ++++++++++
> > .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 543 ++++++++++
> > .../U5SeriesPkg/FreedomU500VC707Board/U500.fdf | 336 ++++++
> > .../FreedomU540HiFiveUnleashedBoard/U540.fdf | 336 ++++++
> > .../U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc | 55 +
> > .../FreedomU500VC707Board/VarStore.fdf.inc | 78 ++
> > .../FreedomU540HiFiveUnleashedBoard/U540.fdf.inc | 54 +
> > .../VarStore.fdf.inc | 78 ++
> > .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 52 +
> > .../Universal/Pei/PlatformPei/PlatformPei.inf | 73 ++
> > .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 52 +
> > .../Universal/Pei/PlatformPei/PlatformPei.inf | 72 ++
> > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 58 +
> > .../RiscVPlatformTimerLib.inf | 36 +
> > .../Library/SerialIoLib/SerialIoLib.inf | 38 +
> > .../FvbServicesRuntimeDxe.inf | 80 ++
> > .../Universal/Dxe/TimerDxe/TimerDxe.inf | 53 +
> > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 47 +
> > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 48 +
> > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 46 +
> > .../Universal/Pei/PlatformPei/Platform.h | 86 ++
> > .../Universal/Pei/PlatformPei/Platform.h | 86 ++
> > .../U5SeriesPkg/Include/SiFiveU5MCCoreplex.h | 51 +
> > Platform/SiFive/U5SeriesPkg/Include/U5Clint.h | 20 +
> > .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h | 187 ++++
> > .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.h | 85 ++
> > .../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.h | 174 +++
> > Silicon/SiFive/Include/Library/SiFiveE51.h | 60 ++
> > Silicon/SiFive/Include/Library/SiFiveU54.h | 60 ++
> > .../SiFive/Include/Library/SiFiveU54MCCoreplex.h | 55 +
> > .../Library/OpensbiPlatformLib/Platform.c | 213 ++++
> > .../Universal/Pei/PlatformPei/Fv.c | 51 +
> > .../Universal/Pei/PlatformPei/MemDetect.c | 74 ++
> > .../Universal/Pei/PlatformPei/Platform.c | 310 ++++++
> > .../Library/OpensbiPlatformLib/Platform.c | 213 ++++
> > .../Universal/Pei/PlatformPei/Fv.c | 51 +
> > .../Universal/Pei/PlatformPei/MemDetect.c | 74 ++
> > .../Universal/Pei/PlatformPei/Platform.c | 310 ++++++
> > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 195 ++++
> > .../Library/SerialIoLib/SerialPortLib.c | 253 +++++
> > .../Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c | 127 +++
> > .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c | 1114
> ++++++++++++++++++++
> > .../RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c | 150 +++
> > .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.c | 145 +++
> > .../Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c | 20 +
> > .../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c | 304 ++++++
> > .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 242 +++++
> > .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 290 +++++
> > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 184 ++++
> > Platform/SiFive/U5SeriesPkg/Readme.md | 110 ++
> > Readme.md | 13 +
> > Maintainers.txt | 16 +
> > .../U5SeriesPkg/FreedomU500VC707Board/U500.uni | 13 +
> > .../FreedomU500VC707Board/U500PkgExtra.uni | 12 +
> > .../FreedomU540HiFiveUnleashedBoard/U540.uni | 13 +
> > .../U540PkgExtra.uni | 12 +
> > .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.S | 48 +
> > .../Library/SerialIoLib/U5SerialPortLib.uni | 16 +
> > Platform/SiFive/U5SeriesPkg/U5SeriesPkg.uni | 13 +
> > Platform/SiFive/U5SeriesPkg/U5SeriesPkgExtra.uni | 12 +
> > .../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.uni | 14 +
> > .../Universal/Dxe/TimerDxe/TimerExtra.uni | 12 +
> > 66 files changed, 8288 insertions(+)
> > create mode 100644
> > Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dec
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.de
> c
> > create mode 100644 Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
> > create mode 100644 Silicon/SiFive/SiFive.dec create mode 100644
> > Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
> > create mode 100644
> > Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
> > create mode 100644
> > Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
> > create mode 100644
> > Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
> .i
> > nc create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore
> .f
> > df.inc create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlat
> f
> > ormLib/OpensbiPlatformLib.inf create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/Platf
> o
> > rmPei/PlatformPei.inf create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/
> Op
> > ensbiPlatformLib/OpensbiPlatformLib.inf
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universa
> l/
> > Pei/PlatformPei/PlatformPei.inf create mode 100644
> > Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLi
> > b.inf create mode 100644
> > Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatfor
> > mTimerLib.inf create mode 100644
> > Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialIoLib.inf
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/Fv
> b
> > ServicesRuntimeDxe.inf create mode 100644
> > Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
> > create mode 100644
> > Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> > create mode 100644
> > Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> > create mode 100644
> >
> Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobL
> > ib.inf create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/Platf
> o
> > rmPei/Platform.h create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universa
> l/
> > Pei/PlatformPei/Platform.h create mode 100644
> > Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h
> > create mode 100644 Platform/SiFive/U5SeriesPkg/Include/U5Clint.h
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/F
> wB
> > lockService.h create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/R
> am
> > Flash.h create mode 100644
> > Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.h
> > create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h
> > create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54.h
> > create mode 100644
> > Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlat
> f
> > ormLib/Platform.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/Platf
> o
> > rmPei/Fv.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/Platf
> o
> > rmPei/MemDetect.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/Platf
> o
> > rmPei/Platform.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/
> Op
> > ensbiPlatformLib/Platform.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universa
> l/
> > Pei/PlatformPei/Fv.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universa
> l/
> > Pei/PlatformPei/MemDetect.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universa
> l/
> > Pei/PlatformPei/Platform.c create mode 100644
> > Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> > create mode 100644
> > Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/Fv
> b
> > Info.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/F
> wB
> > lockService.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/F
> wB
> > lockServiceDxe.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/R
> am
> > Flash.c create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/R
> am
> > FlashDxe.c create mode 100644
> > Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c
> > create mode 100644
> > Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> > create mode 100644
> > Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> > create mode 100644
> > Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
> > create mode 100644 Platform/SiFive/U5SeriesPkg/Readme.md
> > create mode 100644
> > Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.uni
> > create mode 100644
> > Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500PkgExtra.uni
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.uni
> > create mode 100644
> >
> Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540Pkg
> Ext
> > ra.uni create mode 100644
> > Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatfor
> > mTimerLib.S create mode 100644
> > Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/U5SerialPortLib.uni
> > create mode 100644 Platform/SiFive/U5SeriesPkg/U5SeriesPkg.uni
> > create mode 100644 Platform/SiFive/U5SeriesPkg/U5SeriesPkgExtra.uni
> > create mode 100644
> > Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.uni
> > create mode 100644
> > Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerExtra.uni
> >
> > --
> > 2.7.4
> >
> >
> >
> >
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread