From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.2348.1572238382439614517 for ; Sun, 27 Oct 2019 21:53:02 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=02044412f4=abner.chang@hpe.com) Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9S4pdA1005877; Mon, 28 Oct 2019 04:53:02 GMT Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0a-002e3701.pphosted.com with ESMTP id 2vvyrfnan4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 04:53:02 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 55E4A59; Mon, 28 Oct 2019 04:53:01 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 4C9A74B; Mon, 28 Oct 2019 04:52:59 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Michael D Kinney , Ard Biesheuvel , Leif Lindholm , Gilbert Chen , Palmer Dabbelt Subject: [platform/devel-riscv-v2 PATCHv5 14/18] FreedomU500VC707Board/OpensbiPlatformLib: OpenSBI platform interface. Date: Mon, 28 Oct 2019 12:20:29 +0800 Message-Id: <1572236433-15404-15-git-send-email-abner.chang@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572236433-15404-1-git-send-email-abner.chang@hpe.com> References: <1572236433-15404-1-git-send-email-abner.chang@hpe.com> X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-28_01:2019-10-25,2019-10-28 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 phishscore=0 clxscore=1015 suspectscore=13 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1910280047 This is OpenSBI platform code implementation of U500 platform. Signed-off-by: Abner Chang Cc: Michael D Kinney Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Gilbert Chen Cc: Palmer Dabbelt Signed-off-by: Abner Chang --- .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 52 +++++ .../Library/OpensbiPlatformLib/Platform.c | 213 +++++++++++++++++++++ 2 files changed, 265 insertions(+) create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf new file mode 100644 index 0000000..60aec6d --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf @@ -0,0 +1,52 @@ +## @file +# RISC-V OpenSBI Platform Library +# This is the the library which provides platform +# level opensbi functions follow RISC-V OpenSBI implementation. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = RiscVOpensbiPlatformLib + FILE_GUID = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = RiscVOpensbiPlatformLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + Platform.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec + RiscVPlatformPkg/RiscVPlatformPkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DebugAgentLib + FdtLib + PcdLib + PrintLib + RiscVCpuLib + +[FixedPcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize + + gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c new file mode 100644 index 0000000..bcdb643 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c @@ -0,0 +1,213 @@ +/* + * + * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.
+ * + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define U500_HART_COUNT FixedPcdGet32(PcdHartCount) +#define U500_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize) +#define U500_BOOT_HART_ID FixedPcdGet32(PcdBootHartId) + +#define U500_SYS_CLK 100000000 + +#define U500_PLIC_ADDR 0xc000000 +#define U500_PLIC_NUM_SOURCES 0x35 +#define U500_PLIC_NUM_PRIORITIES 7 + +#define U500_UART_ADDR FixedPcdGet32(PcdU5UartBase) + +#define U500_UART_BAUDRATE 115200 + +/** + * The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode. + * HARTs 1 is selected as boot HART + */ +#ifndef U500_ENABLED_HART_MASK +#define U500_ENABLED_HART_MASK (1 << U500_BOOT_HART_ID) +#endif + +#define U500_HARTID_DISABLED ~(U500_ENABLED_HART_MASK) + +/* PRCI clock related macros */ +//TODO: Do we need a separate driver for this ? +#define U500_PRCI_BASE_ADDR 0x10000000 +#define U500_PRCI_CLKMUXSTATUSREG 0x002C +#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1) + +static void U500_modify_dt(void *fdt) +{ + u32 i, size; + int chosen_offset, err; + int cpu_offset; + char cpu_node[32] = ""; + const char *mmu_type; + + for (i = 0; i < U500_HART_COUNT; i++) { + sbi_sprintf(cpu_node, "/cpus/cpu@%d", i); + cpu_offset = fdt_path_offset(fdt, cpu_node); + mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL); + if (mmu_type && (!AsciiStrCmp(mmu_type, "riscv,sv39") || + !AsciiStrCmp(mmu_type,"riscv,sv48"))) + continue; + else + fdt_setprop_string(fdt, cpu_offset, "status", "masked"); + memset(cpu_node, 0, sizeof(cpu_node)); + } + size = fdt_totalsize(fdt); + err = fdt_open_into(fdt, fdt, size + 256); + if (err < 0) + sbi_printf("Device Tree can't be expanded to accmodate new node"); + + chosen_offset = fdt_path_offset(fdt, "/chosen"); + fdt_setprop_string(fdt, chosen_offset, "stdout-path", + "/soc/serial@10010000:115200"); + + plic_fdt_fixup(fdt, "riscv,plic0"); +} + +static int U500_final_init(bool cold_boot) +{ + void *fdt; + + if (!cold_boot) + return 0; + + fdt = sbi_scratch_thishart_arg1_ptr(); + U500_modify_dt(fdt); + + return 0; +} + +static u32 U500_pmp_region_count(u32 hartid) +{ + return 1; +} + +static int U500_pmp_region_info(u32 hartid, u32 index, + ulong *prot, ulong *addr, ulong *log2size) +{ + int ret = 0; + + switch (index) { + case 0: + *prot = PMP_R | PMP_W | PMP_X; + *addr = 0; + *log2size = __riscv_xlen; + break; + default: + ret = -1; + break; + }; + + return ret; +} + +static int U500_console_init(void) +{ + unsigned long peri_in_freq; + + peri_in_freq = U500_SYS_CLK/2; + return sifive_uart_init(U500_UART_ADDR, peri_in_freq, U500_UART_BAUDRATE); +} + +static int U500_irqchip_init(bool cold_boot) +{ + int rc; + u32 hartid = sbi_current_hartid(); + + if (cold_boot) { + rc = plic_cold_irqchip_init(U500_PLIC_ADDR, + U500_PLIC_NUM_SOURCES, + U500_HART_COUNT); + if (rc) + return rc; + } + + return plic_warm_irqchip_init(hartid, + (hartid) ? (2 * hartid - 1) : 0, + (hartid) ? (2 * hartid) : -1); +} + +static int U500_ipi_init(bool cold_boot) +{ + int rc; + + if (cold_boot) { + rc = clint_cold_ipi_init(CLINT_REG_BASE_ADDR, + U500_HART_COUNT); + if (rc) + return rc; + + } + + return clint_warm_ipi_init(); +} + +static int U500_timer_init(bool cold_boot) +{ + int rc; + + if (cold_boot) { + rc = clint_cold_timer_init(CLINT_REG_BASE_ADDR, + U500_HART_COUNT); + if (rc) + return rc; + } + + return clint_warm_timer_init(); +} + +static int U500_system_down(u32 type) +{ + /* For now nothing to do. */ + return 0; +} + +const struct sbi_platform_operations platform_ops = { + .pmp_region_count = U500_pmp_region_count, + .pmp_region_info = U500_pmp_region_info, + .final_init = U500_final_init, + .console_putc = sifive_uart_putc, + .console_getc = sifive_uart_getc, + .console_init = U500_console_init, + .irqchip_init = U500_irqchip_init, + .ipi_send = clint_ipi_send, + .ipi_clear = clint_ipi_clear, + .ipi_init = U500_ipi_init, + .timer_value = clint_timer_value, + .timer_event_stop = clint_timer_event_stop, + .timer_event_start = clint_timer_event_start, + .timer_init = U500_timer_init, + .system_reboot = U500_system_down, + .system_shutdown = U500_system_down +}; + +const struct sbi_platform platform = { + .opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on. + .platform_version = SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI Platform version 1.0 + .name = "SiFive Freedom U500", + .features = SBI_PLATFORM_DEFAULT_FEATURES, + .hart_count = U500_HART_COUNT, + .hart_stack_size = U500_HART_STACK_SIZE, + .disabled_hart_mask = U500_HARTID_DISABLED, + .platform_ops_addr = (unsigned long)&platform_ops +}; -- 2.7.4